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gerrit-public.fairphone.software / kernel / msm / 166353bd75587a2158d713af1b9489a79e0ce297 / . / arch / arm / mach-omap2 / prcm.c
blob: 2eca8475d39671f6c295066075722d9e038c0074 [file] [log] [blame]
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
Abhijit Pagare37903002010-01-26 20:12:51 -0700[diff] [blame]14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]23#include <linux/io.h>
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]24#include <linux/delay.h>
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]25
Tony Lindgrence491cf2009-10-20 09:40:47 -0700[diff] [blame]26#include <plat/common.h>
27#include <plat/prcm.h>
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]28#include <plat/irqs.h>
Paul Walmsley44595982008-03-18 10:04:51 +0200[diff] [blame]29
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]30#include "clock.h"
Paul Walmsleyfeec1272010-01-26 20:13:11 -0700[diff] [blame]31#include "clock2xxx.h"
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]32#include "cm.h"
Paul Walmsley44595982008-03-18 10:04:51 +0200[diff] [blame]33#include "prm.h"
34#include "prm-regbits-24xx.h"
Rajeev Kulkarniff4d3e12010-09-21 10:34:09 -0600[diff] [blame]35#include "prm-regbits-44xx.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -0600[diff] [blame]36#include "control.h"
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]37
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]38static void __iomem *prm_base;
39static void __iomem *cm_base;
Rajendra Nayak9ef89152009-12-08 18:24:49 -0700[diff] [blame]40static void __iomem *cm2_base;
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]41
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]42#define MAX_MODULE_ENABLE_WAIT 100000
43
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]44struct omap3_prcm_regs {
45 u32 control_padconf_sys_nirq;
Jouni Hogander133464d2009-02-05 13:34:01 +0200[diff] [blame]46 u32 iva2_cm_clksel1;
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]47 u32 iva2_cm_clksel2;
48 u32 cm_sysconfig;
49 u32 sgx_cm_clksel;
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]50 u32 dss_cm_clksel;
51 u32 cam_cm_clksel;
52 u32 per_cm_clksel;
53 u32 emu_cm_clksel;
54 u32 emu_cm_clkstctrl;
55 u32 pll_cm_autoidle2;
56 u32 pll_cm_clksel4;
57 u32 pll_cm_clksel5;
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]58 u32 pll_cm_clken2;
59 u32 cm_polctrl;
60 u32 iva2_cm_fclken;
61 u32 iva2_cm_clken_pll;
62 u32 core_cm_fclken1;
63 u32 core_cm_fclken3;
64 u32 sgx_cm_fclken;
65 u32 wkup_cm_fclken;
66 u32 dss_cm_fclken;
67 u32 cam_cm_fclken;
68 u32 per_cm_fclken;
69 u32 usbhost_cm_fclken;
70 u32 core_cm_iclken1;
71 u32 core_cm_iclken2;
72 u32 core_cm_iclken3;
73 u32 sgx_cm_iclken;
74 u32 wkup_cm_iclken;
75 u32 dss_cm_iclken;
76 u32 cam_cm_iclken;
77 u32 per_cm_iclken;
78 u32 usbhost_cm_iclken;
79 u32 iva2_cm_autiidle2;
80 u32 mpu_cm_autoidle2;
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]81 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl;
84 u32 sgx_cm_clkstctrl;
85 u32 dss_cm_clkstctrl;
86 u32 cam_cm_clkstctrl;
87 u32 per_cm_clkstctrl;
88 u32 neon_cm_clkstctrl;
89 u32 usbhost_cm_clkstctrl;
90 u32 core_cm_autoidle1;
91 u32 core_cm_autoidle2;
92 u32 core_cm_autoidle3;
93 u32 wkup_cm_autoidle;
94 u32 dss_cm_autoidle;
95 u32 cam_cm_autoidle;
96 u32 per_cm_autoidle;
97 u32 usbhost_cm_autoidle;
98 u32 sgx_cm_sleepdep;
99 u32 dss_cm_sleepdep;
100 u32 cam_cm_sleepdep;
101 u32 per_cm_sleepdep;
102 u32 usbhost_cm_sleepdep;
103 u32 cm_clkout_ctrl;
104 u32 prm_clkout_ctrl;
105 u32 sgx_pm_wkdep;
106 u32 dss_pm_wkdep;
107 u32 cam_pm_wkdep;
108 u32 per_pm_wkdep;
109 u32 neon_pm_wkdep;
110 u32 usbhost_pm_wkdep;
111 u32 core_pm_mpugrpsel1;
112 u32 iva2_pm_ivagrpsel1;
113 u32 core_pm_mpugrpsel3;
114 u32 core_pm_ivagrpsel3;
115 u32 wkup_pm_mpugrpsel;
116 u32 wkup_pm_ivagrpsel;
117 u32 per_pm_mpugrpsel;
118 u32 per_pm_ivagrpsel;
119 u32 wkup_pm_wken;
120};
121
Manjunath Kondaiah G38815732010-10-08 09:56:37 -0700[diff] [blame]122static struct omap3_prcm_regs prcm_context;
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]123
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]124u32 omap_prcm_get_reset_sources(void)
125{
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]126 /* XXX This presumably needs modification for 34XX */
Rajendra Nayak766d3052010-03-31 04:16:30 -0600[diff] [blame]127 if (cpu_is_omap24xx() || cpu_is_omap34xx())
Abhijit Pagare37903002010-01-26 20:12:51 -0700[diff] [blame]128 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
129 if (cpu_is_omap44xx())
130 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
Kevin Hilman0cc93142010-02-24 12:05:56 -0700[diff] [blame]131
132 return 0;
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]133}
134EXPORT_SYMBOL(omap_prcm_get_reset_sources);
135
136/* Resets clock rates and reboots the system. Only called from system.h */
Aaro Koskinen29b9a212010-02-26 10:25:28 +0000[diff] [blame]137void omap_prcm_arch_reset(char mode, const char *cmd)
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]138{
Kevin Hilman0cc93142010-02-24 12:05:56 -0700[diff] [blame]139 s16 prcm_offs = 0;
Paul Walmsley44595982008-03-18 10:04:51 +0200[diff] [blame]140
Paul Walmsleyfeec1272010-01-26 20:13:11 -0700[diff] [blame]141 if (cpu_is_omap24xx()) {
142 omap2xxx_clk_prepare_for_reboot();
143
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]144 prcm_offs = WKUP_MOD;
Paul Walmsleyfeec1272010-01-26 20:13:11 -0700[diff] [blame]145 } else if (cpu_is_omap34xx()) {
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]146 prcm_offs = OMAP3430_GR_MOD;
Paul Walmsley166353b2010-12-21 20:01:21 -0700[diff] [blame^]147 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
Abhijit Pagare37903002010-01-26 20:12:51 -0700[diff] [blame]148 } else if (cpu_is_omap44xx())
149 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
150 else
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]151 WARN_ON(1);
152
Rajendra Nayak766d3052010-03-31 04:16:30 -0600[diff] [blame]153 if (cpu_is_omap24xx() || cpu_is_omap34xx())
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600[diff] [blame]154 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
Abhijit Pagare37903002010-01-26 20:12:51 -0700[diff] [blame]155 OMAP2_RM_RSTCTRL);
156 if (cpu_is_omap44xx())
Rajeev Kulkarniff4d3e12010-09-21 10:34:09 -0600[diff] [blame]157 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
158 prcm_offs, OMAP4_RM_RSTCTRL);
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100[diff] [blame]159}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]160
161static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
162{
163 BUG_ON(!base);
164 return __raw_readl(base + module + reg);
165}
166
167static inline void __omap_prcm_write(u32 value, void __iomem *base,
168 s16 module, u16 reg)
169{
170 BUG_ON(!base);
171 __raw_writel(value, base + module + reg);
172}
173
174/* Read a register in a PRM module */
175u32 prm_read_mod_reg(s16 module, u16 idx)
176{
177 return __omap_prcm_read(prm_base, module, idx);
178}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]179
180/* Write into a register in a PRM module */
181void prm_write_mod_reg(u32 val, s16 module, u16 idx)
182{
183 __omap_prcm_write(val, prm_base, module, idx);
184}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]185
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]186/* Read-modify-write a register in a PRM module. Caller must lock */
187u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
188{
189 u32 v;
190
191 v = prm_read_mod_reg(module, idx);
192 v &= ~mask;
193 v |= bits;
194 prm_write_mod_reg(v, module, idx);
195
196 return v;
197}
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]198
Paul Walmsley55ed9692010-01-26 20:12:59 -0700[diff] [blame]199/* Read a PRM register, AND it, and shift the result down to bit 0 */
200u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
201{
202 u32 v;
203
204 v = prm_read_mod_reg(domain, idx);
205 v &= mask;
206 v >>= __ffs(mask);
207
208 return v;
209}
210
Benoit Cousson16b04012010-09-21 10:34:10 -0600[diff] [blame]211/* Read a PRM register, AND it, and shift the result down to bit 0 */
212u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
213{
214 u32 v;
215
216 v = __raw_readl(reg);
217 v &= mask;
218 v >>= __ffs(mask);
219
220 return v;
221}
222
223/* Read-modify-write a register in a PRM module. Caller must lock */
224u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
225{
226 u32 v;
227
228 v = __raw_readl(reg);
229 v &= ~mask;
230 v |= bits;
231 __raw_writel(v, reg);
232
233 return v;
234}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]235/* Read a register in a CM module */
236u32 cm_read_mod_reg(s16 module, u16 idx)
237{
238 return __omap_prcm_read(cm_base, module, idx);
239}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]240
241/* Write into a register in a CM module */
242void cm_write_mod_reg(u32 val, s16 module, u16 idx)
243{
244 __omap_prcm_write(val, cm_base, module, idx);
245}
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]246
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]247/* Read-modify-write a register in a CM module. Caller must lock */
248u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
249{
250 u32 v;
251
252 v = cm_read_mod_reg(module, idx);
253 v &= ~mask;
254 v |= bits;
255 cm_write_mod_reg(v, module, idx);
256
257 return v;
258}
Tony Lindgrenff00fcc2008-07-03 12:24:44 +0300[diff] [blame]259
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]260/**
261 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
262 * @reg: physical address of module IDLEST register
263 * @mask: value to mask against to determine if the module is active
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700[diff] [blame]264 * @idlest: idle state indicator (0 or 1) for the clock
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]265 * @name: name of the clock (for printk)
266 *
267 * Returns 1 if the module indicated readiness in time, or 0 if it
268 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
269 */
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700[diff] [blame]270int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
271 const char *name)
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]272{
273 int i = 0;
274 int ena = 0;
275
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700[diff] [blame]276 if (idlest)
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]277 ena = 0;
278 else
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700[diff] [blame]279 ena = mask;
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]280
281 /* Wait for lock */
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]282 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
283 MAX_MODULE_ENABLE_WAIT, i);
Paul Walmsley72350b22009-07-24 19:44:03 -0600[diff] [blame]284
285 if (i < MAX_MODULE_ENABLE_WAIT)
286 pr_debug("cm: Module associated with clock %s ready after %d "
287 "loops\n", name, i);
288 else
289 pr_err("cm: Module associated with clock %s didn't enable in "
290 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
291
292 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
293};
294
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]295void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
296{
Santosh Shilimkarb7ebb102010-02-15 18:03:37 +0530[diff] [blame]297 /* Static mapping, never released */
298 if (omap2_globals->prm) {
299 prm_base = ioremap(omap2_globals->prm, SZ_8K);
300 WARN_ON(!prm_base);
301 }
302 if (omap2_globals->cm) {
303 cm_base = ioremap(omap2_globals->cm, SZ_8K);
304 WARN_ON(!cm_base);
305 }
306 if (omap2_globals->cm2) {
307 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
308 WARN_ON(!cm2_base);
309 }
Tony Lindgrena58caad2008-07-03 12:24:44 +0300[diff] [blame]310}
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]311
312#ifdef CONFIG_ARCH_OMAP3
313void omap3_prcm_save_context(void)
314{
315 prcm_context.control_padconf_sys_nirq =
316 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
Jouni Hogander133464d2009-02-05 13:34:01 +0200[diff] [blame]317 prcm_context.iva2_cm_clksel1 =
318 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]319 prcm_context.iva2_cm_clksel2 =
320 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
321 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
322 prcm_context.sgx_cm_clksel =
323 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]324 prcm_context.dss_cm_clksel =
325 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
326 prcm_context.cam_cm_clksel =
327 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
328 prcm_context.per_cm_clksel =
329 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
330 prcm_context.emu_cm_clksel =
331 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
332 prcm_context.emu_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]333 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]334 prcm_context.pll_cm_autoidle2 =
335 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
336 prcm_context.pll_cm_clksel4 =
337 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
338 prcm_context.pll_cm_clksel5 =
339 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]340 prcm_context.pll_cm_clken2 =
341 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
342 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
343 prcm_context.iva2_cm_fclken =
344 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
345 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
346 OMAP3430_CM_CLKEN_PLL);
347 prcm_context.core_cm_fclken1 =
348 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
349 prcm_context.core_cm_fclken3 =
350 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
351 prcm_context.sgx_cm_fclken =
352 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
353 prcm_context.wkup_cm_fclken =
354 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
355 prcm_context.dss_cm_fclken =
356 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
357 prcm_context.cam_cm_fclken =
358 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
359 prcm_context.per_cm_fclken =
360 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
361 prcm_context.usbhost_cm_fclken =
362 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
363 prcm_context.core_cm_iclken1 =
364 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
365 prcm_context.core_cm_iclken2 =
366 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
367 prcm_context.core_cm_iclken3 =
368 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
369 prcm_context.sgx_cm_iclken =
370 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
371 prcm_context.wkup_cm_iclken =
372 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
373 prcm_context.dss_cm_iclken =
374 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
375 prcm_context.cam_cm_iclken =
376 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
377 prcm_context.per_cm_iclken =
378 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
379 prcm_context.usbhost_cm_iclken =
380 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
381 prcm_context.iva2_cm_autiidle2 =
382 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
383 prcm_context.mpu_cm_autoidle2 =
384 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]385 prcm_context.iva2_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]386 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]387 prcm_context.mpu_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]388 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]389 prcm_context.core_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]390 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]391 prcm_context.sgx_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]392 cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
393 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]394 prcm_context.dss_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]395 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]396 prcm_context.cam_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]397 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]398 prcm_context.per_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]399 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]400 prcm_context.neon_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]401 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]402 prcm_context.usbhost_cm_clkstctrl =
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]403 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
404 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]405 prcm_context.core_cm_autoidle1 =
406 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
407 prcm_context.core_cm_autoidle2 =
408 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
409 prcm_context.core_cm_autoidle3 =
410 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
411 prcm_context.wkup_cm_autoidle =
412 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
413 prcm_context.dss_cm_autoidle =
414 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
415 prcm_context.cam_cm_autoidle =
416 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
417 prcm_context.per_cm_autoidle =
418 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
419 prcm_context.usbhost_cm_autoidle =
420 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
421 prcm_context.sgx_cm_sleepdep =
422 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
423 prcm_context.dss_cm_sleepdep =
424 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
425 prcm_context.cam_cm_sleepdep =
426 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
427 prcm_context.per_cm_sleepdep =
428 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
429 prcm_context.usbhost_cm_sleepdep =
430 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
431 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
432 OMAP3_CM_CLKOUT_CTRL_OFFSET);
433 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
434 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
435 prcm_context.sgx_pm_wkdep =
436 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
437 prcm_context.dss_pm_wkdep =
438 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
439 prcm_context.cam_pm_wkdep =
440 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
441 prcm_context.per_pm_wkdep =
442 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
443 prcm_context.neon_pm_wkdep =
444 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
445 prcm_context.usbhost_pm_wkdep =
446 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
447 prcm_context.core_pm_mpugrpsel1 =
448 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
449 prcm_context.iva2_pm_ivagrpsel1 =
450 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
451 prcm_context.core_pm_mpugrpsel3 =
452 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
453 prcm_context.core_pm_ivagrpsel3 =
454 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
455 prcm_context.wkup_pm_mpugrpsel =
456 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
457 prcm_context.wkup_pm_ivagrpsel =
458 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
459 prcm_context.per_pm_mpugrpsel =
460 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
461 prcm_context.per_pm_ivagrpsel =
462 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
463 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
464 return;
465}
466
467void omap3_prcm_restore_context(void)
468{
469 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
470 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
Jouni Hogander133464d2009-02-05 13:34:01 +0200[diff] [blame]471 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
472 CM_CLKSEL1);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]473 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
474 CM_CLKSEL2);
475 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
476 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
477 CM_CLKSEL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]478 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
479 CM_CLKSEL);
480 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
481 CM_CLKSEL);
482 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
483 CM_CLKSEL);
484 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
485 CM_CLKSEL1);
486 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]487 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]488 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
489 CM_AUTOIDLE2);
490 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
491 OMAP3430ES2_CM_CLKSEL4);
492 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
493 OMAP3430ES2_CM_CLKSEL5);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]494 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
495 OMAP3430ES2_CM_CLKEN2);
496 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
497 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
498 CM_FCLKEN);
499 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
500 OMAP3430_CM_CLKEN_PLL);
501 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
502 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
503 OMAP3430ES2_CM_FCLKEN3);
504 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
505 CM_FCLKEN);
506 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
507 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
508 CM_FCLKEN);
509 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
510 CM_FCLKEN);
511 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
512 CM_FCLKEN);
513 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
514 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
515 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
516 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
517 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
518 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
519 CM_ICLKEN);
520 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
521 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
522 CM_ICLKEN);
523 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
524 CM_ICLKEN);
525 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
526 CM_ICLKEN);
527 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
528 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
529 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
530 CM_AUTOIDLE2);
531 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]532 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]533 OMAP2_CM_CLKSTCTRL);
534 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
535 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]536 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]537 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]538 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]539 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]540 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]541 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]542 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]543 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]544 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]545 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]546 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]547 OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]548 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
Abhijit Pagare84c0c392010-01-26 20:12:53 -0700[diff] [blame]549 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
Rajendra Nayakc171a252008-09-26 17:48:31 +0530[diff] [blame]550 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
551 CM_AUTOIDLE1);
552 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
553 CM_AUTOIDLE2);
554 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
555 CM_AUTOIDLE3);
556 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
557 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
558 CM_AUTOIDLE);
559 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
560 CM_AUTOIDLE);
561 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
562 CM_AUTOIDLE);
563 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
564 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
565 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
566 OMAP3430_CM_SLEEPDEP);
567 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
568 OMAP3430_CM_SLEEPDEP);
569 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
570 OMAP3430_CM_SLEEPDEP);
571 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
572 OMAP3430_CM_SLEEPDEP);
573 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
574 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
575 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
576 OMAP3_CM_CLKOUT_CTRL_OFFSET);
577 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
578 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
579 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
580 PM_WKDEP);
581 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
582 PM_WKDEP);
583 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
584 PM_WKDEP);
585 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
586 PM_WKDEP);
587 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
588 PM_WKDEP);
589 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
590 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
591 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
592 OMAP3430_PM_MPUGRPSEL1);
593 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
594 OMAP3430_PM_IVAGRPSEL1);
595 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
596 OMAP3430ES2_PM_MPUGRPSEL3);
597 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
598 OMAP3430ES2_PM_IVAGRPSEL3);
599 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
600 OMAP3430_PM_MPUGRPSEL);
601 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
602 OMAP3430_PM_IVAGRPSEL);
603 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
604 OMAP3430_PM_MPUGRPSEL);
605 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
606 OMAP3430_PM_IVAGRPSEL);
607 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
608 return;
609}
610#endif