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gerrit-public.fairphone.software / kernel / msm / 170a46177094b390299d1206748d7f15cd375dc9 / . / arch / arm / mach-omap2 / clockdomains44xx.h
blob: 7e5ba0f679255de8b18a4f2f49d0b20be1bde40e [file] [log] [blame]
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]1/*
2 * OMAP4 Clock domains framework
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
Abhijit Pagare1a422722010-01-26 20:12:54 -0700[diff] [blame]21/*
22 * To-Do List
23 * -> Populate the Sleep/Wakeup dependencies for the domains
24 */
25
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]26#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
27#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
28
29#include <plat/clockdomain.h>
30
31#if defined(CONFIG_ARCH_OMAP4)
32
33static struct clockdomain l4_cefuse_44xx_clkdm = {
34 .name = "l4_cefuse_clkdm",
35 .pwrdm = { .name = "cefuse_pwrdm" },
36 .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
37 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
38 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
40};
41
42static struct clockdomain l4_cfg_44xx_clkdm = {
43 .name = "l4_cfg_clkdm",
44 .pwrdm = { .name = "core_pwrdm" },
45 .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
46 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
47 .flags = CLKDM_CAN_HWSUP,
48 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
49};
50
51static struct clockdomain tesla_44xx_clkdm = {
52 .name = "tesla_clkdm",
53 .pwrdm = { .name = "tesla_pwrdm" },
54 .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
55 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
56 .flags = CLKDM_CAN_HWSUP_SWSUP,
57 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
58};
59
60static struct clockdomain l3_gfx_44xx_clkdm = {
61 .name = "l3_gfx_clkdm",
62 .pwrdm = { .name = "gfx_pwrdm" },
63 .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
64 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
65 .flags = CLKDM_CAN_HWSUP_SWSUP,
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
67};
68
69static struct clockdomain ivahd_44xx_clkdm = {
70 .name = "ivahd_clkdm",
71 .pwrdm = { .name = "ivahd_pwrdm" },
72 .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
73 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
74 .flags = CLKDM_CAN_HWSUP_SWSUP,
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
76};
77
78static struct clockdomain l4_secure_44xx_clkdm = {
79 .name = "l4_secure_clkdm",
80 .pwrdm = { .name = "l4per_pwrdm" },
81 .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
82 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
83 .flags = CLKDM_CAN_HWSUP_SWSUP,
84 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
85};
86
87static struct clockdomain l4_per_44xx_clkdm = {
88 .name = "l4_per_clkdm",
89 .pwrdm = { .name = "l4per_pwrdm" },
90 .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
91 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
92 .flags = CLKDM_CAN_HWSUP_SWSUP,
93 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
94};
95
96static struct clockdomain abe_44xx_clkdm = {
97 .name = "abe_clkdm",
98 .pwrdm = { .name = "abe_pwrdm" },
99 .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
100 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
101 .flags = CLKDM_CAN_HWSUP_SWSUP,
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
103};
104
Abhijit Pagare6b04e0d2010-01-26 20:12:58 -0700[diff] [blame]105static struct clockdomain l3_instr_44xx_clkdm = {
106 .name = "l3_instr_clkdm",
107 .pwrdm = { .name = "core_pwrdm" },
108 .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL,
109 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
111};
112
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]113static struct clockdomain l3_init_44xx_clkdm = {
114 .name = "l3_init_clkdm",
115 .pwrdm = { .name = "l3init_pwrdm" },
116 .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
117 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
118 .flags = CLKDM_CAN_HWSUP_SWSUP,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
120};
121
122static struct clockdomain mpuss_44xx_clkdm = {
123 .name = "mpuss_clkdm",
124 .pwrdm = { .name = "mpu_pwrdm" },
125 .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
126 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
127 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
129};
130
131static struct clockdomain mpu0_44xx_clkdm = {
132 .name = "mpu0_clkdm",
133 .pwrdm = { .name = "cpu0_pwrdm" },
Benoit Cousson79328702010-05-20 12:31:11 -0600[diff] [blame]134 .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL,
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]135 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
136 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
138};
139
140static struct clockdomain mpu1_44xx_clkdm = {
141 .name = "mpu1_clkdm",
142 .pwrdm = { .name = "cpu1_pwrdm" },
Benoit Cousson79328702010-05-20 12:31:11 -0600[diff] [blame]143 .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL,
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]144 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
145 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
147};
148
149static struct clockdomain l3_emif_44xx_clkdm = {
150 .name = "l3_emif_clkdm",
151 .pwrdm = { .name = "core_pwrdm" },
152 .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
153 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
154 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
155 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
156};
157
158static struct clockdomain l4_ao_44xx_clkdm = {
159 .name = "l4_ao_clkdm",
160 .pwrdm = { .name = "always_on_core_pwrdm" },
161 .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
162 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
163 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
165};
166
167static struct clockdomain ducati_44xx_clkdm = {
168 .name = "ducati_clkdm",
169 .pwrdm = { .name = "core_pwrdm" },
170 .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
171 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
172 .flags = CLKDM_CAN_HWSUP_SWSUP,
173 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
174};
175
176static struct clockdomain l3_2_44xx_clkdm = {
177 .name = "l3_2_clkdm",
178 .pwrdm = { .name = "core_pwrdm" },
179 .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
180 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
181 .flags = CLKDM_CAN_HWSUP,
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
183};
184
185static struct clockdomain l3_1_44xx_clkdm = {
186 .name = "l3_1_clkdm",
187 .pwrdm = { .name = "core_pwrdm" },
188 .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
189 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
190 .flags = CLKDM_CAN_HWSUP,
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
192};
193
194static struct clockdomain l3_d2d_44xx_clkdm = {
195 .name = "l3_d2d_clkdm",
196 .pwrdm = { .name = "core_pwrdm" },
197 .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
198 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
199 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
201};
202
203static struct clockdomain iss_44xx_clkdm = {
204 .name = "iss_clkdm",
205 .pwrdm = { .name = "cam_pwrdm" },
206 .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
207 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
208 .flags = CLKDM_CAN_HWSUP_SWSUP,
209 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
210};
211
212static struct clockdomain l3_dss_44xx_clkdm = {
213 .name = "l3_dss_clkdm",
214 .pwrdm = { .name = "dss_pwrdm" },
215 .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
216 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
217 .flags = CLKDM_CAN_HWSUP_SWSUP,
218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
219};
220
221static struct clockdomain l4_wkup_44xx_clkdm = {
222 .name = "l4_wkup_clkdm",
223 .pwrdm = { .name = "wkup_pwrdm" },
224 .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
225 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
226 .flags = CLKDM_CAN_HWSUP,
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
228};
229
230static struct clockdomain emu_sys_44xx_clkdm = {
231 .name = "emu_sys_clkdm",
232 .pwrdm = { .name = "emu_pwrdm" },
233 .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
234 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
235 .flags = CLKDM_CAN_HWSUP,
236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
237};
238
239static struct clockdomain l3_dma_44xx_clkdm = {
240 .name = "l3_dma_clkdm",
241 .pwrdm = { .name = "core_pwrdm" },
242 .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
243 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
244 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
246};
247
248#endif
249
250#endif