blob: e5e172d21692d60a81fce6a9ed06e5807c57b370 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_platform.h>
37
38#include "fsldma.h"
39
Ira Snyderc14330412010-09-30 11:46:45 +000040static const char msg_ld_oom[] = "No free memory for link descriptor\n";
41
Ira Snydera1c03312010-01-06 13:34:05 +000042static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070043{
44 /* Reset the channel */
Ira Snydera1c03312010-01-06 13:34:05 +000045 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070046
Ira Snydera1c03312010-01-06 13:34:05 +000047 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -070048 case FSL_DMA_IP_85XX:
49 /* Set the channel to below modes:
50 * EIE - Error interrupt enable
51 * EOSIE - End of segments interrupt enable (basic mode)
52 * EOLNIE - End of links interrupt enable
Forrest Shif3c677b2010-12-09 16:14:04 +080053 * BWC - Bandwidth sharing among channels
Zhang Wei173acc72008-03-01 07:42:48 -070054 */
Forrest Shif3c677b2010-12-09 16:14:04 +080055 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
56 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
57 | FSL_DMA_MR_EOSIE, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070058 break;
59 case FSL_DMA_IP_83XX:
60 /* Set the channel to below modes:
61 * EOTIE - End-of-transfer interrupt enable
Ira W. Snydera7aea372009-04-23 16:17:54 -070062 * PRC_RM - PCI read multiple
Zhang Wei173acc72008-03-01 07:42:48 -070063 */
Ira Snydera1c03312010-01-06 13:34:05 +000064 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
Ira W. Snydera7aea372009-04-23 16:17:54 -070065 | FSL_DMA_MR_PRC_RM, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070066 break;
67 }
Zhang Wei173acc72008-03-01 07:42:48 -070068}
69
Ira Snydera1c03312010-01-06 13:34:05 +000070static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070071{
Ira Snydera1c03312010-01-06 13:34:05 +000072 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070073}
74
Ira Snydera1c03312010-01-06 13:34:05 +000075static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070076{
Ira Snydera1c03312010-01-06 13:34:05 +000077 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070078}
79
Ira Snydera1c03312010-01-06 13:34:05 +000080static void set_desc_cnt(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070081 struct fsl_dma_ld_hw *hw, u32 count)
82{
Ira Snydera1c03312010-01-06 13:34:05 +000083 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070084}
85
Ira Snydera1c03312010-01-06 13:34:05 +000086static void set_desc_src(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070087 struct fsl_dma_ld_hw *hw, dma_addr_t src)
88{
89 u64 snoop_bits;
90
Ira Snydera1c03312010-01-06 13:34:05 +000091 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070092 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +000093 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070094}
95
Ira Snydera1c03312010-01-06 13:34:05 +000096static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder738f5f72010-01-06 13:34:02 +000097 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -070098{
99 u64 snoop_bits;
100
Ira Snydera1c03312010-01-06 13:34:05 +0000101 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700102 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000103 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700104}
105
Ira Snydera1c03312010-01-06 13:34:05 +0000106static void set_desc_next(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700107 struct fsl_dma_ld_hw *hw, dma_addr_t next)
108{
109 u64 snoop_bits;
110
Ira Snydera1c03312010-01-06 13:34:05 +0000111 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700112 ? FSL_DMA_SNEN : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000113 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700114}
115
Ira Snydera1c03312010-01-06 13:34:05 +0000116static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -0700117{
Ira Snydera1c03312010-01-06 13:34:05 +0000118 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700119}
120
Ira Snydera1c03312010-01-06 13:34:05 +0000121static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700122{
Ira Snydera1c03312010-01-06 13:34:05 +0000123 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -0700124}
125
Ira Snydera1c03312010-01-06 13:34:05 +0000126static dma_addr_t get_ndar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700127{
Ira Snydera1c03312010-01-06 13:34:05 +0000128 return DMA_IN(chan, &chan->regs->ndar, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700129}
130
Ira Snydera1c03312010-01-06 13:34:05 +0000131static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -0700132{
Ira Snydera1c03312010-01-06 13:34:05 +0000133 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -0700134}
135
Ira Snydera1c03312010-01-06 13:34:05 +0000136static int dma_is_idle(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700137{
Ira Snydera1c03312010-01-06 13:34:05 +0000138 u32 sr = get_sr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700139 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
140}
141
Ira Snydera1c03312010-01-06 13:34:05 +0000142static void dma_start(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700143{
Ira Snyder272ca652010-01-06 13:33:59 +0000144 u32 mode;
Zhang Wei173acc72008-03-01 07:42:48 -0700145
Ira Snydera1c03312010-01-06 13:34:05 +0000146 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000147
Ira Snydera1c03312010-01-06 13:34:05 +0000148 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
149 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
150 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000151 mode |= FSL_DMA_MR_EMP_EN;
152 } else {
153 mode &= ~FSL_DMA_MR_EMP_EN;
154 }
Ira Snyder43a1a3e2009-05-28 09:26:40 +0000155 }
Zhang Wei173acc72008-03-01 07:42:48 -0700156
Ira Snydera1c03312010-01-06 13:34:05 +0000157 if (chan->feature & FSL_DMA_CHAN_START_EXT)
Ira Snyder272ca652010-01-06 13:33:59 +0000158 mode |= FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700159 else
Ira Snyder272ca652010-01-06 13:33:59 +0000160 mode |= FSL_DMA_MR_CS;
Zhang Wei173acc72008-03-01 07:42:48 -0700161
Ira Snydera1c03312010-01-06 13:34:05 +0000162 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700163}
164
Ira Snydera1c03312010-01-06 13:34:05 +0000165static void dma_halt(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700166{
Ira Snyder272ca652010-01-06 13:33:59 +0000167 u32 mode;
Dan Williams900325a2009-03-02 15:33:46 -0700168 int i;
169
Ira Snydera1c03312010-01-06 13:34:05 +0000170 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000171 mode |= FSL_DMA_MR_CA;
Ira Snydera1c03312010-01-06 13:34:05 +0000172 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000173
174 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
Ira Snydera1c03312010-01-06 13:34:05 +0000175 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700176
Dan Williams900325a2009-03-02 15:33:46 -0700177 for (i = 0; i < 100; i++) {
Ira Snydera1c03312010-01-06 13:34:05 +0000178 if (dma_is_idle(chan))
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000179 return;
180
Zhang Wei173acc72008-03-01 07:42:48 -0700181 udelay(10);
Dan Williams900325a2009-03-02 15:33:46 -0700182 }
Ira Snyder272ca652010-01-06 13:33:59 +0000183
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000184 if (!dma_is_idle(chan))
Ira Snydera1c03312010-01-06 13:34:05 +0000185 dev_err(chan->dev, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700186}
187
Ira Snydera1c03312010-01-06 13:34:05 +0000188static void set_ld_eol(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700189 struct fsl_desc_sw *desc)
190{
Ira Snyder776c8942009-05-15 11:33:20 -0700191 u64 snoop_bits;
192
Ira Snydera1c03312010-01-06 13:34:05 +0000193 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700194 ? FSL_DMA_SNEN : 0;
195
Ira Snydera1c03312010-01-06 13:34:05 +0000196 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
197 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700198 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700199}
200
Zhang Wei173acc72008-03-01 07:42:48 -0700201/**
202 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000203 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700204 * @size : Address loop size, 0 for disable loop
205 *
206 * The set source address hold transfer size. The source
207 * address hold or loop transfer size is when the DMA transfer
208 * data from source address (SA), if the loop size is 4, the DMA will
209 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
210 * SA + 1 ... and so on.
211 */
Ira Snydera1c03312010-01-06 13:34:05 +0000212static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700213{
Ira Snyder272ca652010-01-06 13:33:59 +0000214 u32 mode;
215
Ira Snydera1c03312010-01-06 13:34:05 +0000216 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000217
Zhang Wei173acc72008-03-01 07:42:48 -0700218 switch (size) {
219 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000220 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700221 break;
222 case 1:
223 case 2:
224 case 4:
225 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000226 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700227 break;
228 }
Ira Snyder272ca652010-01-06 13:33:59 +0000229
Ira Snydera1c03312010-01-06 13:34:05 +0000230 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700231}
232
233/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000234 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000235 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700236 * @size : Address loop size, 0 for disable loop
237 *
238 * The set destination address hold transfer size. The destination
239 * address hold or loop transfer size is when the DMA transfer
240 * data to destination address (TA), if the loop size is 4, the DMA will
241 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
242 * TA + 1 ... and so on.
243 */
Ira Snydera1c03312010-01-06 13:34:05 +0000244static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700245{
Ira Snyder272ca652010-01-06 13:33:59 +0000246 u32 mode;
247
Ira Snydera1c03312010-01-06 13:34:05 +0000248 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000249
Zhang Wei173acc72008-03-01 07:42:48 -0700250 switch (size) {
251 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000252 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700253 break;
254 case 1:
255 case 2:
256 case 4:
257 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000258 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700259 break;
260 }
Ira Snyder272ca652010-01-06 13:33:59 +0000261
Ira Snydera1c03312010-01-06 13:34:05 +0000262 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700263}
264
265/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700266 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000267 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700268 * @size : Number of bytes to transfer in a single request
269 *
270 * The Freescale DMA channel can be controlled by the external signal DREQ#.
271 * The DMA request count is how many bytes are allowed to transfer before
272 * pausing the channel, after which a new assertion of DREQ# resumes channel
273 * operation.
274 *
275 * A size of 0 disables external pause control. The maximum size is 1024.
276 */
Ira Snydera1c03312010-01-06 13:34:05 +0000277static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700278{
Ira Snyder272ca652010-01-06 13:33:59 +0000279 u32 mode;
280
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700281 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000282
Ira Snydera1c03312010-01-06 13:34:05 +0000283 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000284 mode |= (__ilog2(size) << 24) & 0x0f000000;
285
Ira Snydera1c03312010-01-06 13:34:05 +0000286 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700287}
288
289/**
Zhang Wei173acc72008-03-01 07:42:48 -0700290 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000291 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700292 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700293 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700294 * The Freescale DMA channel can be controlled by the external signal DREQ#.
295 * The DMA Request Count feature should be used in addition to this feature
296 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700297 */
Ira Snydera1c03312010-01-06 13:34:05 +0000298static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700299{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700300 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000301 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700302 else
Ira Snydera1c03312010-01-06 13:34:05 +0000303 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700304}
305
306/**
307 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000308 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700309 * @enable : 0 is disabled, 1 is enabled.
310 *
311 * If enable the external start, the channel can be started by an
312 * external DMA start pin. So the dma_start() does not start the
313 * transfer immediately. The DMA channel will wait for the
314 * control pin asserted.
315 */
Ira Snydera1c03312010-01-06 13:34:05 +0000316static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700317{
318 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000319 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700320 else
Ira Snydera1c03312010-01-06 13:34:05 +0000321 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700322}
323
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000324static void append_ld_queue(struct fsldma_chan *chan,
325 struct fsl_desc_sw *desc)
326{
327 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
328
329 if (list_empty(&chan->ld_pending))
330 goto out_splice;
331
332 /*
333 * Add the hardware descriptor to the chain of hardware descriptors
334 * that already exists in memory.
335 *
336 * This will un-set the EOL bit of the existing transaction, and the
337 * last link in this transaction will become the EOL descriptor.
338 */
339 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
340
341 /*
342 * Add the software descriptor and all children to the list
343 * of pending transactions
344 */
345out_splice:
346 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
347}
348
Zhang Wei173acc72008-03-01 07:42:48 -0700349static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
350{
Ira Snydera1c03312010-01-06 13:34:05 +0000351 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700352 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
353 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700354 unsigned long flags;
355 dma_cookie_t cookie;
356
Ira Snydera1c03312010-01-06 13:34:05 +0000357 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700358
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000359 /*
360 * assign cookies to all of the software descriptors
361 * that make up this transaction
362 */
Ira Snydera1c03312010-01-06 13:34:05 +0000363 cookie = chan->common.cookie;
Dan Williamseda34232009-09-08 17:53:02 -0700364 list_for_each_entry(child, &desc->tx_list, node) {
Ira Snyderbcfb7462009-05-15 14:27:16 -0700365 cookie++;
366 if (cookie < 0)
367 cookie = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700368
Steven J. Magnani6ca3a7a2010-02-25 13:39:30 -0600369 child->async_tx.cookie = cookie;
Ira Snyderbcfb7462009-05-15 14:27:16 -0700370 }
371
Ira Snydera1c03312010-01-06 13:34:05 +0000372 chan->common.cookie = cookie;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000373
374 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000375 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700376
Ira Snydera1c03312010-01-06 13:34:05 +0000377 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700378
379 return cookie;
380}
381
382/**
383 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000384 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700385 *
386 * Return - The descriptor allocated. NULL for failed.
387 */
388static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
Ira Snydera1c03312010-01-06 13:34:05 +0000389 struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700390{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000391 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700392 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700393
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000394 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
395 if (!desc) {
396 dev_dbg(chan->dev, "out of memory for link desc\n");
397 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700398 }
399
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000400 memset(desc, 0, sizeof(*desc));
401 INIT_LIST_HEAD(&desc->tx_list);
402 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
403 desc->async_tx.tx_submit = fsl_dma_tx_submit;
404 desc->async_tx.phys = pdesc;
405
406 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700407}
408
409
410/**
411 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000412 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700413 *
414 * This function will create a dma pool for descriptor allocation.
415 *
416 * Return - The number of descriptors allocated.
417 */
Ira Snydera1c03312010-01-06 13:34:05 +0000418static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700419{
Ira Snydera1c03312010-01-06 13:34:05 +0000420 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700421
422 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000423 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700424 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700425
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000426 /*
427 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700428 * for meeting FSL DMA specification requirement.
429 */
Ira Snydera1c03312010-01-06 13:34:05 +0000430 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000431 chan->dev,
432 sizeof(struct fsl_desc_sw),
433 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000434 if (!chan->desc_pool) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000435 dev_err(chan->dev, "unable to allocate channel %d "
436 "descriptor pool\n", chan->id);
437 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700438 }
439
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000440 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700441 return 1;
442}
443
444/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000445 * fsldma_free_desc_list - Free all descriptors in a queue
446 * @chan: Freescae DMA channel
447 * @list: the list to free
448 *
449 * LOCKING: must hold chan->desc_lock
450 */
451static void fsldma_free_desc_list(struct fsldma_chan *chan,
452 struct list_head *list)
453{
454 struct fsl_desc_sw *desc, *_desc;
455
456 list_for_each_entry_safe(desc, _desc, list, node) {
457 list_del(&desc->node);
458 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
459 }
460}
461
462static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
463 struct list_head *list)
464{
465 struct fsl_desc_sw *desc, *_desc;
466
467 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
468 list_del(&desc->node);
469 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
470 }
471}
472
473/**
Zhang Wei173acc72008-03-01 07:42:48 -0700474 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000475 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700476 */
Ira Snydera1c03312010-01-06 13:34:05 +0000477static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700478{
Ira Snydera1c03312010-01-06 13:34:05 +0000479 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700480 unsigned long flags;
481
Ira Snydera1c03312010-01-06 13:34:05 +0000482 dev_dbg(chan->dev, "Free all channel resources.\n");
483 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000484 fsldma_free_desc_list(chan, &chan->ld_pending);
485 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000486 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700487
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000488 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000489 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700490}
491
Zhang Wei2187c262008-03-13 17:45:28 -0700492static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000493fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700494{
Ira Snydera1c03312010-01-06 13:34:05 +0000495 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700496 struct fsl_desc_sw *new;
497
Ira Snydera1c03312010-01-06 13:34:05 +0000498 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700499 return NULL;
500
Ira Snydera1c03312010-01-06 13:34:05 +0000501 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700502
Ira Snydera1c03312010-01-06 13:34:05 +0000503 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700504 if (!new) {
Ira Snyderc14330412010-09-30 11:46:45 +0000505 dev_err(chan->dev, msg_ld_oom);
Zhang Wei2187c262008-03-13 17:45:28 -0700506 return NULL;
507 }
508
509 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700510 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700511
Zhang Weif79abb62008-03-18 18:45:00 -0700512 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700513 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700514
Zhang Wei2187c262008-03-13 17:45:28 -0700515 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000516 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700517
518 return &new->async_tx;
519}
520
Zhang Wei173acc72008-03-01 07:42:48 -0700521static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
Ira Snydera1c03312010-01-06 13:34:05 +0000522 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700523 size_t len, unsigned long flags)
524{
Ira Snydera1c03312010-01-06 13:34:05 +0000525 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700526 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
527 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700528
Ira Snydera1c03312010-01-06 13:34:05 +0000529 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700530 return NULL;
531
532 if (!len)
533 return NULL;
534
Ira Snydera1c03312010-01-06 13:34:05 +0000535 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700536
537 do {
538
539 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000540 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700541 if (!new) {
Ira Snyderc14330412010-09-30 11:46:45 +0000542 dev_err(chan->dev, msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700543 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700544 }
545#ifdef FSL_DMA_LD_DEBUG
Ira Snydera1c03312010-01-06 13:34:05 +0000546 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
Zhang Wei173acc72008-03-01 07:42:48 -0700547#endif
548
Zhang Wei56822842008-03-13 10:45:27 -0700549 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700550
Ira Snydera1c03312010-01-06 13:34:05 +0000551 set_desc_cnt(chan, &new->hw, copy);
552 set_desc_src(chan, &new->hw, dma_src);
553 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700554
555 if (!first)
556 first = new;
557 else
Ira Snydera1c03312010-01-06 13:34:05 +0000558 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700559
560 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700561 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700562
563 prev = new;
564 len -= copy;
565 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000566 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700567
568 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700569 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700570 } while (len);
571
Dan Williams636bdea2008-04-17 20:17:26 -0700572 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700573 new->async_tx.cookie = -EBUSY;
574
575 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000576 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700577
Ira Snyder2e077f82009-05-15 09:59:46 -0700578 return &first->async_tx;
579
580fail:
581 if (!first)
582 return NULL;
583
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000584 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700585 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700586}
587
Ira Snyderc14330412010-09-30 11:46:45 +0000588static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
589 struct scatterlist *dst_sg, unsigned int dst_nents,
590 struct scatterlist *src_sg, unsigned int src_nents,
591 unsigned long flags)
592{
593 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
594 struct fsldma_chan *chan = to_fsl_chan(dchan);
595 size_t dst_avail, src_avail;
596 dma_addr_t dst, src;
597 size_t len;
598
599 /* basic sanity checks */
600 if (dst_nents == 0 || src_nents == 0)
601 return NULL;
602
603 if (dst_sg == NULL || src_sg == NULL)
604 return NULL;
605
606 /*
607 * TODO: should we check that both scatterlists have the same
608 * TODO: number of bytes in total? Is that really an error?
609 */
610
611 /* get prepared for the loop */
612 dst_avail = sg_dma_len(dst_sg);
613 src_avail = sg_dma_len(src_sg);
614
615 /* run until we are out of scatterlist entries */
616 while (true) {
617
618 /* create the largest transaction possible */
619 len = min_t(size_t, src_avail, dst_avail);
620 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
621 if (len == 0)
622 goto fetch;
623
624 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
625 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
626
627 /* allocate and populate the descriptor */
628 new = fsl_dma_alloc_descriptor(chan);
629 if (!new) {
630 dev_err(chan->dev, msg_ld_oom);
631 goto fail;
632 }
633#ifdef FSL_DMA_LD_DEBUG
634 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
635#endif
636
637 set_desc_cnt(chan, &new->hw, len);
638 set_desc_src(chan, &new->hw, src);
639 set_desc_dst(chan, &new->hw, dst);
640
641 if (!first)
642 first = new;
643 else
644 set_desc_next(chan, &prev->hw, new->async_tx.phys);
645
646 new->async_tx.cookie = 0;
647 async_tx_ack(&new->async_tx);
648 prev = new;
649
650 /* Insert the link descriptor to the LD ring */
651 list_add_tail(&new->node, &first->tx_list);
652
653 /* update metadata */
654 dst_avail -= len;
655 src_avail -= len;
656
657fetch:
658 /* fetch the next dst scatterlist entry */
659 if (dst_avail == 0) {
660
661 /* no more entries: we're done */
662 if (dst_nents == 0)
663 break;
664
665 /* fetch the next entry: if there are no more: done */
666 dst_sg = sg_next(dst_sg);
667 if (dst_sg == NULL)
668 break;
669
670 dst_nents--;
671 dst_avail = sg_dma_len(dst_sg);
672 }
673
674 /* fetch the next src scatterlist entry */
675 if (src_avail == 0) {
676
677 /* no more entries: we're done */
678 if (src_nents == 0)
679 break;
680
681 /* fetch the next entry: if there are no more: done */
682 src_sg = sg_next(src_sg);
683 if (src_sg == NULL)
684 break;
685
686 src_nents--;
687 src_avail = sg_dma_len(src_sg);
688 }
689 }
690
691 new->async_tx.flags = flags; /* client is in control of this ack */
692 new->async_tx.cookie = -EBUSY;
693
694 /* Set End-of-link to the last link descriptor of new list */
695 set_ld_eol(chan, new);
696
697 return &first->async_tx;
698
699fail:
700 if (!first)
701 return NULL;
702
703 fsldma_free_desc_list_reverse(chan, &first->tx_list);
704 return NULL;
705}
706
Zhang Wei173acc72008-03-01 07:42:48 -0700707/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700708 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
709 * @chan: DMA channel
710 * @sgl: scatterlist to transfer to/from
711 * @sg_len: number of entries in @scatterlist
712 * @direction: DMA direction
713 * @flags: DMAEngine flags
714 *
715 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
716 * DMA_SLAVE API, this gets the device-specific information from the
717 * chan->private variable.
718 */
719static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000720 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700721 enum dma_data_direction direction, unsigned long flags)
722{
Ira Snyderbbea0b62009-09-08 17:53:04 -0700723 /*
Ira Snyder968f19a2010-09-30 11:46:46 +0000724 * This operation is not supported on the Freescale DMA controller
Ira Snyderbbea0b62009-09-08 17:53:04 -0700725 *
Ira Snyder968f19a2010-09-30 11:46:46 +0000726 * However, we need to provide the function pointer to allow the
727 * device_control() method to work.
Ira Snyderbbea0b62009-09-08 17:53:04 -0700728 */
Ira Snyderbbea0b62009-09-08 17:53:04 -0700729 return NULL;
730}
731
Linus Walleijc3635c72010-03-26 16:44:01 -0700732static int fsl_dma_device_control(struct dma_chan *dchan,
Linus Walleij05827632010-05-17 16:30:42 -0700733 enum dma_ctrl_cmd cmd, unsigned long arg)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700734{
Ira Snyder968f19a2010-09-30 11:46:46 +0000735 struct dma_slave_config *config;
Ira Snydera1c03312010-01-06 13:34:05 +0000736 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700737 unsigned long flags;
Ira Snyder968f19a2010-09-30 11:46:46 +0000738 int size;
Linus Walleijc3635c72010-03-26 16:44:01 -0700739
Ira Snydera1c03312010-01-06 13:34:05 +0000740 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700741 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700742
Ira Snydera1c03312010-01-06 13:34:05 +0000743 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700744
Ira Snyder968f19a2010-09-30 11:46:46 +0000745 switch (cmd) {
746 case DMA_TERMINATE_ALL:
747 /* Halt the DMA engine */
748 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700749
Ira Snyder968f19a2010-09-30 11:46:46 +0000750 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700751
Ira Snyder968f19a2010-09-30 11:46:46 +0000752 /* Remove and free all of the descriptors in the LD queue */
753 fsldma_free_desc_list(chan, &chan->ld_pending);
754 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700755
Ira Snyder968f19a2010-09-30 11:46:46 +0000756 spin_unlock_irqrestore(&chan->desc_lock, flags);
757 return 0;
758
759 case DMA_SLAVE_CONFIG:
760 config = (struct dma_slave_config *)arg;
761
762 /* make sure the channel supports setting burst size */
763 if (!chan->set_request_count)
764 return -ENXIO;
765
766 /* we set the controller burst size depending on direction */
767 if (config->direction == DMA_TO_DEVICE)
768 size = config->dst_addr_width * config->dst_maxburst;
769 else
770 size = config->src_addr_width * config->src_maxburst;
771
772 chan->set_request_count(chan, size);
773 return 0;
774
775 case FSLDMA_EXTERNAL_START:
776
777 /* make sure the channel supports external start */
778 if (!chan->toggle_ext_start)
779 return -ENXIO;
780
781 chan->toggle_ext_start(chan, arg);
782 return 0;
783
784 default:
785 return -ENXIO;
786 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700787
788 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700789}
790
791/**
Zhang Wei173acc72008-03-01 07:42:48 -0700792 * fsl_dma_update_completed_cookie - Update the completed cookie.
Ira Snydera1c03312010-01-06 13:34:05 +0000793 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000794 *
795 * CONTEXT: hardirq
Zhang Wei173acc72008-03-01 07:42:48 -0700796 */
Ira Snydera1c03312010-01-06 13:34:05 +0000797static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700798{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000799 struct fsl_desc_sw *desc;
800 unsigned long flags;
801 dma_cookie_t cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700802
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000803 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700804
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000805 if (list_empty(&chan->ld_running)) {
806 dev_dbg(chan->dev, "no running descriptors\n");
807 goto out_unlock;
Zhang Wei173acc72008-03-01 07:42:48 -0700808 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000809
810 /* Get the last descriptor, update the cookie to that */
811 desc = to_fsl_desc(chan->ld_running.prev);
812 if (dma_is_idle(chan))
813 cookie = desc->async_tx.cookie;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700814 else {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000815 cookie = desc->async_tx.cookie - 1;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700816 if (unlikely(cookie < DMA_MIN_COOKIE))
817 cookie = DMA_MAX_COOKIE;
818 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000819
820 chan->completed_cookie = cookie;
821
822out_unlock:
823 spin_unlock_irqrestore(&chan->desc_lock, flags);
824}
825
826/**
827 * fsldma_desc_status - Check the status of a descriptor
828 * @chan: Freescale DMA channel
829 * @desc: DMA SW descriptor
830 *
831 * This function will return the status of the given descriptor
832 */
833static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
834 struct fsl_desc_sw *desc)
835{
836 return dma_async_is_complete(desc->async_tx.cookie,
837 chan->completed_cookie,
838 chan->common.cookie);
Zhang Wei173acc72008-03-01 07:42:48 -0700839}
840
841/**
842 * fsl_chan_ld_cleanup - Clean up link descriptors
Ira Snydera1c03312010-01-06 13:34:05 +0000843 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700844 *
845 * This function clean up the ld_queue of DMA channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700846 */
Ira Snydera1c03312010-01-06 13:34:05 +0000847static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700848{
849 struct fsl_desc_sw *desc, *_desc;
850 unsigned long flags;
851
Ira Snydera1c03312010-01-06 13:34:05 +0000852 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700853
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000854 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
855 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
Zhang Wei173acc72008-03-01 07:42:48 -0700856 dma_async_tx_callback callback;
857 void *callback_param;
858
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000859 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
Zhang Wei173acc72008-03-01 07:42:48 -0700860 break;
861
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000862 /* Remove from the list of running transactions */
Zhang Wei173acc72008-03-01 07:42:48 -0700863 list_del(&desc->node);
864
Zhang Wei173acc72008-03-01 07:42:48 -0700865 /* Run the link descriptor callback function */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000866 callback = desc->async_tx.callback;
867 callback_param = desc->async_tx.callback_param;
Zhang Wei173acc72008-03-01 07:42:48 -0700868 if (callback) {
Ira Snydera1c03312010-01-06 13:34:05 +0000869 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000870 dev_dbg(chan->dev, "LD %p callback\n", desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700871 callback(callback_param);
Ira Snydera1c03312010-01-06 13:34:05 +0000872 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700873 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000874
875 /* Run any dependencies, then free the descriptor */
876 dma_run_dependencies(&desc->async_tx);
877 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700878 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000879
Ira Snydera1c03312010-01-06 13:34:05 +0000880 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700881}
882
883/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000884 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000885 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000886 *
887 * This will make sure that any pending transactions will be run.
888 * If the DMA controller is idle, it will be started. Otherwise,
889 * the DMA controller's interrupt handler will start any pending
890 * transactions when it becomes idle.
Zhang Wei173acc72008-03-01 07:42:48 -0700891 */
Ira Snydera1c03312010-01-06 13:34:05 +0000892static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700893{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000894 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700895 unsigned long flags;
896
Ira Snydera1c03312010-01-06 13:34:05 +0000897 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder138ef012009-05-19 15:42:13 -0700898
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000899 /*
900 * If the list of pending descriptors is empty, then we
901 * don't need to do any work at all
902 */
903 if (list_empty(&chan->ld_pending)) {
904 dev_dbg(chan->dev, "no pending LDs\n");
Ira Snyder138ef012009-05-19 15:42:13 -0700905 goto out_unlock;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000906 }
Zhang Wei173acc72008-03-01 07:42:48 -0700907
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000908 /*
909 * The DMA controller is not idle, which means the interrupt
910 * handler will start any queued transactions when it runs
911 * at the end of the current transaction
912 */
913 if (!dma_is_idle(chan)) {
914 dev_dbg(chan->dev, "DMA controller still busy\n");
915 goto out_unlock;
916 }
917
918 /*
919 * TODO:
920 * make sure the dma_halt() function really un-wedges the
921 * controller as much as possible
922 */
Ira Snydera1c03312010-01-06 13:34:05 +0000923 dma_halt(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700924
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000925 /*
926 * If there are some link descriptors which have not been
927 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700928 */
Zhang Wei173acc72008-03-01 07:42:48 -0700929
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000930 /*
931 * Move all elements from the queue of pending transactions
932 * onto the list of running transactions
933 */
934 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
935 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700936
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000937 /*
938 * Program the descriptor's address into the DMA controller,
939 * then start the DMA transaction
940 */
941 set_cdar(chan, desc->async_tx.phys);
942 dma_start(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700943
944out_unlock:
Ira Snydera1c03312010-01-06 13:34:05 +0000945 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700946}
947
948/**
949 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000950 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700951 */
Ira Snydera1c03312010-01-06 13:34:05 +0000952static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700953{
Ira Snydera1c03312010-01-06 13:34:05 +0000954 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snydera1c03312010-01-06 13:34:05 +0000955 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700956}
957
Zhang Wei173acc72008-03-01 07:42:48 -0700958/**
Linus Walleij07934482010-03-26 16:50:49 -0700959 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000960 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700961 */
Linus Walleij07934482010-03-26 16:50:49 -0700962static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700963 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700964 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700965{
Ira Snydera1c03312010-01-06 13:34:05 +0000966 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700967 dma_cookie_t last_used;
968 dma_cookie_t last_complete;
969
Ira Snydera1c03312010-01-06 13:34:05 +0000970 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700971
Ira Snydera1c03312010-01-06 13:34:05 +0000972 last_used = dchan->cookie;
973 last_complete = chan->completed_cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700974
Dan Williamsbca34692010-03-26 16:52:10 -0700975 dma_set_tx_state(txstate, last_complete, last_used, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700976
977 return dma_async_is_complete(cookie, last_complete, last_used);
978}
979
Ira Snyderd3f620b2010-01-06 13:34:04 +0000980/*----------------------------------------------------------------------------*/
981/* Interrupt Handling */
982/*----------------------------------------------------------------------------*/
983
Ira Snydere7a29152010-01-06 13:34:03 +0000984static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700985{
Ira Snydera1c03312010-01-06 13:34:05 +0000986 struct fsldma_chan *chan = data;
Zhang Wei1c629792008-04-17 20:17:25 -0700987 int update_cookie = 0;
988 int xfer_ld_q = 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000989 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -0700990
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000991 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +0000992 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000993 set_sr(chan, stat);
994 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
Zhang Wei173acc72008-03-01 07:42:48 -0700995
996 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
997 if (!stat)
998 return IRQ_NONE;
999
1000 if (stat & FSL_DMA_SR_TE)
Ira Snydera1c03312010-01-06 13:34:05 +00001001 dev_err(chan->dev, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001002
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001003 /*
1004 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001005 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1006 * triger a PE interrupt.
1007 */
1008 if (stat & FSL_DMA_SR_PE) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001009 dev_dbg(chan->dev, "irq: Programming Error INT\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001010 if (get_bcr(chan) == 0) {
Zhang Weif79abb62008-03-18 18:45:00 -07001011 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1012 * Now, update the completed cookie, and continue the
1013 * next uncompleted transfer.
1014 */
Zhang Wei1c629792008-04-17 20:17:25 -07001015 update_cookie = 1;
1016 xfer_ld_q = 1;
Zhang Weif79abb62008-03-18 18:45:00 -07001017 }
1018 stat &= ~FSL_DMA_SR_PE;
1019 }
1020
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001021 /*
1022 * If the link descriptor segment transfer finishes,
Zhang Wei173acc72008-03-01 07:42:48 -07001023 * we will recycle the used descriptor.
1024 */
1025 if (stat & FSL_DMA_SR_EOSI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001026 dev_dbg(chan->dev, "irq: End-of-segments INT\n");
1027 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
Ira Snydera1c03312010-01-06 13:34:05 +00001028 (unsigned long long)get_cdar(chan),
1029 (unsigned long long)get_ndar(chan));
Zhang Wei173acc72008-03-01 07:42:48 -07001030 stat &= ~FSL_DMA_SR_EOSI;
Zhang Wei1c629792008-04-17 20:17:25 -07001031 update_cookie = 1;
1032 }
1033
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001034 /*
1035 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001036 * and start the next transfer if it exist.
1037 */
1038 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001039 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001040 stat &= ~FSL_DMA_SR_EOCDI;
1041 update_cookie = 1;
1042 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001043 }
1044
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001045 /*
1046 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001047 * we should clear the Channel Start bit for
1048 * prepare next transfer.
1049 */
Zhang Wei1c629792008-04-17 20:17:25 -07001050 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001051 dev_dbg(chan->dev, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001052 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei1c629792008-04-17 20:17:25 -07001053 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001054 }
1055
Zhang Wei1c629792008-04-17 20:17:25 -07001056 if (update_cookie)
Ira Snydera1c03312010-01-06 13:34:05 +00001057 fsl_dma_update_completed_cookie(chan);
Zhang Wei1c629792008-04-17 20:17:25 -07001058 if (xfer_ld_q)
Ira Snydera1c03312010-01-06 13:34:05 +00001059 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001060 if (stat)
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001061 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001062
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001063 dev_dbg(chan->dev, "irq: Exit\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001064 tasklet_schedule(&chan->tasklet);
Zhang Wei173acc72008-03-01 07:42:48 -07001065 return IRQ_HANDLED;
1066}
1067
Zhang Wei173acc72008-03-01 07:42:48 -07001068static void dma_do_tasklet(unsigned long data)
1069{
Ira Snydera1c03312010-01-06 13:34:05 +00001070 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1071 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001072}
1073
Ira Snyderd3f620b2010-01-06 13:34:04 +00001074static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1075{
1076 struct fsldma_device *fdev = data;
1077 struct fsldma_chan *chan;
1078 unsigned int handled = 0;
1079 u32 gsr, mask;
1080 int i;
1081
1082 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1083 : in_le32(fdev->regs);
1084 mask = 0xff000000;
1085 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1086
1087 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1088 chan = fdev->chan[i];
1089 if (!chan)
1090 continue;
1091
1092 if (gsr & mask) {
1093 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1094 fsldma_chan_irq(irq, chan);
1095 handled++;
1096 }
1097
1098 gsr &= ~mask;
1099 mask >>= 8;
1100 }
1101
1102 return IRQ_RETVAL(handled);
1103}
1104
1105static void fsldma_free_irqs(struct fsldma_device *fdev)
1106{
1107 struct fsldma_chan *chan;
1108 int i;
1109
1110 if (fdev->irq != NO_IRQ) {
1111 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1112 free_irq(fdev->irq, fdev);
1113 return;
1114 }
1115
1116 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1117 chan = fdev->chan[i];
1118 if (chan && chan->irq != NO_IRQ) {
1119 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
1120 free_irq(chan->irq, chan);
1121 }
1122 }
1123}
1124
1125static int fsldma_request_irqs(struct fsldma_device *fdev)
1126{
1127 struct fsldma_chan *chan;
1128 int ret;
1129 int i;
1130
1131 /* if we have a per-controller IRQ, use that */
1132 if (fdev->irq != NO_IRQ) {
1133 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1134 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1135 "fsldma-controller", fdev);
1136 return ret;
1137 }
1138
1139 /* no per-controller IRQ, use the per-channel IRQs */
1140 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1141 chan = fdev->chan[i];
1142 if (!chan)
1143 continue;
1144
1145 if (chan->irq == NO_IRQ) {
1146 dev_err(fdev->dev, "no interrupts property defined for "
1147 "DMA channel %d. Please fix your "
1148 "device tree\n", chan->id);
1149 ret = -ENODEV;
1150 goto out_unwind;
1151 }
1152
1153 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
1154 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1155 "fsldma-chan", chan);
1156 if (ret) {
1157 dev_err(fdev->dev, "unable to request IRQ for DMA "
1158 "channel %d\n", chan->id);
1159 goto out_unwind;
1160 }
1161 }
1162
1163 return 0;
1164
1165out_unwind:
1166 for (/* none */; i >= 0; i--) {
1167 chan = fdev->chan[i];
1168 if (!chan)
1169 continue;
1170
1171 if (chan->irq == NO_IRQ)
1172 continue;
1173
1174 free_irq(chan->irq, chan);
1175 }
1176
1177 return ret;
1178}
1179
Ira Snydera4f56d42010-01-06 13:34:01 +00001180/*----------------------------------------------------------------------------*/
1181/* OpenFirmware Subsystem */
1182/*----------------------------------------------------------------------------*/
1183
1184static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001185 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001186{
Ira Snydera1c03312010-01-06 13:34:05 +00001187 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001188 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001189 int err;
1190
Zhang Wei173acc72008-03-01 07:42:48 -07001191 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001192 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1193 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001194 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1195 err = -ENOMEM;
1196 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001197 }
1198
Ira Snydere7a29152010-01-06 13:34:03 +00001199 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001200 chan->regs = of_iomap(node, 0);
1201 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001202 dev_err(fdev->dev, "unable to ioremap registers\n");
1203 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001204 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001205 }
1206
Ira Snyder4ce0e952010-01-06 13:34:00 +00001207 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001208 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001209 dev_err(fdev->dev, "unable to find 'reg' property\n");
1210 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001211 }
1212
Ira Snydera1c03312010-01-06 13:34:05 +00001213 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001214 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001215 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001216
Ira Snydere7a29152010-01-06 13:34:03 +00001217 /*
1218 * If the DMA device's feature is different than the feature
1219 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001220 */
Ira Snydera1c03312010-01-06 13:34:05 +00001221 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001222
Ira Snydera1c03312010-01-06 13:34:05 +00001223 chan->dev = fdev->dev;
1224 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1225 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001226 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001227 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001228 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001229 }
Zhang Wei173acc72008-03-01 07:42:48 -07001230
Ira Snydera1c03312010-01-06 13:34:05 +00001231 fdev->chan[chan->id] = chan;
1232 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001233
1234 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001235 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001236
1237 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001238 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001239
Ira Snydera1c03312010-01-06 13:34:05 +00001240 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001241 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001242 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001243 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001244 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1245 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1246 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1247 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001248 }
1249
Ira Snydera1c03312010-01-06 13:34:05 +00001250 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001251 INIT_LIST_HEAD(&chan->ld_pending);
1252 INIT_LIST_HEAD(&chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -07001253
Ira Snydera1c03312010-01-06 13:34:05 +00001254 chan->common.device = &fdev->common;
Zhang Wei173acc72008-03-01 07:42:48 -07001255
Ira Snyderd3f620b2010-01-06 13:34:04 +00001256 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001257 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001258
Zhang Wei173acc72008-03-01 07:42:48 -07001259 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001260 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001261 fdev->common.chancnt++;
1262
Ira Snydera1c03312010-01-06 13:34:05 +00001263 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1264 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001265
1266 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001267
Ira Snydere7a29152010-01-06 13:34:03 +00001268out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001269 iounmap(chan->regs);
1270out_free_chan:
1271 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001272out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001273 return err;
1274}
1275
Ira Snydera1c03312010-01-06 13:34:05 +00001276static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001277{
Ira Snydera1c03312010-01-06 13:34:05 +00001278 irq_dispose_mapping(chan->irq);
1279 list_del(&chan->common.device_node);
1280 iounmap(chan->regs);
1281 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001282}
1283
Grant Likely2dc11582010-08-06 09:25:50 -06001284static int __devinit fsldma_of_probe(struct platform_device *op,
Zhang Wei173acc72008-03-01 07:42:48 -07001285 const struct of_device_id *match)
1286{
Ira Snydera4f56d42010-01-06 13:34:01 +00001287 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001288 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001289 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001290
Ira Snydera4f56d42010-01-06 13:34:01 +00001291 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001292 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001293 dev_err(&op->dev, "No enough memory for 'priv'\n");
1294 err = -ENOMEM;
1295 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001296 }
Ira Snydere7a29152010-01-06 13:34:03 +00001297
1298 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001299 INIT_LIST_HEAD(&fdev->common.channels);
1300
Ira Snydere7a29152010-01-06 13:34:03 +00001301 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001302 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001303 if (!fdev->regs) {
1304 dev_err(&op->dev, "unable to ioremap registers\n");
1305 err = -ENOMEM;
1306 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001307 }
1308
Ira Snyderd3f620b2010-01-06 13:34:04 +00001309 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001310 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001311
Zhang Wei173acc72008-03-01 07:42:48 -07001312 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1313 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001314 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001315 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001316 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1317 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001318 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001319 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001320 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001321 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001322 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001323 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001324 fdev->common.device_control = fsl_dma_device_control;
Ira Snydere7a29152010-01-06 13:34:03 +00001325 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001326
Ira Snydere7a29152010-01-06 13:34:03 +00001327 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001328
Ira Snydere7a29152010-01-06 13:34:03 +00001329 /*
1330 * We cannot use of_platform_bus_probe() because there is no
1331 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001332 * channel object.
1333 */
Grant Likely61c7a082010-04-13 16:12:29 -07001334 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001335 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001336 fsl_dma_chan_probe(fdev, child,
1337 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1338 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001339 }
1340
1341 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001342 fsl_dma_chan_probe(fdev, child,
1343 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1344 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001345 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001346 }
Zhang Wei173acc72008-03-01 07:42:48 -07001347
Ira Snyderd3f620b2010-01-06 13:34:04 +00001348 /*
1349 * Hookup the IRQ handler(s)
1350 *
1351 * If we have a per-controller interrupt, we prefer that to the
1352 * per-channel interrupts to reduce the number of shared interrupt
1353 * handlers on the same IRQ line
1354 */
1355 err = fsldma_request_irqs(fdev);
1356 if (err) {
1357 dev_err(fdev->dev, "unable to request IRQs\n");
1358 goto out_free_fdev;
1359 }
1360
Zhang Wei173acc72008-03-01 07:42:48 -07001361 dma_async_device_register(&fdev->common);
1362 return 0;
1363
Ira Snydere7a29152010-01-06 13:34:03 +00001364out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001365 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001366 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001367out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001368 return err;
1369}
1370
Grant Likely2dc11582010-08-06 09:25:50 -06001371static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001372{
Ira Snydera4f56d42010-01-06 13:34:01 +00001373 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001374 unsigned int i;
1375
Ira Snydere7a29152010-01-06 13:34:03 +00001376 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001377 dma_async_device_unregister(&fdev->common);
1378
Ira Snyderd3f620b2010-01-06 13:34:04 +00001379 fsldma_free_irqs(fdev);
1380
Ira Snydere7a29152010-01-06 13:34:03 +00001381 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001382 if (fdev->chan[i])
1383 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001384 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001385
Ira Snydere7a29152010-01-06 13:34:03 +00001386 iounmap(fdev->regs);
1387 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001388 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001389
1390 return 0;
1391}
1392
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001393static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001394 { .compatible = "fsl,eloplus-dma", },
1395 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001396 {}
1397};
1398
Ira Snydera4f56d42010-01-06 13:34:01 +00001399static struct of_platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001400 .driver = {
1401 .name = "fsl-elo-dma",
1402 .owner = THIS_MODULE,
1403 .of_match_table = fsldma_of_ids,
1404 },
1405 .probe = fsldma_of_probe,
1406 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001407};
1408
Ira Snydera4f56d42010-01-06 13:34:01 +00001409/*----------------------------------------------------------------------------*/
1410/* Module Init / Exit */
1411/*----------------------------------------------------------------------------*/
1412
1413static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001414{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001415 int ret;
1416
1417 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1418
Ira Snydera4f56d42010-01-06 13:34:01 +00001419 ret = of_register_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001420 if (ret)
1421 pr_err("fsldma: failed to register platform driver\n");
1422
1423 return ret;
Zhang Wei173acc72008-03-01 07:42:48 -07001424}
1425
Ira Snydera4f56d42010-01-06 13:34:01 +00001426static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001427{
Ira Snydera4f56d42010-01-06 13:34:01 +00001428 of_unregister_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001429}
1430
Ira Snydera4f56d42010-01-06 13:34:01 +00001431subsys_initcall(fsldma_init);
1432module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001433
1434MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1435MODULE_LICENSE("GPL");