Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device |
| 3 | * |
| 4 | * Copyright (C) 1995 Jay Estabrook |
| 5 | * Copyright (C) 1997 Geert Uytterhoeven |
| 6 | * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha |
| 7 | * Copyright (C) 2002 Richard Henderson |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file COPYING in the main directory of this archive for |
| 11 | * more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/sched.h> |
| 17 | #include <linux/errno.h> |
| 18 | #include <linux/string.h> |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/tty.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/fb.h> |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/selection.h> |
| 27 | #include <asm/io.h> |
| 28 | #include <video/tgafb.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * Local functions. |
| 32 | */ |
| 33 | |
| 34 | static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *); |
| 35 | static int tgafb_set_par(struct fb_info *); |
| 36 | static void tgafb_set_pll(struct tga_par *, int); |
| 37 | static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned, |
| 38 | unsigned, struct fb_info *); |
| 39 | static int tgafb_blank(int, struct fb_info *); |
| 40 | static void tgafb_init_fix(struct fb_info *); |
| 41 | |
| 42 | static void tgafb_imageblit(struct fb_info *, const struct fb_image *); |
| 43 | static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *); |
| 44 | static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *); |
| 45 | |
| 46 | static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | static void tgafb_pci_unregister(struct pci_dev *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | static const char *mode_option = "640x480@60"; |
| 50 | |
| 51 | |
| 52 | /* |
| 53 | * Frame buffer operations |
| 54 | */ |
| 55 | |
| 56 | static struct fb_ops tgafb_ops = { |
| 57 | .owner = THIS_MODULE, |
| 58 | .fb_check_var = tgafb_check_var, |
| 59 | .fb_set_par = tgafb_set_par, |
| 60 | .fb_setcolreg = tgafb_setcolreg, |
| 61 | .fb_blank = tgafb_blank, |
| 62 | .fb_fillrect = tgafb_fillrect, |
| 63 | .fb_copyarea = tgafb_copyarea, |
| 64 | .fb_imageblit = tgafb_imageblit, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | |
| 68 | /* |
| 69 | * PCI registration operations |
| 70 | */ |
| 71 | |
| 72 | static struct pci_device_id const tgafb_pci_table[] = { |
| 73 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID, |
| 74 | 0, 0, 0 } |
| 75 | }; |
| 76 | |
| 77 | static struct pci_driver tgafb_driver = { |
| 78 | .name = "tgafb", |
| 79 | .id_table = tgafb_pci_table, |
| 80 | .probe = tgafb_pci_register, |
| 81 | .remove = __devexit_p(tgafb_pci_unregister), |
| 82 | }; |
| 83 | |
| 84 | |
| 85 | /** |
| 86 | * tgafb_check_var - Optional function. Validates a var passed in. |
| 87 | * @var: frame buffer variable screen structure |
| 88 | * @info: frame buffer structure that represents a single frame buffer |
| 89 | */ |
| 90 | static int |
| 91 | tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 92 | { |
| 93 | struct tga_par *par = (struct tga_par *)info->par; |
| 94 | |
| 95 | if (par->tga_type == TGA_TYPE_8PLANE) { |
| 96 | if (var->bits_per_pixel != 8) |
| 97 | return -EINVAL; |
| 98 | } else { |
| 99 | if (var->bits_per_pixel != 32) |
| 100 | return -EINVAL; |
| 101 | } |
| 102 | |
| 103 | if (var->xres_virtual != var->xres || var->yres_virtual != var->yres) |
| 104 | return -EINVAL; |
| 105 | if (var->nonstd) |
| 106 | return -EINVAL; |
| 107 | if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ) |
| 108 | return -EINVAL; |
| 109 | if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) |
| 110 | return -EINVAL; |
| 111 | |
| 112 | /* Some of the acceleration routines assume the line width is |
| 113 | a multiple of 64 bytes. */ |
| 114 | if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64) |
| 115 | return -EINVAL; |
| 116 | |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | /** |
| 121 | * tgafb_set_par - Optional function. Alters the hardware state. |
| 122 | * @info: frame buffer structure that represents a single frame buffer |
| 123 | */ |
| 124 | static int |
| 125 | tgafb_set_par(struct fb_info *info) |
| 126 | { |
| 127 | static unsigned int const deep_presets[4] = { |
| 128 | 0x00014000, |
| 129 | 0x0001440d, |
| 130 | 0xffffffff, |
| 131 | 0x0001441d |
| 132 | }; |
| 133 | static unsigned int const rasterop_presets[4] = { |
| 134 | 0x00000003, |
| 135 | 0x00000303, |
| 136 | 0xffffffff, |
| 137 | 0x00000303 |
| 138 | }; |
| 139 | static unsigned int const mode_presets[4] = { |
| 140 | 0x00002000, |
| 141 | 0x00002300, |
| 142 | 0xffffffff, |
| 143 | 0x00002300 |
| 144 | }; |
| 145 | static unsigned int const base_addr_presets[4] = { |
| 146 | 0x00000000, |
| 147 | 0x00000001, |
| 148 | 0xffffffff, |
| 149 | 0x00000001 |
| 150 | }; |
| 151 | |
| 152 | struct tga_par *par = (struct tga_par *) info->par; |
| 153 | u32 htimings, vtimings, pll_freq; |
| 154 | u8 tga_type; |
| 155 | int i, j; |
| 156 | |
| 157 | /* Encode video timings. */ |
| 158 | htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB) |
| 159 | | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB)); |
| 160 | vtimings = (info->var.yres & TGA_VERT_ACTIVE); |
| 161 | htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP; |
| 162 | vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP; |
| 163 | htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC; |
| 164 | vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC; |
| 165 | htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP; |
| 166 | vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP; |
| 167 | |
| 168 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
| 169 | htimings |= TGA_HORIZ_POLARITY; |
| 170 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
| 171 | vtimings |= TGA_VERT_POLARITY; |
| 172 | |
| 173 | par->htimings = htimings; |
| 174 | par->vtimings = vtimings; |
| 175 | |
| 176 | par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN); |
| 177 | |
| 178 | /* Store other useful values in par. */ |
| 179 | par->xres = info->var.xres; |
| 180 | par->yres = info->var.yres; |
| 181 | par->pll_freq = pll_freq = 1000000000 / info->var.pixclock; |
| 182 | par->bits_per_pixel = info->var.bits_per_pixel; |
| 183 | |
| 184 | tga_type = par->tga_type; |
| 185 | |
| 186 | /* First, disable video. */ |
| 187 | TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); |
| 188 | |
| 189 | /* Write the DEEP register. */ |
| 190 | while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ |
| 191 | continue; |
| 192 | mb(); |
| 193 | TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG); |
| 194 | while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ |
| 195 | continue; |
| 196 | mb(); |
| 197 | |
| 198 | /* Write some more registers. */ |
| 199 | TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG); |
| 200 | TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG); |
| 201 | TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG); |
| 202 | |
| 203 | /* Calculate & write the PLL. */ |
| 204 | tgafb_set_pll(par, pll_freq); |
| 205 | |
| 206 | /* Write some more registers. */ |
| 207 | TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG); |
| 208 | TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG); |
| 209 | |
| 210 | /* Init video timing regs. */ |
| 211 | TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG); |
| 212 | TGA_WRITE_REG(par, vtimings, TGA_VERT_REG); |
| 213 | |
| 214 | /* Initalise RAMDAC. */ |
| 215 | if (tga_type == TGA_TYPE_8PLANE) { |
| 216 | |
| 217 | /* Init BT485 RAMDAC registers. */ |
| 218 | BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0), |
| 219 | BT485_CMD_0); |
| 220 | BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE); |
| 221 | BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */ |
| 222 | BT485_WRITE(par, 0x40, BT485_CMD_1); |
| 223 | BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */ |
| 224 | BT485_WRITE(par, 0xff, BT485_PIXEL_MASK); |
| 225 | |
| 226 | /* Fill palette registers. */ |
| 227 | BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); |
| 228 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); |
| 229 | |
| 230 | for (i = 0; i < 16; i++) { |
| 231 | j = color_table[i]; |
| 232 | TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8), |
| 233 | TGA_RAMDAC_REG); |
| 234 | TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8), |
| 235 | TGA_RAMDAC_REG); |
| 236 | TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8), |
| 237 | TGA_RAMDAC_REG); |
| 238 | } |
| 239 | for (i = 0; i < 240*3; i += 4) { |
| 240 | TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8), |
| 241 | TGA_RAMDAC_REG); |
| 242 | TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), |
| 243 | TGA_RAMDAC_REG); |
| 244 | TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), |
| 245 | TGA_RAMDAC_REG); |
| 246 | TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), |
| 247 | TGA_RAMDAC_REG); |
| 248 | } |
| 249 | |
| 250 | } else { /* 24-plane or 24plusZ */ |
| 251 | |
| 252 | /* Init BT463 registers. */ |
| 253 | BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40); |
| 254 | BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08); |
| 255 | BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2, |
| 256 | (par->sync_on_green ? 0x80 : 0x40)); |
| 257 | |
| 258 | BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff); |
| 259 | BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff); |
| 260 | BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff); |
| 261 | BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f); |
| 262 | |
| 263 | BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00); |
| 264 | BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00); |
| 265 | BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00); |
| 266 | BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00); |
| 267 | |
| 268 | /* Fill the palette. */ |
| 269 | BT463_LOAD_ADDR(par, 0x0000); |
| 270 | TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG); |
| 271 | |
| 272 | for (i = 0; i < 16; i++) { |
| 273 | j = color_table[i]; |
| 274 | TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10), |
| 275 | TGA_RAMDAC_REG); |
| 276 | TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10), |
| 277 | TGA_RAMDAC_REG); |
| 278 | TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10), |
| 279 | TGA_RAMDAC_REG); |
| 280 | } |
| 281 | for (i = 0; i < 512*3; i += 4) { |
| 282 | TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10), |
| 283 | TGA_RAMDAC_REG); |
| 284 | TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), |
| 285 | TGA_RAMDAC_REG); |
| 286 | TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), |
| 287 | TGA_RAMDAC_REG); |
| 288 | TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), |
| 289 | TGA_RAMDAC_REG); |
| 290 | } |
| 291 | |
| 292 | /* Fill window type table after start of vertical retrace. */ |
| 293 | while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) |
| 294 | continue; |
| 295 | TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); |
| 296 | mb(); |
| 297 | while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) |
| 298 | continue; |
| 299 | TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); |
| 300 | |
| 301 | BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE); |
| 302 | TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG); |
| 303 | |
| 304 | for (i = 0; i < 16; i++) { |
| 305 | TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10), |
| 306 | TGA_RAMDAC_REG); |
| 307 | TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10), |
| 308 | TGA_RAMDAC_REG); |
| 309 | TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10), |
| 310 | TGA_RAMDAC_REG); |
| 311 | } |
| 312 | |
| 313 | } |
| 314 | |
| 315 | /* Finally, enable video scan (and pray for the monitor... :-) */ |
| 316 | TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG); |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | #define DIFFCHECK(X) \ |
| 322 | do { \ |
| 323 | if (m <= 0x3f) { \ |
| 324 | int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \ |
| 325 | if (delta < 0) \ |
| 326 | delta = -delta; \ |
| 327 | if (delta < min_diff) \ |
| 328 | min_diff = delta, vm = m, va = a, vr = r; \ |
| 329 | } \ |
| 330 | } while (0) |
| 331 | |
| 332 | static void |
| 333 | tgafb_set_pll(struct tga_par *par, int f) |
| 334 | { |
| 335 | int n, shift, base, min_diff, target; |
| 336 | int r,a,m,vm = 34, va = 1, vr = 30; |
| 337 | |
| 338 | for (r = 0 ; r < 12 ; r++) |
| 339 | TGA_WRITE_REG(par, !r, TGA_CLOCK_REG); |
| 340 | |
| 341 | if (f > TGA_PLL_MAX_FREQ) |
| 342 | f = TGA_PLL_MAX_FREQ; |
| 343 | |
| 344 | if (f >= TGA_PLL_MAX_FREQ / 2) |
| 345 | shift = 0; |
| 346 | else if (f >= TGA_PLL_MAX_FREQ / 4) |
| 347 | shift = 1; |
| 348 | else |
| 349 | shift = 2; |
| 350 | |
| 351 | TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG); |
| 352 | TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG); |
| 353 | |
| 354 | for (r = 0 ; r < 10 ; r++) |
| 355 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 356 | |
| 357 | if (f <= 120000) { |
| 358 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 359 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 360 | } |
| 361 | else if (f <= 200000) { |
| 362 | TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); |
| 363 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 364 | } |
| 365 | else { |
| 366 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 367 | TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); |
| 368 | } |
| 369 | |
| 370 | TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); |
| 371 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 372 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 373 | TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); |
| 374 | TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); |
| 375 | TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); |
| 376 | |
| 377 | target = (f << shift) / TGA_PLL_BASE_FREQ; |
| 378 | min_diff = TGA_PLL_MAX_FREQ; |
| 379 | |
| 380 | r = 7 / target; |
| 381 | if (!r) r = 1; |
| 382 | |
| 383 | base = target * r; |
| 384 | while (base < 449) { |
| 385 | for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) { |
| 386 | m = ((n + 3) / 7) - 1; |
| 387 | a = 0; |
| 388 | DIFFCHECK((m + 1) * 7); |
| 389 | m++; |
| 390 | DIFFCHECK((m + 1) * 7); |
| 391 | m = (n / 6) - 1; |
| 392 | if ((a = n % 6)) |
| 393 | DIFFCHECK(n); |
| 394 | } |
| 395 | r++; |
| 396 | base += target; |
| 397 | } |
| 398 | |
| 399 | vr--; |
| 400 | |
| 401 | for (r = 0; r < 8; r++) |
| 402 | TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG); |
| 403 | for (r = 0; r < 8 ; r++) |
| 404 | TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG); |
| 405 | for (r = 0; r < 7 ; r++) |
| 406 | TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG); |
| 407 | TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG); |
| 408 | } |
| 409 | |
| 410 | |
| 411 | /** |
| 412 | * tgafb_setcolreg - Optional function. Sets a color register. |
| 413 | * @regno: boolean, 0 copy local, 1 get_user() function |
| 414 | * @red: frame buffer colormap structure |
| 415 | * @green: The green value which can be up to 16 bits wide |
| 416 | * @blue: The blue value which can be up to 16 bits wide. |
| 417 | * @transp: If supported the alpha value which can be up to 16 bits wide. |
| 418 | * @info: frame buffer info structure |
| 419 | */ |
| 420 | static int |
| 421 | tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, |
| 422 | unsigned transp, struct fb_info *info) |
| 423 | { |
| 424 | struct tga_par *par = (struct tga_par *) info->par; |
| 425 | |
| 426 | if (regno > 255) |
| 427 | return 1; |
| 428 | red >>= 8; |
| 429 | green >>= 8; |
| 430 | blue >>= 8; |
| 431 | |
| 432 | if (par->tga_type == TGA_TYPE_8PLANE) { |
| 433 | BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE); |
| 434 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); |
| 435 | TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
| 436 | TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
| 437 | TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
| 438 | } else if (regno < 16) { |
| 439 | u32 value = (red << 16) | (green << 8) | blue; |
| 440 | ((u32 *)info->pseudo_palette)[regno] = value; |
| 441 | } |
| 442 | |
| 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | |
| 447 | /** |
| 448 | * tgafb_blank - Optional function. Blanks the display. |
| 449 | * @blank_mode: the blank mode we want. |
| 450 | * @info: frame buffer structure that represents a single frame buffer |
| 451 | */ |
| 452 | static int |
| 453 | tgafb_blank(int blank, struct fb_info *info) |
| 454 | { |
| 455 | struct tga_par *par = (struct tga_par *) info->par; |
| 456 | u32 vhcr, vvcr, vvvr; |
| 457 | unsigned long flags; |
| 458 | |
| 459 | local_irq_save(flags); |
| 460 | |
| 461 | vhcr = TGA_READ_REG(par, TGA_HORIZ_REG); |
| 462 | vvcr = TGA_READ_REG(par, TGA_VERT_REG); |
| 463 | vvvr = TGA_READ_REG(par, TGA_VALID_REG); |
| 464 | vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK); |
| 465 | |
| 466 | switch (blank) { |
| 467 | case FB_BLANK_UNBLANK: /* Unblanking */ |
| 468 | if (par->vesa_blanked) { |
| 469 | TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG); |
| 470 | TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG); |
| 471 | par->vesa_blanked = 0; |
| 472 | } |
| 473 | TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG); |
| 474 | break; |
| 475 | |
| 476 | case FB_BLANK_NORMAL: /* Normal blanking */ |
| 477 | TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, |
| 478 | TGA_VALID_REG); |
| 479 | break; |
| 480 | |
| 481 | case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ |
| 482 | TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); |
| 483 | TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); |
| 484 | par->vesa_blanked = 1; |
| 485 | break; |
| 486 | |
| 487 | case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ |
| 488 | TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); |
| 489 | TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); |
| 490 | par->vesa_blanked = 1; |
| 491 | break; |
| 492 | |
| 493 | case FB_BLANK_POWERDOWN: /* Poweroff */ |
| 494 | TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); |
| 495 | TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); |
| 496 | TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); |
| 497 | par->vesa_blanked = 1; |
| 498 | break; |
| 499 | } |
| 500 | |
| 501 | local_irq_restore(flags); |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | |
| 506 | /* |
| 507 | * Acceleration. |
| 508 | */ |
| 509 | |
| 510 | /** |
| 511 | * tgafb_imageblit - REQUIRED function. Can use generic routines if |
| 512 | * non acclerated hardware and packed pixel based. |
| 513 | * Copies a image from system memory to the screen. |
| 514 | * |
| 515 | * @info: frame buffer structure that represents a single frame buffer |
| 516 | * @image: structure defining the image. |
| 517 | */ |
| 518 | static void |
| 519 | tgafb_imageblit(struct fb_info *info, const struct fb_image *image) |
| 520 | { |
| 521 | static unsigned char const bitrev[256] = { |
| 522 | 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, |
| 523 | 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, |
| 524 | 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, |
| 525 | 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, |
| 526 | 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, |
| 527 | 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, |
| 528 | 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, |
| 529 | 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, |
| 530 | 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, |
| 531 | 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, |
| 532 | 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, |
| 533 | 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, |
| 534 | 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, |
| 535 | 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, |
| 536 | 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, |
| 537 | 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, |
| 538 | 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, |
| 539 | 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, |
| 540 | 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, |
| 541 | 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, |
| 542 | 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, |
| 543 | 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, |
| 544 | 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, |
| 545 | 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, |
| 546 | 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, |
| 547 | 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, |
| 548 | 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, |
| 549 | 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, |
| 550 | 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, |
| 551 | 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, |
| 552 | 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, |
| 553 | 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff |
| 554 | }; |
| 555 | |
| 556 | struct tga_par *par = (struct tga_par *) info->par; |
| 557 | u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask; |
| 558 | unsigned long rincr, line_length, shift, pos, is8bpp; |
| 559 | unsigned long i, j; |
| 560 | const unsigned char *data; |
| 561 | void __iomem *regs_base; |
| 562 | void __iomem *fb_base; |
| 563 | |
| 564 | dx = image->dx; |
| 565 | dy = image->dy; |
| 566 | width = image->width; |
| 567 | height = image->height; |
| 568 | vxres = info->var.xres_virtual; |
| 569 | vyres = info->var.yres_virtual; |
| 570 | line_length = info->fix.line_length; |
| 571 | rincr = (width + 7) / 8; |
| 572 | |
| 573 | /* Crop the image to the screen. */ |
| 574 | if (dx > vxres || dy > vyres) |
| 575 | return; |
| 576 | if (dx + width > vxres) |
| 577 | width = vxres - dx; |
| 578 | if (dy + height > vyres) |
| 579 | height = vyres - dy; |
| 580 | |
| 581 | /* For copies that aren't pixel expansion, there's little we |
| 582 | can do better than the generic code. */ |
| 583 | /* ??? There is a DMA write mode; I wonder if that could be |
| 584 | made to pull the data from the image buffer... */ |
| 585 | if (image->depth > 1) { |
| 586 | cfb_imageblit(info, image); |
| 587 | return; |
| 588 | } |
| 589 | |
| 590 | regs_base = par->tga_regs_base; |
| 591 | fb_base = par->tga_fb_base; |
| 592 | is8bpp = info->var.bits_per_pixel == 8; |
| 593 | |
| 594 | /* Expand the color values to fill 32-bits. */ |
| 595 | /* ??? Would be nice to notice colour changes elsewhere, so |
| 596 | that we can do this only when necessary. */ |
| 597 | fgcolor = image->fg_color; |
| 598 | bgcolor = image->bg_color; |
| 599 | if (is8bpp) { |
| 600 | fgcolor |= fgcolor << 8; |
| 601 | fgcolor |= fgcolor << 16; |
| 602 | bgcolor |= bgcolor << 8; |
| 603 | bgcolor |= bgcolor << 16; |
| 604 | } else { |
| 605 | if (fgcolor < 16) |
| 606 | fgcolor = ((u32 *)info->pseudo_palette)[fgcolor]; |
| 607 | if (bgcolor < 16) |
| 608 | bgcolor = ((u32 *)info->pseudo_palette)[bgcolor]; |
| 609 | } |
| 610 | __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG); |
| 611 | __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG); |
| 612 | |
| 613 | /* Acquire proper alignment; set up the PIXELMASK register |
| 614 | so that we only write the proper character cell. */ |
| 615 | pos = dy * line_length; |
| 616 | if (is8bpp) { |
| 617 | pos += dx; |
| 618 | shift = pos & 3; |
| 619 | pos &= -4; |
| 620 | } else { |
| 621 | pos += dx * 4; |
| 622 | shift = (pos & 7) >> 2; |
| 623 | pos &= -8; |
| 624 | } |
| 625 | |
| 626 | data = (const unsigned char *) image->data; |
| 627 | |
| 628 | /* Enable opaque stipple mode. */ |
| 629 | __raw_writel((is8bpp |
| 630 | ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE |
| 631 | : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE), |
| 632 | regs_base + TGA_MODE_REG); |
| 633 | |
| 634 | if (width + shift <= 32) { |
| 635 | unsigned long bwidth; |
| 636 | |
| 637 | /* Handle common case of imaging a single character, in |
| 638 | a font less than 32 pixels wide. */ |
| 639 | |
| 640 | pixelmask = (1 << width) - 1; |
| 641 | pixelmask <<= shift; |
| 642 | __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); |
| 643 | wmb(); |
| 644 | |
| 645 | bwidth = (width + 7) / 8; |
| 646 | |
| 647 | for (i = 0; i < height; ++i) { |
| 648 | u32 mask = 0; |
| 649 | |
| 650 | /* The image data is bit big endian; we need |
| 651 | little endian. */ |
| 652 | for (j = 0; j < bwidth; ++j) |
| 653 | mask |= bitrev[data[j]] << (j * 8); |
| 654 | |
| 655 | __raw_writel(mask << shift, fb_base + pos); |
| 656 | |
| 657 | pos += line_length; |
| 658 | data += rincr; |
| 659 | } |
| 660 | wmb(); |
| 661 | __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); |
| 662 | } else if (shift == 0) { |
| 663 | unsigned long pos0 = pos; |
| 664 | const unsigned char *data0 = data; |
| 665 | unsigned long bincr = (is8bpp ? 8 : 8*4); |
| 666 | unsigned long bwidth; |
| 667 | |
| 668 | /* Handle another common case in which accel_putcs |
| 669 | generates a large bitmap, which happens to be aligned. |
| 670 | Allow the tail to be misaligned. This case is |
| 671 | interesting because we've not got to hold partial |
| 672 | bytes across the words being written. */ |
| 673 | |
| 674 | wmb(); |
| 675 | |
| 676 | bwidth = (width / 8) & -4; |
| 677 | for (i = 0; i < height; ++i) { |
| 678 | for (j = 0; j < bwidth; j += 4) { |
| 679 | u32 mask = 0; |
| 680 | mask |= bitrev[data[j+0]] << (0 * 8); |
| 681 | mask |= bitrev[data[j+1]] << (1 * 8); |
| 682 | mask |= bitrev[data[j+2]] << (2 * 8); |
| 683 | mask |= bitrev[data[j+3]] << (3 * 8); |
| 684 | __raw_writel(mask, fb_base + pos + j*bincr); |
| 685 | } |
| 686 | pos += line_length; |
| 687 | data += rincr; |
| 688 | } |
| 689 | wmb(); |
| 690 | |
| 691 | pixelmask = (1ul << (width & 31)) - 1; |
| 692 | if (pixelmask) { |
| 693 | __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); |
| 694 | wmb(); |
| 695 | |
| 696 | pos = pos0 + bwidth*bincr; |
| 697 | data = data0 + bwidth; |
| 698 | bwidth = ((width & 31) + 7) / 8; |
| 699 | |
| 700 | for (i = 0; i < height; ++i) { |
| 701 | u32 mask = 0; |
| 702 | for (j = 0; j < bwidth; ++j) |
| 703 | mask |= bitrev[data[j]] << (j * 8); |
| 704 | __raw_writel(mask, fb_base + pos); |
| 705 | pos += line_length; |
| 706 | data += rincr; |
| 707 | } |
| 708 | wmb(); |
| 709 | __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); |
| 710 | } |
| 711 | } else { |
| 712 | unsigned long pos0 = pos; |
| 713 | const unsigned char *data0 = data; |
| 714 | unsigned long bincr = (is8bpp ? 8 : 8*4); |
| 715 | unsigned long bwidth; |
| 716 | |
| 717 | /* Finally, handle the generic case of misaligned start. |
| 718 | Here we split the write into 16-bit spans. This allows |
| 719 | us to use only one pixel mask, instead of four as would |
| 720 | be required by writing 24-bit spans. */ |
| 721 | |
| 722 | pixelmask = 0xffff << shift; |
| 723 | __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); |
| 724 | wmb(); |
| 725 | |
| 726 | bwidth = (width / 8) & -2; |
| 727 | for (i = 0; i < height; ++i) { |
| 728 | for (j = 0; j < bwidth; j += 2) { |
| 729 | u32 mask = 0; |
| 730 | mask |= bitrev[data[j+0]] << (0 * 8); |
| 731 | mask |= bitrev[data[j+1]] << (1 * 8); |
| 732 | mask <<= shift; |
| 733 | __raw_writel(mask, fb_base + pos + j*bincr); |
| 734 | } |
| 735 | pos += line_length; |
| 736 | data += rincr; |
| 737 | } |
| 738 | wmb(); |
| 739 | |
| 740 | pixelmask = ((1ul << (width & 15)) - 1) << shift; |
| 741 | if (pixelmask) { |
| 742 | __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); |
| 743 | wmb(); |
| 744 | |
| 745 | pos = pos0 + bwidth*bincr; |
| 746 | data = data0 + bwidth; |
| 747 | bwidth = (width & 15) > 8; |
| 748 | |
| 749 | for (i = 0; i < height; ++i) { |
| 750 | u32 mask = bitrev[data[0]]; |
| 751 | if (bwidth) |
| 752 | mask |= bitrev[data[1]] << 8; |
| 753 | mask <<= shift; |
| 754 | __raw_writel(mask, fb_base + pos); |
| 755 | pos += line_length; |
| 756 | data += rincr; |
| 757 | } |
| 758 | wmb(); |
| 759 | } |
| 760 | __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); |
| 761 | } |
| 762 | |
| 763 | /* Disable opaque stipple mode. */ |
| 764 | __raw_writel((is8bpp |
| 765 | ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE |
| 766 | : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), |
| 767 | regs_base + TGA_MODE_REG); |
| 768 | } |
| 769 | |
| 770 | /** |
| 771 | * tgafb_fillrect - REQUIRED function. Can use generic routines if |
| 772 | * non acclerated hardware and packed pixel based. |
| 773 | * Draws a rectangle on the screen. |
| 774 | * |
| 775 | * @info: frame buffer structure that represents a single frame buffer |
| 776 | * @rect: structure defining the rectagle and operation. |
| 777 | */ |
| 778 | static void |
| 779 | tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 780 | { |
| 781 | struct tga_par *par = (struct tga_par *) info->par; |
| 782 | int is8bpp = info->var.bits_per_pixel == 8; |
| 783 | u32 dx, dy, width, height, vxres, vyres, color; |
| 784 | unsigned long pos, align, line_length, i, j; |
| 785 | void __iomem *regs_base; |
| 786 | void __iomem *fb_base; |
| 787 | |
| 788 | dx = rect->dx; |
| 789 | dy = rect->dy; |
| 790 | width = rect->width; |
| 791 | height = rect->height; |
| 792 | vxres = info->var.xres_virtual; |
| 793 | vyres = info->var.yres_virtual; |
| 794 | line_length = info->fix.line_length; |
| 795 | regs_base = par->tga_regs_base; |
| 796 | fb_base = par->tga_fb_base; |
| 797 | |
| 798 | /* Crop the rectangle to the screen. */ |
| 799 | if (dx > vxres || dy > vyres || !width || !height) |
| 800 | return; |
| 801 | if (dx + width > vxres) |
| 802 | width = vxres - dx; |
| 803 | if (dy + height > vyres) |
| 804 | height = vyres - dy; |
| 805 | |
| 806 | pos = dy * line_length + dx * (is8bpp ? 1 : 4); |
| 807 | |
| 808 | /* ??? We could implement ROP_XOR with opaque fill mode |
| 809 | and a RasterOp setting of GXxor, but as far as I can |
| 810 | tell, this mode is not actually used in the kernel. |
| 811 | Thus I am ignoring it for now. */ |
| 812 | if (rect->rop != ROP_COPY) { |
| 813 | cfb_fillrect(info, rect); |
| 814 | return; |
| 815 | } |
| 816 | |
| 817 | /* Expand the color value to fill 8 pixels. */ |
| 818 | color = rect->color; |
| 819 | if (is8bpp) { |
| 820 | color |= color << 8; |
| 821 | color |= color << 16; |
| 822 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); |
| 823 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); |
| 824 | } else { |
| 825 | if (color < 16) |
| 826 | color = ((u32 *)info->pseudo_palette)[color]; |
| 827 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); |
| 828 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); |
| 829 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG); |
| 830 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG); |
| 831 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG); |
| 832 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG); |
| 833 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG); |
| 834 | __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG); |
| 835 | } |
| 836 | |
| 837 | /* The DATA register holds the fill mask for block fill mode. |
| 838 | Since we're not stippling, this is all ones. */ |
| 839 | __raw_writel(0xffffffff, regs_base + TGA_DATA_REG); |
| 840 | |
| 841 | /* Enable block fill mode. */ |
| 842 | __raw_writel((is8bpp |
| 843 | ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL |
| 844 | : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL), |
| 845 | regs_base + TGA_MODE_REG); |
| 846 | wmb(); |
| 847 | |
| 848 | /* We can fill 2k pixels per operation. Notice blocks that fit |
| 849 | the width of the screen so that we can take advantage of this |
| 850 | and fill more than one line per write. */ |
| 851 | if (width == line_length) |
| 852 | width *= height, height = 1; |
| 853 | |
| 854 | /* The write into the frame buffer must be aligned to 4 bytes, |
| 855 | but we are allowed to encode the offset within the word in |
| 856 | the data word written. */ |
| 857 | align = (pos & 3) << 16; |
| 858 | pos &= -4; |
| 859 | |
| 860 | if (width <= 2048) { |
| 861 | u32 data; |
| 862 | |
| 863 | data = (width - 1) | align; |
| 864 | |
| 865 | for (i = 0; i < height; ++i) { |
| 866 | __raw_writel(data, fb_base + pos); |
| 867 | pos += line_length; |
| 868 | } |
| 869 | } else { |
| 870 | unsigned long Bpp = (is8bpp ? 1 : 4); |
| 871 | unsigned long nwidth = width & -2048; |
| 872 | u32 fdata, ldata; |
| 873 | |
| 874 | fdata = (2048 - 1) | align; |
| 875 | ldata = ((width & 2047) - 1) | align; |
| 876 | |
| 877 | for (i = 0; i < height; ++i) { |
| 878 | for (j = 0; j < nwidth; j += 2048) |
| 879 | __raw_writel(fdata, fb_base + pos + j*Bpp); |
| 880 | if (j < width) |
| 881 | __raw_writel(ldata, fb_base + pos + j*Bpp); |
| 882 | pos += line_length; |
| 883 | } |
| 884 | } |
| 885 | wmb(); |
| 886 | |
| 887 | /* Disable block fill mode. */ |
| 888 | __raw_writel((is8bpp |
| 889 | ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE |
| 890 | : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), |
| 891 | regs_base + TGA_MODE_REG); |
| 892 | } |
| 893 | |
| 894 | /** |
| 895 | * tgafb_copyarea - REQUIRED function. Can use generic routines if |
| 896 | * non acclerated hardware and packed pixel based. |
| 897 | * Copies on area of the screen to another area. |
| 898 | * |
| 899 | * @info: frame buffer structure that represents a single frame buffer |
| 900 | * @area: structure defining the source and destination. |
| 901 | */ |
| 902 | |
| 903 | /* Handle the special case of copying entire lines, e.g. during scrolling. |
| 904 | We can avoid a lot of needless computation in this case. In the 8bpp |
| 905 | case we need to use the COPY64 registers instead of mask writes into |
| 906 | the frame buffer to achieve maximum performance. */ |
| 907 | |
| 908 | static inline void |
| 909 | copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy, |
| 910 | u32 height, u32 width) |
| 911 | { |
| 912 | struct tga_par *par = (struct tga_par *) info->par; |
| 913 | void __iomem *tga_regs = par->tga_regs_base; |
| 914 | unsigned long dpos, spos, i, n64; |
| 915 | |
| 916 | /* Set up the MODE and PIXELSHIFT registers. */ |
| 917 | __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); |
| 918 | __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); |
| 919 | wmb(); |
| 920 | |
| 921 | n64 = (height * width) / 64; |
| 922 | |
| 923 | if (dy < sy) { |
| 924 | spos = (sy + height) * width; |
| 925 | dpos = (dy + height) * width; |
| 926 | |
| 927 | for (i = 0; i < n64; ++i) { |
| 928 | spos -= 64; |
| 929 | dpos -= 64; |
| 930 | __raw_writel(spos, tga_regs+TGA_COPY64_SRC); |
| 931 | wmb(); |
| 932 | __raw_writel(dpos, tga_regs+TGA_COPY64_DST); |
| 933 | wmb(); |
| 934 | } |
| 935 | } else { |
| 936 | spos = sy * width; |
| 937 | dpos = dy * width; |
| 938 | |
| 939 | for (i = 0; i < n64; ++i) { |
| 940 | __raw_writel(spos, tga_regs+TGA_COPY64_SRC); |
| 941 | wmb(); |
| 942 | __raw_writel(dpos, tga_regs+TGA_COPY64_DST); |
| 943 | wmb(); |
| 944 | spos += 64; |
| 945 | dpos += 64; |
| 946 | } |
| 947 | } |
| 948 | |
| 949 | /* Reset the MODE register to normal. */ |
| 950 | __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); |
| 951 | } |
| 952 | |
| 953 | static inline void |
| 954 | copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy, |
| 955 | u32 height, u32 width) |
| 956 | { |
| 957 | struct tga_par *par = (struct tga_par *) info->par; |
| 958 | void __iomem *tga_regs = par->tga_regs_base; |
| 959 | void __iomem *tga_fb = par->tga_fb_base; |
| 960 | void __iomem *src; |
| 961 | void __iomem *dst; |
| 962 | unsigned long i, n16; |
| 963 | |
| 964 | /* Set up the MODE and PIXELSHIFT registers. */ |
| 965 | __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); |
| 966 | __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); |
| 967 | wmb(); |
| 968 | |
| 969 | n16 = (height * width) / 16; |
| 970 | |
| 971 | if (dy < sy) { |
| 972 | src = tga_fb + (sy + height) * width * 4; |
| 973 | dst = tga_fb + (dy + height) * width * 4; |
| 974 | |
| 975 | for (i = 0; i < n16; ++i) { |
| 976 | src -= 64; |
| 977 | dst -= 64; |
| 978 | __raw_writel(0xffff, src); |
| 979 | wmb(); |
| 980 | __raw_writel(0xffff, dst); |
| 981 | wmb(); |
| 982 | } |
| 983 | } else { |
| 984 | src = tga_fb + sy * width * 4; |
| 985 | dst = tga_fb + dy * width * 4; |
| 986 | |
| 987 | for (i = 0; i < n16; ++i) { |
| 988 | __raw_writel(0xffff, src); |
| 989 | wmb(); |
| 990 | __raw_writel(0xffff, dst); |
| 991 | wmb(); |
| 992 | src += 64; |
| 993 | dst += 64; |
| 994 | } |
| 995 | } |
| 996 | |
| 997 | /* Reset the MODE register to normal. */ |
| 998 | __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); |
| 999 | } |
| 1000 | |
| 1001 | /* The general case of forward copy in 8bpp mode. */ |
| 1002 | static inline void |
| 1003 | copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy, |
| 1004 | u32 height, u32 width, u32 line_length) |
| 1005 | { |
| 1006 | struct tga_par *par = (struct tga_par *) info->par; |
| 1007 | unsigned long i, copied, left; |
| 1008 | unsigned long dpos, spos, dalign, salign, yincr; |
| 1009 | u32 smask_first, dmask_first, dmask_last; |
| 1010 | int pixel_shift, need_prime, need_second; |
| 1011 | unsigned long n64, n32, xincr_first; |
| 1012 | void __iomem *tga_regs; |
| 1013 | void __iomem *tga_fb; |
| 1014 | |
| 1015 | yincr = line_length; |
| 1016 | if (dy > sy) { |
| 1017 | dy += height - 1; |
| 1018 | sy += height - 1; |
| 1019 | yincr = -yincr; |
| 1020 | } |
| 1021 | |
| 1022 | /* Compute the offsets and alignments in the frame buffer. |
| 1023 | More than anything else, these control how we do copies. */ |
| 1024 | dpos = dy * line_length + dx; |
| 1025 | spos = sy * line_length + sx; |
| 1026 | dalign = dpos & 7; |
| 1027 | salign = spos & 7; |
| 1028 | dpos &= -8; |
| 1029 | spos &= -8; |
| 1030 | |
| 1031 | /* Compute the value for the PIXELSHIFT register. This controls |
| 1032 | both non-co-aligned source and destination and copy direction. */ |
| 1033 | if (dalign >= salign) |
| 1034 | pixel_shift = dalign - salign; |
| 1035 | else |
| 1036 | pixel_shift = 8 - (salign - dalign); |
| 1037 | |
| 1038 | /* Figure out if we need an additional priming step for the |
| 1039 | residue register. */ |
| 1040 | need_prime = (salign > dalign); |
| 1041 | if (need_prime) |
| 1042 | dpos -= 8; |
| 1043 | |
| 1044 | /* Begin by copying the leading unaligned destination. Copy enough |
| 1045 | to make the next destination address 32-byte aligned. */ |
| 1046 | copied = 32 - (dalign + (dpos & 31)); |
| 1047 | if (copied == 32) |
| 1048 | copied = 0; |
| 1049 | xincr_first = (copied + 7) & -8; |
| 1050 | smask_first = dmask_first = (1ul << copied) - 1; |
| 1051 | smask_first <<= salign; |
| 1052 | dmask_first <<= dalign + need_prime*8; |
| 1053 | if (need_prime && copied > 24) |
| 1054 | copied -= 8; |
| 1055 | left = width - copied; |
| 1056 | |
| 1057 | /* Care for small copies. */ |
| 1058 | if (copied > width) { |
| 1059 | u32 t; |
| 1060 | t = (1ul << width) - 1; |
| 1061 | t <<= dalign + need_prime*8; |
| 1062 | dmask_first &= t; |
| 1063 | left = 0; |
| 1064 | } |
| 1065 | |
| 1066 | /* Attempt to use 64-byte copies. This is only possible if the |
| 1067 | source and destination are co-aligned at 64 bytes. */ |
| 1068 | n64 = need_second = 0; |
| 1069 | if ((dpos & 63) == (spos & 63) |
| 1070 | && (height == 1 || line_length % 64 == 0)) { |
| 1071 | /* We may need a 32-byte copy to ensure 64 byte alignment. */ |
| 1072 | need_second = (dpos + xincr_first) & 63; |
| 1073 | if ((need_second & 32) != need_second) |
| 1074 | printk(KERN_ERR "tgafb: need_second wrong\n"); |
| 1075 | if (left >= need_second + 64) { |
| 1076 | left -= need_second; |
| 1077 | n64 = left / 64; |
| 1078 | left %= 64; |
| 1079 | } else |
| 1080 | need_second = 0; |
| 1081 | } |
| 1082 | |
| 1083 | /* Copy trailing full 32-byte sections. This will be the main |
| 1084 | loop if the 64 byte loop can't be used. */ |
| 1085 | n32 = left / 32; |
| 1086 | left %= 32; |
| 1087 | |
| 1088 | /* Copy the trailing unaligned destination. */ |
| 1089 | dmask_last = (1ul << left) - 1; |
| 1090 | |
| 1091 | tga_regs = par->tga_regs_base; |
| 1092 | tga_fb = par->tga_fb_base; |
| 1093 | |
| 1094 | /* Set up the MODE and PIXELSHIFT registers. */ |
| 1095 | __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG); |
| 1096 | __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG); |
| 1097 | wmb(); |
| 1098 | |
| 1099 | for (i = 0; i < height; ++i) { |
| 1100 | unsigned long j; |
| 1101 | void __iomem *sfb; |
| 1102 | void __iomem *dfb; |
| 1103 | |
| 1104 | sfb = tga_fb + spos; |
| 1105 | dfb = tga_fb + dpos; |
| 1106 | if (dmask_first) { |
| 1107 | __raw_writel(smask_first, sfb); |
| 1108 | wmb(); |
| 1109 | __raw_writel(dmask_first, dfb); |
| 1110 | wmb(); |
| 1111 | sfb += xincr_first; |
| 1112 | dfb += xincr_first; |
| 1113 | } |
| 1114 | |
| 1115 | if (need_second) { |
| 1116 | __raw_writel(0xffffffff, sfb); |
| 1117 | wmb(); |
| 1118 | __raw_writel(0xffffffff, dfb); |
| 1119 | wmb(); |
| 1120 | sfb += 32; |
| 1121 | dfb += 32; |
| 1122 | } |
| 1123 | |
| 1124 | if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63)) |
| 1125 | printk(KERN_ERR |
| 1126 | "tgafb: misaligned copy64 (s:%p, d:%p)\n", |
| 1127 | sfb, dfb); |
| 1128 | |
| 1129 | for (j = 0; j < n64; ++j) { |
| 1130 | __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC); |
| 1131 | wmb(); |
| 1132 | __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST); |
| 1133 | wmb(); |
| 1134 | sfb += 64; |
| 1135 | dfb += 64; |
| 1136 | } |
| 1137 | |
| 1138 | for (j = 0; j < n32; ++j) { |
| 1139 | __raw_writel(0xffffffff, sfb); |
| 1140 | wmb(); |
| 1141 | __raw_writel(0xffffffff, dfb); |
| 1142 | wmb(); |
| 1143 | sfb += 32; |
| 1144 | dfb += 32; |
| 1145 | } |
| 1146 | |
| 1147 | if (dmask_last) { |
| 1148 | __raw_writel(0xffffffff, sfb); |
| 1149 | wmb(); |
| 1150 | __raw_writel(dmask_last, dfb); |
| 1151 | wmb(); |
| 1152 | } |
| 1153 | |
| 1154 | spos += yincr; |
| 1155 | dpos += yincr; |
| 1156 | } |
| 1157 | |
| 1158 | /* Reset the MODE register to normal. */ |
| 1159 | __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); |
| 1160 | } |
| 1161 | |
| 1162 | /* The (almost) general case of backward copy in 8bpp mode. */ |
| 1163 | static inline void |
| 1164 | copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy, |
| 1165 | u32 height, u32 width, u32 line_length, |
| 1166 | const struct fb_copyarea *area) |
| 1167 | { |
| 1168 | struct tga_par *par = (struct tga_par *) info->par; |
| 1169 | unsigned long i, left, yincr; |
| 1170 | unsigned long depos, sepos, dealign, sealign; |
| 1171 | u32 mask_first, mask_last; |
| 1172 | unsigned long n32; |
| 1173 | void __iomem *tga_regs; |
| 1174 | void __iomem *tga_fb; |
| 1175 | |
| 1176 | yincr = line_length; |
| 1177 | if (dy > sy) { |
| 1178 | dy += height - 1; |
| 1179 | sy += height - 1; |
| 1180 | yincr = -yincr; |
| 1181 | } |
| 1182 | |
| 1183 | /* Compute the offsets and alignments in the frame buffer. |
| 1184 | More than anything else, these control how we do copies. */ |
| 1185 | depos = dy * line_length + dx + width; |
| 1186 | sepos = sy * line_length + sx + width; |
| 1187 | dealign = depos & 7; |
| 1188 | sealign = sepos & 7; |
| 1189 | |
| 1190 | /* ??? The documentation appears to be incorrect (or very |
| 1191 | misleading) wrt how pixel shifting works in backward copy |
| 1192 | mode, i.e. when PIXELSHIFT is negative. I give up for now. |
| 1193 | Do handle the common case of co-aligned backward copies, |
| 1194 | but frob everything else back on generic code. */ |
| 1195 | if (dealign != sealign) { |
| 1196 | cfb_copyarea(info, area); |
| 1197 | return; |
| 1198 | } |
| 1199 | |
| 1200 | /* We begin the copy with the trailing pixels of the |
| 1201 | unaligned destination. */ |
| 1202 | mask_first = (1ul << dealign) - 1; |
| 1203 | left = width - dealign; |
| 1204 | |
| 1205 | /* Care for small copies. */ |
| 1206 | if (dealign > width) { |
| 1207 | mask_first ^= (1ul << (dealign - width)) - 1; |
| 1208 | left = 0; |
| 1209 | } |
| 1210 | |
| 1211 | /* Next copy full words at a time. */ |
| 1212 | n32 = left / 32; |
| 1213 | left %= 32; |
| 1214 | |
| 1215 | /* Finally copy the unaligned head of the span. */ |
| 1216 | mask_last = -1 << (32 - left); |
| 1217 | |
| 1218 | tga_regs = par->tga_regs_base; |
| 1219 | tga_fb = par->tga_fb_base; |
| 1220 | |
| 1221 | /* Set up the MODE and PIXELSHIFT registers. */ |
| 1222 | __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG); |
| 1223 | __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); |
| 1224 | wmb(); |
| 1225 | |
| 1226 | for (i = 0; i < height; ++i) { |
| 1227 | unsigned long j; |
| 1228 | void __iomem *sfb; |
| 1229 | void __iomem *dfb; |
| 1230 | |
| 1231 | sfb = tga_fb + sepos; |
| 1232 | dfb = tga_fb + depos; |
| 1233 | if (mask_first) { |
| 1234 | __raw_writel(mask_first, sfb); |
| 1235 | wmb(); |
| 1236 | __raw_writel(mask_first, dfb); |
| 1237 | wmb(); |
| 1238 | } |
| 1239 | |
| 1240 | for (j = 0; j < n32; ++j) { |
| 1241 | sfb -= 32; |
| 1242 | dfb -= 32; |
| 1243 | __raw_writel(0xffffffff, sfb); |
| 1244 | wmb(); |
| 1245 | __raw_writel(0xffffffff, dfb); |
| 1246 | wmb(); |
| 1247 | } |
| 1248 | |
| 1249 | if (mask_last) { |
| 1250 | sfb -= 32; |
| 1251 | dfb -= 32; |
| 1252 | __raw_writel(mask_last, sfb); |
| 1253 | wmb(); |
| 1254 | __raw_writel(mask_last, dfb); |
| 1255 | wmb(); |
| 1256 | } |
| 1257 | |
| 1258 | sepos += yincr; |
| 1259 | depos += yincr; |
| 1260 | } |
| 1261 | |
| 1262 | /* Reset the MODE register to normal. */ |
| 1263 | __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); |
| 1264 | } |
| 1265 | |
| 1266 | static void |
| 1267 | tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area) |
| 1268 | { |
| 1269 | unsigned long dx, dy, width, height, sx, sy, vxres, vyres; |
| 1270 | unsigned long line_length, bpp; |
| 1271 | |
| 1272 | dx = area->dx; |
| 1273 | dy = area->dy; |
| 1274 | width = area->width; |
| 1275 | height = area->height; |
| 1276 | sx = area->sx; |
| 1277 | sy = area->sy; |
| 1278 | vxres = info->var.xres_virtual; |
| 1279 | vyres = info->var.yres_virtual; |
| 1280 | line_length = info->fix.line_length; |
| 1281 | |
| 1282 | /* The top left corners must be in the virtual screen. */ |
| 1283 | if (dx > vxres || sx > vxres || dy > vyres || sy > vyres) |
| 1284 | return; |
| 1285 | |
| 1286 | /* Clip the destination. */ |
| 1287 | if (dx + width > vxres) |
| 1288 | width = vxres - dx; |
| 1289 | if (dy + height > vyres) |
| 1290 | height = vyres - dy; |
| 1291 | |
| 1292 | /* The source must be completely inside the virtual screen. */ |
| 1293 | if (sx + width > vxres || sy + height > vyres) |
| 1294 | return; |
| 1295 | |
| 1296 | bpp = info->var.bits_per_pixel; |
| 1297 | |
| 1298 | /* Detect copies of the entire line. */ |
| 1299 | if (width * (bpp >> 3) == line_length) { |
| 1300 | if (bpp == 8) |
| 1301 | copyarea_line_8bpp(info, dy, sy, height, width); |
| 1302 | else |
| 1303 | copyarea_line_32bpp(info, dy, sy, height, width); |
| 1304 | } |
| 1305 | |
| 1306 | /* ??? The documentation is unclear to me exactly how the pixelshift |
| 1307 | register works in 32bpp mode. Since I don't have hardware to test, |
| 1308 | give up for now and fall back on the generic routines. */ |
| 1309 | else if (bpp == 32) |
| 1310 | cfb_copyarea(info, area); |
| 1311 | |
| 1312 | /* Detect overlapping source and destination that requires |
| 1313 | a backward copy. */ |
| 1314 | else if (dy == sy && dx > sx && dx < sx + width) |
| 1315 | copyarea_backward_8bpp(info, dx, dy, sx, sy, height, |
| 1316 | width, line_length, area); |
| 1317 | else |
| 1318 | copyarea_foreward_8bpp(info, dx, dy, sx, sy, height, |
| 1319 | width, line_length); |
| 1320 | } |
| 1321 | |
| 1322 | |
| 1323 | /* |
| 1324 | * Initialisation |
| 1325 | */ |
| 1326 | |
| 1327 | static void |
| 1328 | tgafb_init_fix(struct fb_info *info) |
| 1329 | { |
| 1330 | struct tga_par *par = (struct tga_par *)info->par; |
| 1331 | u8 tga_type = par->tga_type; |
| 1332 | const char *tga_type_name; |
| 1333 | |
| 1334 | switch (tga_type) { |
| 1335 | case TGA_TYPE_8PLANE: |
| 1336 | tga_type_name = "Digital ZLXp-E1"; |
| 1337 | break; |
| 1338 | case TGA_TYPE_24PLANE: |
| 1339 | tga_type_name = "Digital ZLXp-E2"; |
| 1340 | break; |
| 1341 | case TGA_TYPE_24PLUSZ: |
| 1342 | tga_type_name = "Digital ZLXp-E3"; |
| 1343 | break; |
| 1344 | default: |
| 1345 | tga_type_name = "Unknown"; |
| 1346 | break; |
| 1347 | } |
| 1348 | |
| 1349 | strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id)); |
| 1350 | |
| 1351 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
| 1352 | info->fix.type_aux = 0; |
| 1353 | info->fix.visual = (tga_type == TGA_TYPE_8PLANE |
| 1354 | ? FB_VISUAL_PSEUDOCOLOR |
| 1355 | : FB_VISUAL_TRUECOLOR); |
| 1356 | |
| 1357 | info->fix.line_length = par->xres * (par->bits_per_pixel >> 3); |
| 1358 | info->fix.smem_start = (size_t) par->tga_fb_base; |
| 1359 | info->fix.smem_len = info->fix.line_length * par->yres; |
| 1360 | info->fix.mmio_start = (size_t) par->tga_regs_base; |
| 1361 | info->fix.mmio_len = 512; |
| 1362 | |
| 1363 | info->fix.xpanstep = 0; |
| 1364 | info->fix.ypanstep = 0; |
| 1365 | info->fix.ywrapstep = 0; |
| 1366 | |
| 1367 | info->fix.accel = FB_ACCEL_DEC_TGA; |
| 1368 | } |
| 1369 | |
| 1370 | static __devinit int |
| 1371 | tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1372 | { |
| 1373 | static unsigned int const fb_offset_presets[4] = { |
| 1374 | TGA_8PLANE_FB_OFFSET, |
| 1375 | TGA_24PLANE_FB_OFFSET, |
| 1376 | 0xffffffff, |
| 1377 | TGA_24PLUSZ_FB_OFFSET |
| 1378 | }; |
| 1379 | |
| 1380 | struct all_info { |
| 1381 | struct fb_info info; |
| 1382 | struct tga_par par; |
| 1383 | u32 pseudo_palette[16]; |
| 1384 | } *all; |
| 1385 | |
| 1386 | void __iomem *mem_base; |
| 1387 | unsigned long bar0_start, bar0_len; |
| 1388 | u8 tga_type; |
| 1389 | int ret; |
| 1390 | |
| 1391 | /* Enable device in PCI config. */ |
| 1392 | if (pci_enable_device(pdev)) { |
| 1393 | printk(KERN_ERR "tgafb: Cannot enable PCI device\n"); |
| 1394 | return -ENODEV; |
| 1395 | } |
| 1396 | |
| 1397 | /* Allocate the fb and par structures. */ |
| 1398 | all = kmalloc(sizeof(*all), GFP_KERNEL); |
| 1399 | if (!all) { |
| 1400 | printk(KERN_ERR "tgafb: Cannot allocate memory\n"); |
| 1401 | return -ENOMEM; |
| 1402 | } |
| 1403 | memset(all, 0, sizeof(*all)); |
| 1404 | pci_set_drvdata(pdev, all); |
| 1405 | |
| 1406 | /* Request the mem regions. */ |
| 1407 | bar0_start = pci_resource_start(pdev, 0); |
| 1408 | bar0_len = pci_resource_len(pdev, 0); |
| 1409 | ret = -ENODEV; |
| 1410 | if (!request_mem_region (bar0_start, bar0_len, "tgafb")) { |
| 1411 | printk(KERN_ERR "tgafb: cannot reserve FB region\n"); |
| 1412 | goto err0; |
| 1413 | } |
| 1414 | |
| 1415 | /* Map the framebuffer. */ |
| 1416 | mem_base = ioremap(bar0_start, bar0_len); |
| 1417 | if (!mem_base) { |
| 1418 | printk(KERN_ERR "tgafb: Cannot map MMIO\n"); |
| 1419 | goto err1; |
| 1420 | } |
| 1421 | |
| 1422 | /* Grab info about the card. */ |
| 1423 | tga_type = (readl(mem_base) >> 12) & 0x0f; |
| 1424 | all->par.pdev = pdev; |
| 1425 | all->par.tga_mem_base = mem_base; |
| 1426 | all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type]; |
| 1427 | all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET; |
| 1428 | all->par.tga_type = tga_type; |
| 1429 | pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev); |
| 1430 | |
| 1431 | /* Setup framebuffer. */ |
| 1432 | all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | |
| 1433 | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT; |
| 1434 | all->info.fbops = &tgafb_ops; |
| 1435 | all->info.screen_base = all->par.tga_fb_base; |
| 1436 | all->info.par = &all->par; |
| 1437 | all->info.pseudo_palette = all->pseudo_palette; |
| 1438 | |
| 1439 | /* This should give a reasonable default video mode. */ |
| 1440 | |
| 1441 | ret = fb_find_mode(&all->info.var, &all->info, mode_option, |
| 1442 | NULL, 0, NULL, |
| 1443 | tga_type == TGA_TYPE_8PLANE ? 8 : 32); |
| 1444 | if (ret == 0 || ret == 4) { |
| 1445 | printk(KERN_ERR "tgafb: Could not find valid video mode\n"); |
| 1446 | ret = -EINVAL; |
| 1447 | goto err1; |
| 1448 | } |
| 1449 | |
| 1450 | if (fb_alloc_cmap(&all->info.cmap, 256, 0)) { |
| 1451 | printk(KERN_ERR "tgafb: Could not allocate color map\n"); |
| 1452 | ret = -ENOMEM; |
| 1453 | goto err1; |
| 1454 | } |
| 1455 | |
| 1456 | tgafb_set_par(&all->info); |
| 1457 | tgafb_init_fix(&all->info); |
| 1458 | |
| 1459 | all->info.device = &pdev->dev; |
| 1460 | if (register_framebuffer(&all->info) < 0) { |
| 1461 | printk(KERN_ERR "tgafb: Could not register framebuffer\n"); |
| 1462 | ret = -EINVAL; |
| 1463 | goto err1; |
| 1464 | } |
| 1465 | |
| 1466 | printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", |
| 1467 | all->par.tga_chip_rev); |
| 1468 | printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", |
| 1469 | pdev->bus->number, PCI_SLOT(pdev->devfn), |
| 1470 | PCI_FUNC(pdev->devfn)); |
| 1471 | printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n", |
| 1472 | all->info.node, all->info.fix.id, bar0_start); |
| 1473 | |
| 1474 | return 0; |
| 1475 | |
| 1476 | err1: |
| 1477 | release_mem_region(bar0_start, bar0_len); |
| 1478 | err0: |
| 1479 | kfree(all); |
| 1480 | return ret; |
| 1481 | } |
| 1482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | static void __exit |
| 1484 | tgafb_pci_unregister(struct pci_dev *pdev) |
| 1485 | { |
| 1486 | struct fb_info *info = pci_get_drvdata(pdev); |
| 1487 | struct tga_par *par = info->par; |
| 1488 | |
| 1489 | if (!info) |
| 1490 | return; |
| 1491 | unregister_framebuffer(info); |
| 1492 | iounmap(par->tga_mem_base); |
| 1493 | release_mem_region(pci_resource_start(pdev, 0), |
| 1494 | pci_resource_len(pdev, 0)); |
| 1495 | kfree(info); |
| 1496 | } |
| 1497 | |
Adrian Bunk | 62b56fa | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1498 | #ifdef MODULE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1499 | static void __exit |
| 1500 | tgafb_exit(void) |
| 1501 | { |
| 1502 | pci_unregister_driver(&tgafb_driver); |
| 1503 | } |
| 1504 | #endif /* MODULE */ |
| 1505 | |
| 1506 | #ifndef MODULE |
| 1507 | int __init |
| 1508 | tgafb_setup(char *arg) |
| 1509 | { |
| 1510 | char *this_opt; |
| 1511 | |
| 1512 | if (arg && *arg) { |
| 1513 | while ((this_opt = strsep(&arg, ","))) { |
| 1514 | if (!*this_opt) |
| 1515 | continue; |
| 1516 | if (!strncmp(this_opt, "mode:", 5)) |
| 1517 | mode_option = this_opt+5; |
| 1518 | else |
| 1519 | printk(KERN_ERR |
| 1520 | "tgafb: unknown parameter %s\n", |
| 1521 | this_opt); |
| 1522 | } |
| 1523 | } |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | #endif /* !MODULE */ |
| 1528 | |
| 1529 | int __init |
| 1530 | tgafb_init(void) |
| 1531 | { |
| 1532 | #ifndef MODULE |
| 1533 | char *option = NULL; |
| 1534 | |
| 1535 | if (fb_get_options("tgafb", &option)) |
| 1536 | return -ENODEV; |
| 1537 | tgafb_setup(option); |
| 1538 | #endif |
| 1539 | return pci_register_driver(&tgafb_driver); |
| 1540 | } |
| 1541 | |
| 1542 | /* |
| 1543 | * Modularisation |
| 1544 | */ |
| 1545 | |
| 1546 | module_init(tgafb_init); |
| 1547 | |
| 1548 | #ifdef MODULE |
| 1549 | module_exit(tgafb_exit); |
| 1550 | #endif |
| 1551 | |
| 1552 | MODULE_DESCRIPTION("framebuffer driver for TGA chipset"); |
| 1553 | MODULE_LICENSE("GPL"); |