| Anirudh Ghayal | 6ece10a | 2014-01-10 16:44:46 +0530 | [diff] [blame] | 1 | Qualcomm Technologies Memory Accelerator |
| 2 | |
| 3 | Memory accelerator configures the power-mode (corner) for the |
| 4 | accelerator. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: Must be "qcom,mem-acc-regulator" |
| 8 | - regulator-name: A string used to describe the regulator |
| 9 | - regulator-min-microvolt: Minimum corner value as min constraint, which |
| 10 | should be 1 for SVS corner |
| 11 | - regulator-max-microvolt: Maximum corner value as max constraint, which |
| 12 | should be 4 for SUPER_TURBO or 3 for TURBO |
| 13 | - qcom,corner-acc-map Array which maps the APC (application processor) |
| 14 | corner value to the accelerator corner. |
| 15 | [0] maps APC SVS corner (1) to accelerator SVS corner |
| 16 | [1] maps APC NOMINAL corner (2) to accelerator NOMINAL corner |
| 17 | [2] maps APC TURBO corner (3) to accelerator TURBO corner |
| 18 | |
| 19 | Optional properties: |
| 20 | - reg: Register addresses for acc-en and acc-sel-l1 acc-sel-l2 control. |
| 21 | - reg-names: Register names. Must be "acc-sel-l1", "acc-sel-l2", "acc-en". |
| 22 | A given mem-acc-regulator driver must have "acc-sel-l1" or |
| 23 | "acc-sel-l2" reg-names property and related register address |
| 24 | property. |
| 25 | - qcom,acc-en-bit-pos Array which specifies bit positions in the |
| 26 | 'acc-en' register. Setting these bits forces the |
| 27 | the acclerator to use the corner value specified |
| 28 | in the 'acc-sel-l1' and 'acc-sel-l2' register. |
| 29 | - qcom,acc-sel-l1-bit-pos Array which specifies bit positions in the |
| 30 | 'acc-sel-l1' register. Each element in this array |
| 31 | is the LSB of a 2-bit value. This 2-bit value |
| 32 | specifies the corner value used by the |
| 33 | accelerator for L1 cache. |
| 34 | - qcom,acc-sel-l2-bit-pos Array which specifies bit positions in the |
| 35 | 'acc-sel-l2' register. Each element in this array |
| 36 | is the LSB of a 2-bit value. This 2-bit value |
| 37 | specifies the corner value used by the |
| 38 | accelerator for L2 cache. |
| 39 | |
| 40 | mem_acc_vreg_corner: regulator@fd4aa044 { |
| 41 | compatible = "qcom,mem-acc-regulator"; |
| 42 | reg = <0xfd4aa048 0x1>, <0xfd4aa044 0x1>, <0xfd4af000 0x1>; |
| 43 | reg-names = "acc-en", "acc-sel-l1" , "acc-sel-l2"; |
| 44 | regulator-name = "mem_acc_corner"; |
| 45 | regulator-min-microvolt = <1>; |
| 46 | regulator-max-microvolt = <3>; |
| 47 | |
| 48 | qcom,acc-en-bit-pos = <0>; |
| 49 | qcom,acc-sel-l1-bit-pos = <0>; |
| 50 | qcom,acc-sel-l2-bit-pos = <0>; |
| 51 | qcom,corner-acc-map = <0 1 3>; |
| 52 | }; |