| Philipp Zabel | d3ca195 | 2009-05-28 07:05:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * GPIO and IRQ definitions for HP iPAQ hx4700 |
| 3 | * |
| 4 | * Copyright (c) 2008 Philipp Zabel |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef _HX4700_H_ |
| 13 | #define _HX4700_H_ |
| 14 | |
| 15 | #include <linux/gpio.h> |
| 16 | #include <linux/mfd/asic3.h> |
| 17 | |
| 18 | #define HX4700_ASIC3_GPIO_BASE NR_BUILTIN_GPIO |
| 19 | #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) |
| 20 | |
| 21 | /* |
| 22 | * PXA GPIOs |
| 23 | */ |
| 24 | |
| 25 | #define GPIO0_HX4700_nKEY_POWER 0 |
| 26 | #define GPIO12_HX4700_ASIC3_IRQ 12 |
| 27 | #define GPIO13_HX4700_W3220_IRQ 13 |
| 28 | #define GPIO14_HX4700_nWLAN_IRQ 14 |
| 29 | #define GPIO18_HX4700_RDY 18 |
| 30 | #define GPIO22_HX4700_LCD_RL 22 |
| 31 | #define GPIO27_HX4700_CODEC_ON 27 |
| 32 | #define GPIO32_HX4700_RS232_ON 32 |
| 33 | #define GPIO52_HX4700_CPU_nBATT_FAULT 52 |
| 34 | #define GPIO58_HX4700_TSC2046_nPENIRQ 58 |
| 35 | #define GPIO59_HX4700_LCD_PC1 59 |
| 36 | #define GPIO60_HX4700_CF_RNB 60 |
| 37 | #define GPIO61_HX4700_W3220_nRESET 61 |
| 38 | #define GPIO62_HX4700_LCD_nRESET 62 |
| 39 | #define GPIO63_HX4700_CPU_SS_nRESET 63 |
| 40 | #define GPIO65_HX4700_TSC2046_PEN_PU 65 |
| 41 | #define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 |
| 42 | #define GPIO67_HX4700_EUART_PS 67 |
| 43 | #define GPIO70_HX4700_LCD_SLIN1 70 |
| 44 | #define GPIO71_HX4700_ASIC3_nRESET 71 |
| 45 | #define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 |
| 46 | #define GPIO73_HX4700_LCD_UD_1 73 |
| 47 | #define GPIO75_HX4700_EARPHONE_nDET 75 |
| 48 | #define GPIO76_HX4700_USBC_PUEN 76 |
| 49 | #define GPIO81_HX4700_CPU_GP_nRESET 81 |
| 50 | #define GPIO82_HX4700_EUART_RESET 82 |
| 51 | #define GPIO83_HX4700_WLAN_nRESET 83 |
| 52 | #define GPIO84_HX4700_LCD_SQN 84 |
| 53 | #define GPIO85_HX4700_nPCE1 85 |
| 54 | #define GPIO88_HX4700_TSC2046_CS 88 |
| 55 | #define GPIO91_HX4700_FLASH_VPEN 91 |
| 56 | #define GPIO92_HX4700_HP_DRIVER 92 |
| 57 | #define GPIO93_HX4700_EUART_INT 93 |
| 58 | #define GPIO94_HX4700_KEY_MAIL 94 |
| 59 | #define GPIO95_HX4700_BATT_OFF 95 |
| 60 | #define GPIO96_HX4700_BQ24022_ISET2 96 |
| 61 | #define GPIO97_HX4700_nBL_DETECT 97 |
| 62 | #define GPIO99_HX4700_KEY_CONTACTS 99 |
| 63 | #define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ |
| 64 | #define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 |
| 65 | #define GPIO103_HX4700_SYNAPTICS_INT 103 |
| 66 | #define GPIO105_HX4700_nIR_ON 105 |
| 67 | #define GPIO106_HX4700_CPU_BT_nRESET 106 |
| 68 | #define GPIO107_HX4700_SPK_nSD 107 |
| 69 | #define GPIO109_HX4700_CODEC_nPDN 109 |
| 70 | #define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 |
| 71 | #define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 |
| 72 | #define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 |
| 73 | #define GPIO114_HX4700_CF_RESET 114 |
| 74 | #define GPIO116_HX4700_CPU_HW_nRESET 116 |
| 75 | |
| 76 | /* |
| 77 | * ASIC3 GPIOs |
| 78 | */ |
| 79 | |
| 80 | #define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) |
| 81 | #define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) |
| 82 | |
| 83 | #define GPIOC0_LED_RED (GPIOC_BASE + 0) |
| 84 | #define GPIOC1_LED_GREEN (GPIOC_BASE + 1) |
| 85 | #define GPIOC2_LED_BLUE (GPIOC_BASE + 2) |
| 86 | #define GPIOC3_nSD_CS (GPIOC_BASE + 3) |
| 87 | #define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ |
| 88 | #define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ |
| 89 | #define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ |
| 90 | #define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ |
| 91 | #define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ |
| 92 | #define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ |
| 93 | #define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ |
| 94 | #define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ |
| 95 | #define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ |
| 96 | #define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ |
| 97 | #define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ |
| 98 | #define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ |
| 99 | |
| 100 | #define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ |
| 101 | #define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) |
| 102 | #define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) |
| 103 | #define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) |
| 104 | #define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ |
| 105 | #define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ |
| 106 | #define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) |
| 107 | #define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) |
| 108 | #define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ |
| 109 | #define GPIOD9_nAC_IN (GPIOD_BASE + 9) |
| 110 | #define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ |
| 111 | #define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ |
| 112 | #define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ |
| 113 | #define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ |
| 114 | #define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) |
| 115 | #define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ |
| 116 | |
| 117 | /* |
| 118 | * EGPIOs |
| 119 | */ |
| 120 | |
| 121 | #define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ |
| 122 | #define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ |
| 123 | #define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ |
| 124 | #define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ |
| 125 | #define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ |
| 126 | #define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ |
| 127 | #define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ |
| 128 | #define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ |
| 129 | #define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ |
| 130 | |
| 131 | #endif /* _HX4700_H_ */ |