Dimitris Papastamos | 6b3860b | 2011-07-15 13:51:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm8983.c -- WM8983 ALSA SoC Audio driver |
| 3 | * |
| 4 | * Copyright 2011 Wolfson Microelectronics plc |
| 5 | * |
| 6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/pm.h> |
| 18 | #include <linux/i2c.h> |
| 19 | #include <linux/spi/spi.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <sound/core.h> |
| 22 | #include <sound/pcm.h> |
| 23 | #include <sound/pcm_params.h> |
| 24 | #include <sound/soc.h> |
| 25 | #include <sound/initval.h> |
| 26 | #include <sound/tlv.h> |
| 27 | |
| 28 | #include "wm8983.h" |
| 29 | |
| 30 | static const u16 wm8983_reg_defs[WM8983_MAX_REGISTER + 1] = { |
| 31 | [0x00] = 0x0000, /* R0 - Software Reset */ |
| 32 | [0x01] = 0x0000, /* R1 - Power management 1 */ |
| 33 | [0x02] = 0x0000, /* R2 - Power management 2 */ |
| 34 | [0x03] = 0x0000, /* R3 - Power management 3 */ |
| 35 | [0x04] = 0x0050, /* R4 - Audio Interface */ |
| 36 | [0x05] = 0x0000, /* R5 - Companding control */ |
| 37 | [0x06] = 0x0140, /* R6 - Clock Gen control */ |
| 38 | [0x07] = 0x0000, /* R7 - Additional control */ |
| 39 | [0x08] = 0x0000, /* R8 - GPIO Control */ |
| 40 | [0x09] = 0x0000, /* R9 - Jack Detect Control 1 */ |
| 41 | [0x0A] = 0x0000, /* R10 - DAC Control */ |
| 42 | [0x0B] = 0x00FF, /* R11 - Left DAC digital Vol */ |
| 43 | [0x0C] = 0x00FF, /* R12 - Right DAC digital vol */ |
| 44 | [0x0D] = 0x0000, /* R13 - Jack Detect Control 2 */ |
| 45 | [0x0E] = 0x0100, /* R14 - ADC Control */ |
| 46 | [0x0F] = 0x00FF, /* R15 - Left ADC Digital Vol */ |
| 47 | [0x10] = 0x00FF, /* R16 - Right ADC Digital Vol */ |
| 48 | [0x12] = 0x012C, /* R18 - EQ1 - low shelf */ |
| 49 | [0x13] = 0x002C, /* R19 - EQ2 - peak 1 */ |
| 50 | [0x14] = 0x002C, /* R20 - EQ3 - peak 2 */ |
| 51 | [0x15] = 0x002C, /* R21 - EQ4 - peak 3 */ |
| 52 | [0x16] = 0x002C, /* R22 - EQ5 - high shelf */ |
| 53 | [0x18] = 0x0032, /* R24 - DAC Limiter 1 */ |
| 54 | [0x19] = 0x0000, /* R25 - DAC Limiter 2 */ |
| 55 | [0x1B] = 0x0000, /* R27 - Notch Filter 1 */ |
| 56 | [0x1C] = 0x0000, /* R28 - Notch Filter 2 */ |
| 57 | [0x1D] = 0x0000, /* R29 - Notch Filter 3 */ |
| 58 | [0x1E] = 0x0000, /* R30 - Notch Filter 4 */ |
| 59 | [0x20] = 0x0038, /* R32 - ALC control 1 */ |
| 60 | [0x21] = 0x000B, /* R33 - ALC control 2 */ |
| 61 | [0x22] = 0x0032, /* R34 - ALC control 3 */ |
| 62 | [0x23] = 0x0000, /* R35 - Noise Gate */ |
| 63 | [0x24] = 0x0008, /* R36 - PLL N */ |
| 64 | [0x25] = 0x000C, /* R37 - PLL K 1 */ |
| 65 | [0x26] = 0x0093, /* R38 - PLL K 2 */ |
| 66 | [0x27] = 0x00E9, /* R39 - PLL K 3 */ |
| 67 | [0x29] = 0x0000, /* R41 - 3D control */ |
| 68 | [0x2A] = 0x0000, /* R42 - OUT4 to ADC */ |
| 69 | [0x2B] = 0x0000, /* R43 - Beep control */ |
| 70 | [0x2C] = 0x0033, /* R44 - Input ctrl */ |
| 71 | [0x2D] = 0x0010, /* R45 - Left INP PGA gain ctrl */ |
| 72 | [0x2E] = 0x0010, /* R46 - Right INP PGA gain ctrl */ |
| 73 | [0x2F] = 0x0100, /* R47 - Left ADC BOOST ctrl */ |
| 74 | [0x30] = 0x0100, /* R48 - Right ADC BOOST ctrl */ |
| 75 | [0x31] = 0x0002, /* R49 - Output ctrl */ |
| 76 | [0x32] = 0x0001, /* R50 - Left mixer ctrl */ |
| 77 | [0x33] = 0x0001, /* R51 - Right mixer ctrl */ |
| 78 | [0x34] = 0x0039, /* R52 - LOUT1 (HP) volume ctrl */ |
| 79 | [0x35] = 0x0039, /* R53 - ROUT1 (HP) volume ctrl */ |
| 80 | [0x36] = 0x0039, /* R54 - LOUT2 (SPK) volume ctrl */ |
| 81 | [0x37] = 0x0039, /* R55 - ROUT2 (SPK) volume ctrl */ |
| 82 | [0x38] = 0x0001, /* R56 - OUT3 mixer ctrl */ |
| 83 | [0x39] = 0x0001, /* R57 - OUT4 (MONO) mix ctrl */ |
| 84 | [0x3D] = 0x0000 /* R61 - BIAS CTRL */ |
| 85 | }; |
| 86 | |
| 87 | static const struct wm8983_reg_access { |
| 88 | u16 read; /* Mask of readable bits */ |
| 89 | u16 write; /* Mask of writable bits */ |
| 90 | } wm8983_access_masks[WM8983_MAX_REGISTER + 1] = { |
| 91 | [0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */ |
| 92 | [0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */ |
| 93 | [0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */ |
| 94 | [0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */ |
| 95 | [0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */ |
| 96 | [0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */ |
| 97 | [0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */ |
| 98 | [0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */ |
| 99 | [0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */ |
| 100 | [0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */ |
| 101 | [0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */ |
| 102 | [0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */ |
| 103 | [0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */ |
| 104 | [0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */ |
| 105 | [0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */ |
| 106 | [0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */ |
| 107 | [0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */ |
| 108 | [0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */ |
| 109 | [0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */ |
| 110 | [0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */ |
| 111 | [0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */ |
| 112 | [0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */ |
| 113 | [0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */ |
| 114 | [0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */ |
| 115 | [0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */ |
| 116 | [0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */ |
| 117 | [0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */ |
| 118 | [0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */ |
| 119 | [0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */ |
| 120 | [0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */ |
| 121 | [0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */ |
| 122 | [0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */ |
| 123 | [0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */ |
| 124 | [0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */ |
| 125 | [0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */ |
| 126 | [0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */ |
| 127 | [0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */ |
| 128 | [0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */ |
| 129 | [0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */ |
| 130 | [0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */ |
| 131 | [0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */ |
| 132 | [0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */ |
| 133 | [0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */ |
| 134 | [0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */ |
| 135 | [0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */ |
| 136 | [0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */ |
| 137 | [0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */ |
| 138 | [0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */ |
| 139 | [0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */ |
| 140 | [0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */ |
| 141 | [0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */ |
| 142 | [0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */ |
| 143 | [0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */ |
| 144 | [0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */ |
| 145 | }; |
| 146 | |
| 147 | /* vol/gain update regs */ |
| 148 | static const int vol_update_regs[] = { |
| 149 | WM8983_LEFT_DAC_DIGITAL_VOL, |
| 150 | WM8983_RIGHT_DAC_DIGITAL_VOL, |
| 151 | WM8983_LEFT_ADC_DIGITAL_VOL, |
| 152 | WM8983_RIGHT_ADC_DIGITAL_VOL, |
| 153 | WM8983_LOUT1_HP_VOLUME_CTRL, |
| 154 | WM8983_ROUT1_HP_VOLUME_CTRL, |
| 155 | WM8983_LOUT2_SPK_VOLUME_CTRL, |
| 156 | WM8983_ROUT2_SPK_VOLUME_CTRL, |
| 157 | WM8983_LEFT_INP_PGA_GAIN_CTRL, |
| 158 | WM8983_RIGHT_INP_PGA_GAIN_CTRL |
| 159 | }; |
| 160 | |
| 161 | struct wm8983_priv { |
| 162 | enum snd_soc_control_type control_type; |
| 163 | u32 sysclk; |
| 164 | u32 bclk; |
| 165 | }; |
| 166 | |
| 167 | static const struct { |
| 168 | int div; |
| 169 | int ratio; |
| 170 | } fs_ratios[] = { |
| 171 | { 10, 128 }, |
| 172 | { 15, 192 }, |
| 173 | { 20, 256 }, |
| 174 | { 30, 384 }, |
| 175 | { 40, 512 }, |
| 176 | { 60, 768 }, |
| 177 | { 80, 1024 }, |
| 178 | { 120, 1536 } |
| 179 | }; |
| 180 | |
| 181 | static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 }; |
| 182 | |
| 183 | static const int bclk_divs[] = { |
| 184 | 1, 2, 4, 8, 16, 32 |
| 185 | }; |
| 186 | |
| 187 | static int eqmode_get(struct snd_kcontrol *kcontrol, |
| 188 | struct snd_ctl_elem_value *ucontrol); |
| 189 | static int eqmode_put(struct snd_kcontrol *kcontrol, |
| 190 | struct snd_ctl_elem_value *ucontrol); |
| 191 | |
| 192 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1); |
| 193 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1); |
| 194 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); |
| 195 | static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0); |
| 196 | static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0); |
| 197 | static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0); |
| 198 | static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0); |
| 199 | static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0); |
| 200 | static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0); |
| 201 | static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1); |
| 202 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
| 203 | static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0); |
| 204 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); |
| 205 | static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0); |
| 206 | |
| 207 | static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" }; |
| 208 | static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, |
| 209 | alc_sel_text); |
| 210 | |
| 211 | static const char *alc_mode_text[] = { "ALC", "Limiter" }; |
| 212 | static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, |
| 213 | alc_mode_text); |
| 214 | |
| 215 | static const char *filter_mode_text[] = { "Audio", "Application" }; |
| 216 | static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7, |
| 217 | filter_mode_text); |
| 218 | |
| 219 | static const char *eq_bw_text[] = { "Narrow", "Wide" }; |
| 220 | static const char *eqmode_text[] = { "Capture", "Playback" }; |
| 221 | static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text); |
| 222 | |
| 223 | static const char *eq1_cutoff_text[] = { |
| 224 | "80Hz", "105Hz", "135Hz", "175Hz" |
| 225 | }; |
| 226 | static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5, |
| 227 | eq1_cutoff_text); |
| 228 | static const char *eq2_cutoff_text[] = { |
| 229 | "230Hz", "300Hz", "385Hz", "500Hz" |
| 230 | }; |
| 231 | static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text); |
| 232 | static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, |
| 233 | eq2_cutoff_text); |
| 234 | static const char *eq3_cutoff_text[] = { |
| 235 | "650Hz", "850Hz", "1.1kHz", "1.4kHz" |
| 236 | }; |
| 237 | static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text); |
| 238 | static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, |
| 239 | eq3_cutoff_text); |
| 240 | static const char *eq4_cutoff_text[] = { |
| 241 | "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" |
| 242 | }; |
| 243 | static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text); |
| 244 | static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, |
| 245 | eq4_cutoff_text); |
| 246 | static const char *eq5_cutoff_text[] = { |
| 247 | "5.3kHz", "6.9kHz", "9kHz", "11.7kHz" |
| 248 | }; |
| 249 | static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5, |
| 250 | eq5_cutoff_text); |
| 251 | |
| 252 | static const char *speaker_mode_text[] = { "Class A/B", "Class D" }; |
| 253 | static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text); |
| 254 | |
| 255 | static const char *depth_3d_text[] = { |
| 256 | "Off", |
| 257 | "6.67%", |
| 258 | "13.3%", |
| 259 | "20%", |
| 260 | "26.7%", |
| 261 | "33.3%", |
| 262 | "40%", |
| 263 | "46.6%", |
| 264 | "53.3%", |
| 265 | "60%", |
| 266 | "66.7%", |
| 267 | "73.3%", |
| 268 | "80%", |
| 269 | "86.7%", |
| 270 | "93.3%", |
| 271 | "100%" |
| 272 | }; |
| 273 | static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0, |
| 274 | depth_3d_text); |
| 275 | |
| 276 | static const struct snd_kcontrol_new wm8983_snd_controls[] = { |
| 277 | SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL, |
| 278 | 0, 1, 0), |
| 279 | |
| 280 | SOC_ENUM("ALC Capture Function", alc_sel), |
| 281 | SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1, |
| 282 | 3, 7, 0, alc_max_tlv), |
| 283 | SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1, |
| 284 | 0, 7, 0, alc_min_tlv), |
| 285 | SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2, |
| 286 | 0, 15, 0, alc_tar_tlv), |
| 287 | SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0), |
| 288 | SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0), |
| 289 | SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0), |
| 290 | SOC_ENUM("ALC Mode", alc_mode), |
| 291 | SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE, |
| 292 | 3, 1, 0), |
| 293 | SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE, |
| 294 | 0, 7, 1), |
| 295 | |
| 296 | SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL, |
| 297 | WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv), |
| 298 | SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL, |
| 299 | WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0), |
| 300 | SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL, |
| 301 | WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv), |
| 302 | |
| 303 | SOC_DOUBLE_R_TLV("Capture PGA Boost Volume", |
| 304 | WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL, |
| 305 | 8, 1, 0, pga_boost_tlv), |
| 306 | |
| 307 | SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0), |
| 308 | SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0), |
| 309 | |
| 310 | SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL, |
| 311 | WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv), |
| 312 | |
| 313 | SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0), |
| 314 | SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0), |
| 315 | SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0), |
| 316 | SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2, |
| 317 | 4, 7, 1, lim_thresh_tlv), |
| 318 | SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2, |
| 319 | 0, 12, 0, lim_boost_tlv), |
| 320 | SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0), |
| 321 | SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0), |
| 322 | SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0), |
| 323 | |
| 324 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL, |
| 325 | WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv), |
| 326 | SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL, |
| 327 | WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0), |
| 328 | SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL, |
| 329 | WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1), |
| 330 | |
| 331 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL, |
| 332 | WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv), |
| 333 | SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL, |
| 334 | WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0), |
| 335 | SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL, |
| 336 | WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1), |
| 337 | |
| 338 | SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL, |
| 339 | 6, 1, 1), |
| 340 | |
| 341 | SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, |
| 342 | 6, 1, 1), |
| 343 | |
| 344 | SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0), |
| 345 | SOC_ENUM("High Pass Filter Mode", filter_mode), |
| 346 | SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0), |
| 347 | |
| 348 | SOC_DOUBLE_R_TLV("Aux Bypass Volume", |
| 349 | WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0, |
| 350 | aux_tlv), |
| 351 | |
| 352 | SOC_DOUBLE_R_TLV("Input PGA Bypass Volume", |
| 353 | WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0, |
| 354 | bypass_tlv), |
| 355 | |
| 356 | SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put), |
| 357 | SOC_ENUM("EQ1 Cutoff", eq1_cutoff), |
| 358 | SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv), |
| 359 | SOC_ENUM("EQ2 Bandwith", eq2_bw), |
| 360 | SOC_ENUM("EQ2 Cutoff", eq2_cutoff), |
| 361 | SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv), |
| 362 | SOC_ENUM("EQ3 Bandwith", eq3_bw), |
| 363 | SOC_ENUM("EQ3 Cutoff", eq3_cutoff), |
| 364 | SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv), |
| 365 | SOC_ENUM("EQ4 Bandwith", eq4_bw), |
| 366 | SOC_ENUM("EQ4 Cutoff", eq4_cutoff), |
| 367 | SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv), |
| 368 | SOC_ENUM("EQ5 Cutoff", eq5_cutoff), |
| 369 | SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv), |
| 370 | |
| 371 | SOC_ENUM("3D Depth", depth_3d), |
| 372 | |
| 373 | SOC_ENUM("Speaker Mode", speaker_mode) |
| 374 | }; |
| 375 | |
| 376 | static const struct snd_kcontrol_new left_out_mixer[] = { |
| 377 | SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0), |
| 378 | SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0), |
| 379 | SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0), |
| 380 | }; |
| 381 | |
| 382 | static const struct snd_kcontrol_new right_out_mixer[] = { |
| 383 | SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0), |
| 384 | SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0), |
| 385 | SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0), |
| 386 | }; |
| 387 | |
| 388 | static const struct snd_kcontrol_new left_input_mixer[] = { |
| 389 | SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0), |
| 390 | SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0), |
| 391 | SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0), |
| 392 | }; |
| 393 | |
| 394 | static const struct snd_kcontrol_new right_input_mixer[] = { |
| 395 | SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0), |
| 396 | SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0), |
| 397 | SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0), |
| 398 | }; |
| 399 | |
| 400 | static const struct snd_kcontrol_new left_boost_mixer[] = { |
| 401 | SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL, |
| 402 | 4, 7, 0, boost_tlv), |
| 403 | SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL, |
| 404 | 0, 7, 0, boost_tlv) |
| 405 | }; |
| 406 | |
| 407 | static const struct snd_kcontrol_new out3_mixer[] = { |
| 408 | SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL, |
| 409 | 1, 1, 0), |
| 410 | SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL, |
| 411 | 0, 1, 0), |
| 412 | }; |
| 413 | |
| 414 | static const struct snd_kcontrol_new out4_mixer[] = { |
| 415 | SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, |
| 416 | 4, 1, 0), |
| 417 | SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, |
| 418 | 1, 1, 0), |
| 419 | SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, |
| 420 | 3, 1, 0), |
| 421 | SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, |
| 422 | 0, 1, 0), |
| 423 | }; |
| 424 | |
| 425 | static const struct snd_kcontrol_new right_boost_mixer[] = { |
| 426 | SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL, |
| 427 | 4, 7, 0, boost_tlv), |
| 428 | SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL, |
| 429 | 0, 7, 0, boost_tlv) |
| 430 | }; |
| 431 | |
| 432 | static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = { |
| 433 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3, |
| 434 | 0, 0), |
| 435 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3, |
| 436 | 1, 0), |
| 437 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2, |
| 438 | 0, 0), |
| 439 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2, |
| 440 | 1, 0), |
| 441 | |
| 442 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3, |
| 443 | 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)), |
| 444 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3, |
| 445 | 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)), |
| 446 | |
| 447 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2, |
| 448 | 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)), |
| 449 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2, |
| 450 | 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)), |
| 451 | |
| 452 | SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2, |
| 453 | 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)), |
| 454 | SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2, |
| 455 | 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)), |
| 456 | |
| 457 | SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1, |
| 458 | 6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)), |
| 459 | |
| 460 | SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1, |
| 461 | 7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)), |
| 462 | |
| 463 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL, |
| 464 | 6, 1, NULL, 0), |
| 465 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL, |
| 466 | 6, 1, NULL, 0), |
| 467 | |
| 468 | SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2, |
| 469 | 7, 0, NULL, 0), |
| 470 | SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2, |
| 471 | 8, 0, NULL, 0), |
| 472 | |
| 473 | SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3, |
| 474 | 5, 0, NULL, 0), |
| 475 | SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3, |
| 476 | 6, 0, NULL, 0), |
| 477 | |
| 478 | SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3, |
| 479 | 7, 0, NULL, 0), |
| 480 | |
| 481 | SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3, |
| 482 | 8, 0, NULL, 0), |
| 483 | |
Mark Brown | 605b151 | 2011-10-27 09:47:24 +0200 | [diff] [blame] | 484 | SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0, |
| 485 | NULL, 0), |
Dimitris Papastamos | 6b3860b | 2011-07-15 13:51:30 +0100 | [diff] [blame] | 486 | |
| 487 | SND_SOC_DAPM_INPUT("LIN"), |
| 488 | SND_SOC_DAPM_INPUT("LIP"), |
| 489 | SND_SOC_DAPM_INPUT("RIN"), |
| 490 | SND_SOC_DAPM_INPUT("RIP"), |
| 491 | SND_SOC_DAPM_INPUT("AUXL"), |
| 492 | SND_SOC_DAPM_INPUT("AUXR"), |
| 493 | SND_SOC_DAPM_INPUT("L2"), |
| 494 | SND_SOC_DAPM_INPUT("R2"), |
| 495 | SND_SOC_DAPM_OUTPUT("HPL"), |
| 496 | SND_SOC_DAPM_OUTPUT("HPR"), |
| 497 | SND_SOC_DAPM_OUTPUT("SPKL"), |
| 498 | SND_SOC_DAPM_OUTPUT("SPKR"), |
| 499 | SND_SOC_DAPM_OUTPUT("OUT3"), |
| 500 | SND_SOC_DAPM_OUTPUT("OUT4") |
| 501 | }; |
| 502 | |
| 503 | static const struct snd_soc_dapm_route wm8983_audio_map[] = { |
| 504 | { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" }, |
| 505 | { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" }, |
| 506 | |
| 507 | { "OUT3 Out", NULL, "OUT3 Mixer" }, |
| 508 | { "OUT3", NULL, "OUT3 Out" }, |
| 509 | |
| 510 | { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" }, |
| 511 | { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" }, |
| 512 | { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" }, |
| 513 | { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" }, |
| 514 | |
| 515 | { "OUT4 Out", NULL, "OUT4 Mixer" }, |
| 516 | { "OUT4", NULL, "OUT4 Out" }, |
| 517 | |
| 518 | { "Right Output Mixer", "PCM Switch", "Right DAC" }, |
| 519 | { "Right Output Mixer", "Aux Switch", "AUXR" }, |
| 520 | { "Right Output Mixer", "Line Switch", "Right Boost Mixer" }, |
| 521 | |
| 522 | { "Left Output Mixer", "PCM Switch", "Left DAC" }, |
| 523 | { "Left Output Mixer", "Aux Switch", "AUXL" }, |
| 524 | { "Left Output Mixer", "Line Switch", "Left Boost Mixer" }, |
| 525 | |
| 526 | { "Right Headphone Out", NULL, "Right Output Mixer" }, |
| 527 | { "HPR", NULL, "Right Headphone Out" }, |
| 528 | |
| 529 | { "Left Headphone Out", NULL, "Left Output Mixer" }, |
| 530 | { "HPL", NULL, "Left Headphone Out" }, |
| 531 | |
| 532 | { "Right Speaker Out", NULL, "Right Output Mixer" }, |
| 533 | { "SPKR", NULL, "Right Speaker Out" }, |
| 534 | |
| 535 | { "Left Speaker Out", NULL, "Left Output Mixer" }, |
| 536 | { "SPKL", NULL, "Left Speaker Out" }, |
| 537 | |
| 538 | { "Right ADC", NULL, "Right Boost Mixer" }, |
| 539 | |
| 540 | { "Right Boost Mixer", "AUXR Volume", "AUXR" }, |
| 541 | { "Right Boost Mixer", NULL, "Right Capture PGA" }, |
| 542 | { "Right Boost Mixer", "R2 Volume", "R2" }, |
| 543 | |
| 544 | { "Left ADC", NULL, "Left Boost Mixer" }, |
| 545 | |
| 546 | { "Left Boost Mixer", "AUXL Volume", "AUXL" }, |
| 547 | { "Left Boost Mixer", NULL, "Left Capture PGA" }, |
| 548 | { "Left Boost Mixer", "L2 Volume", "L2" }, |
| 549 | |
| 550 | { "Right Capture PGA", NULL, "Right Input Mixer" }, |
| 551 | { "Left Capture PGA", NULL, "Left Input Mixer" }, |
| 552 | |
| 553 | { "Right Input Mixer", "R2 Switch", "R2" }, |
| 554 | { "Right Input Mixer", "MicN Switch", "RIN" }, |
| 555 | { "Right Input Mixer", "MicP Switch", "RIP" }, |
| 556 | |
| 557 | { "Left Input Mixer", "L2 Switch", "L2" }, |
| 558 | { "Left Input Mixer", "MicN Switch", "LIN" }, |
| 559 | { "Left Input Mixer", "MicP Switch", "LIP" }, |
| 560 | }; |
| 561 | |
| 562 | static int eqmode_get(struct snd_kcontrol *kcontrol, |
| 563 | struct snd_ctl_elem_value *ucontrol) |
| 564 | { |
| 565 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 566 | unsigned int reg; |
| 567 | |
| 568 | reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF); |
| 569 | if (reg & WM8983_EQ3DMODE) |
| 570 | ucontrol->value.integer.value[0] = 1; |
| 571 | else |
| 572 | ucontrol->value.integer.value[0] = 0; |
| 573 | |
| 574 | return 0; |
| 575 | } |
| 576 | |
| 577 | static int eqmode_put(struct snd_kcontrol *kcontrol, |
| 578 | struct snd_ctl_elem_value *ucontrol) |
| 579 | { |
| 580 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 581 | unsigned int regpwr2, regpwr3; |
| 582 | unsigned int reg_eq; |
| 583 | |
| 584 | if (ucontrol->value.integer.value[0] != 0 |
| 585 | && ucontrol->value.integer.value[0] != 1) |
| 586 | return -EINVAL; |
| 587 | |
| 588 | reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF); |
| 589 | switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) { |
| 590 | case 0: |
| 591 | if (!ucontrol->value.integer.value[0]) |
| 592 | return 0; |
| 593 | break; |
| 594 | case 1: |
| 595 | if (ucontrol->value.integer.value[0]) |
| 596 | return 0; |
| 597 | break; |
| 598 | } |
| 599 | |
| 600 | regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2); |
| 601 | regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3); |
| 602 | /* disable the DACs and ADCs */ |
| 603 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2, |
| 604 | WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0); |
| 605 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3, |
| 606 | WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0); |
| 607 | /* set the desired eqmode */ |
| 608 | snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF, |
| 609 | WM8983_EQ3DMODE_MASK, |
| 610 | ucontrol->value.integer.value[0] |
| 611 | << WM8983_EQ3DMODE_SHIFT); |
| 612 | /* restore DAC/ADC configuration */ |
| 613 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2); |
| 614 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3); |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | static int wm8983_readable(struct snd_soc_codec *codec, unsigned int reg) |
| 619 | { |
| 620 | if (reg > WM8983_MAX_REGISTER) |
| 621 | return 0; |
| 622 | |
| 623 | return wm8983_access_masks[reg].read != 0; |
| 624 | } |
| 625 | |
| 626 | static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute) |
| 627 | { |
| 628 | struct snd_soc_codec *codec = dai->codec; |
| 629 | |
| 630 | return snd_soc_update_bits(codec, WM8983_DAC_CONTROL, |
| 631 | WM8983_SOFTMUTE_MASK, |
| 632 | !!mute << WM8983_SOFTMUTE_SHIFT); |
| 633 | } |
| 634 | |
| 635 | static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 636 | { |
| 637 | struct snd_soc_codec *codec = dai->codec; |
| 638 | u16 format, master, bcp, lrp; |
| 639 | |
| 640 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 641 | case SND_SOC_DAIFMT_I2S: |
| 642 | format = 0x2; |
| 643 | break; |
| 644 | case SND_SOC_DAIFMT_RIGHT_J: |
| 645 | format = 0x0; |
| 646 | break; |
| 647 | case SND_SOC_DAIFMT_LEFT_J: |
| 648 | format = 0x1; |
| 649 | break; |
| 650 | case SND_SOC_DAIFMT_DSP_A: |
| 651 | case SND_SOC_DAIFMT_DSP_B: |
| 652 | format = 0x3; |
| 653 | break; |
| 654 | default: |
| 655 | dev_err(dai->dev, "Unknown dai format\n"); |
| 656 | return -EINVAL; |
| 657 | } |
| 658 | |
| 659 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, |
| 660 | WM8983_FMT_MASK, format << WM8983_FMT_SHIFT); |
| 661 | |
| 662 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 663 | case SND_SOC_DAIFMT_CBM_CFM: |
| 664 | master = 1; |
| 665 | break; |
| 666 | case SND_SOC_DAIFMT_CBS_CFS: |
| 667 | master = 0; |
| 668 | break; |
| 669 | default: |
| 670 | dev_err(dai->dev, "Unknown master/slave configuration\n"); |
| 671 | return -EINVAL; |
| 672 | } |
| 673 | |
| 674 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, |
| 675 | WM8983_MS_MASK, master << WM8983_MS_SHIFT); |
| 676 | |
| 677 | /* FIXME: We don't currently support DSP A/B modes */ |
| 678 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 679 | case SND_SOC_DAIFMT_DSP_A: |
| 680 | case SND_SOC_DAIFMT_DSP_B: |
| 681 | dev_err(dai->dev, "DSP A/B modes are not supported\n"); |
| 682 | return -EINVAL; |
| 683 | default: |
| 684 | break; |
| 685 | } |
| 686 | |
| 687 | bcp = lrp = 0; |
| 688 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 689 | case SND_SOC_DAIFMT_NB_NF: |
| 690 | break; |
| 691 | case SND_SOC_DAIFMT_IB_IF: |
| 692 | bcp = lrp = 1; |
| 693 | break; |
| 694 | case SND_SOC_DAIFMT_IB_NF: |
| 695 | bcp = 1; |
| 696 | break; |
| 697 | case SND_SOC_DAIFMT_NB_IF: |
| 698 | lrp = 1; |
| 699 | break; |
| 700 | default: |
| 701 | dev_err(dai->dev, "Unknown polarity configuration\n"); |
| 702 | return -EINVAL; |
| 703 | } |
| 704 | |
| 705 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, |
| 706 | WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT); |
| 707 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, |
| 708 | WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT); |
| 709 | return 0; |
| 710 | } |
| 711 | |
| 712 | static int wm8983_hw_params(struct snd_pcm_substream *substream, |
| 713 | struct snd_pcm_hw_params *params, |
| 714 | struct snd_soc_dai *dai) |
| 715 | { |
| 716 | int i; |
| 717 | struct snd_soc_codec *codec = dai->codec; |
| 718 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); |
| 719 | u16 blen, srate_idx; |
| 720 | u32 tmp; |
| 721 | int srate_best; |
| 722 | int ret; |
| 723 | |
| 724 | ret = snd_soc_params_to_bclk(params); |
| 725 | if (ret < 0) { |
| 726 | dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret); |
| 727 | return ret; |
| 728 | } |
| 729 | |
| 730 | wm8983->bclk = ret; |
| 731 | |
| 732 | switch (params_format(params)) { |
| 733 | case SNDRV_PCM_FORMAT_S16_LE: |
| 734 | blen = 0x0; |
| 735 | break; |
| 736 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 737 | blen = 0x1; |
| 738 | break; |
| 739 | case SNDRV_PCM_FORMAT_S24_LE: |
| 740 | blen = 0x2; |
| 741 | break; |
| 742 | case SNDRV_PCM_FORMAT_S32_LE: |
| 743 | blen = 0x3; |
| 744 | break; |
| 745 | default: |
| 746 | dev_err(dai->dev, "Unsupported word length %u\n", |
| 747 | params_format(params)); |
| 748 | return -EINVAL; |
| 749 | } |
| 750 | |
| 751 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, |
| 752 | WM8983_WL_MASK, blen << WM8983_WL_SHIFT); |
| 753 | |
| 754 | /* |
| 755 | * match to the nearest possible sample rate and rely |
| 756 | * on the array index to configure the SR register |
| 757 | */ |
| 758 | srate_idx = 0; |
| 759 | srate_best = abs(srates[0] - params_rate(params)); |
| 760 | for (i = 1; i < ARRAY_SIZE(srates); ++i) { |
| 761 | if (abs(srates[i] - params_rate(params)) >= srate_best) |
| 762 | continue; |
| 763 | srate_idx = i; |
| 764 | srate_best = abs(srates[i] - params_rate(params)); |
| 765 | } |
| 766 | |
| 767 | dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]); |
| 768 | snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL, |
| 769 | WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT); |
| 770 | |
| 771 | dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk); |
| 772 | dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk); |
| 773 | |
| 774 | for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) { |
| 775 | if (wm8983->sysclk / params_rate(params) |
| 776 | == fs_ratios[i].ratio) |
| 777 | break; |
| 778 | } |
| 779 | |
| 780 | if (i == ARRAY_SIZE(fs_ratios)) { |
| 781 | dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n", |
| 782 | wm8983->sysclk, params_rate(params)); |
| 783 | return -EINVAL; |
| 784 | } |
| 785 | |
| 786 | dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio); |
| 787 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, |
| 788 | WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT); |
| 789 | |
| 790 | /* select the appropriate bclk divider */ |
| 791 | tmp = (wm8983->sysclk / fs_ratios[i].div) * 10; |
| 792 | for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) { |
| 793 | if (wm8983->bclk == tmp / bclk_divs[i]) |
| 794 | break; |
| 795 | } |
| 796 | |
| 797 | if (i == ARRAY_SIZE(bclk_divs)) { |
| 798 | dev_err(dai->dev, "No matching BCLK divider found\n"); |
| 799 | return -EINVAL; |
| 800 | } |
| 801 | |
| 802 | dev_dbg(dai->dev, "BCLK div = %d\n", i); |
| 803 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, |
| 804 | WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT); |
| 805 | |
| 806 | return 0; |
| 807 | } |
| 808 | |
| 809 | struct pll_div { |
| 810 | u32 div2:1; |
| 811 | u32 n:4; |
| 812 | u32 k:24; |
| 813 | }; |
| 814 | |
| 815 | #define FIXED_PLL_SIZE ((1ULL << 24) * 10) |
| 816 | static int pll_factors(struct pll_div *pll_div, unsigned int target, |
| 817 | unsigned int source) |
| 818 | { |
| 819 | u64 Kpart; |
| 820 | unsigned long int K, Ndiv, Nmod; |
| 821 | |
| 822 | pll_div->div2 = 0; |
| 823 | Ndiv = target / source; |
| 824 | if (Ndiv < 6) { |
| 825 | source >>= 1; |
| 826 | pll_div->div2 = 1; |
| 827 | Ndiv = target / source; |
| 828 | } |
| 829 | |
| 830 | if (Ndiv < 6 || Ndiv > 12) { |
| 831 | printk(KERN_ERR "%s: WM8983 N value is not within" |
| 832 | " the recommended range: %lu\n", __func__, Ndiv); |
| 833 | return -EINVAL; |
| 834 | } |
| 835 | pll_div->n = Ndiv; |
| 836 | |
| 837 | Nmod = target % source; |
| 838 | Kpart = FIXED_PLL_SIZE * (u64)Nmod; |
| 839 | |
| 840 | do_div(Kpart, source); |
| 841 | |
| 842 | K = Kpart & 0xffffffff; |
| 843 | if ((K % 10) >= 5) |
| 844 | K += 5; |
| 845 | K /= 10; |
| 846 | pll_div->k = K; |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id, |
| 851 | int source, unsigned int freq_in, |
| 852 | unsigned int freq_out) |
| 853 | { |
| 854 | int ret; |
| 855 | struct snd_soc_codec *codec; |
| 856 | struct pll_div pll_div; |
| 857 | |
| 858 | codec = dai->codec; |
| 859 | if (freq_in && freq_out) { |
| 860 | ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); |
| 861 | if (ret) |
| 862 | return ret; |
| 863 | } |
| 864 | |
| 865 | /* disable the PLL before re-programming it */ |
| 866 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 867 | WM8983_PLLEN_MASK, 0); |
| 868 | |
| 869 | if (!freq_in || !freq_out) |
| 870 | return 0; |
| 871 | |
| 872 | /* set PLLN and PRESCALE */ |
| 873 | snd_soc_write(codec, WM8983_PLL_N, |
| 874 | (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) |
| 875 | | pll_div.n); |
| 876 | /* set PLLK */ |
| 877 | snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff); |
| 878 | snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff); |
| 879 | snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18)); |
| 880 | /* enable the PLL */ |
| 881 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 882 | WM8983_PLLEN_MASK, WM8983_PLLEN); |
| 883 | return 0; |
| 884 | } |
| 885 | |
| 886 | static int wm8983_set_sysclk(struct snd_soc_dai *dai, |
| 887 | int clk_id, unsigned int freq, int dir) |
| 888 | { |
| 889 | struct snd_soc_codec *codec = dai->codec; |
| 890 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); |
| 891 | |
| 892 | switch (clk_id) { |
| 893 | case WM8983_CLKSRC_MCLK: |
| 894 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, |
| 895 | WM8983_CLKSEL_MASK, 0); |
| 896 | break; |
| 897 | case WM8983_CLKSRC_PLL: |
| 898 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, |
| 899 | WM8983_CLKSEL_MASK, WM8983_CLKSEL); |
| 900 | break; |
| 901 | default: |
| 902 | dev_err(dai->dev, "Unknown clock source: %d\n", clk_id); |
| 903 | return -EINVAL; |
| 904 | } |
| 905 | |
| 906 | wm8983->sysclk = freq; |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static int wm8983_set_bias_level(struct snd_soc_codec *codec, |
| 911 | enum snd_soc_bias_level level) |
| 912 | { |
| 913 | int ret; |
| 914 | |
| 915 | switch (level) { |
| 916 | case SND_SOC_BIAS_ON: |
| 917 | case SND_SOC_BIAS_PREPARE: |
| 918 | /* VMID at 100k */ |
| 919 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 920 | WM8983_VMIDSEL_MASK, |
| 921 | 1 << WM8983_VMIDSEL_SHIFT); |
| 922 | break; |
| 923 | case SND_SOC_BIAS_STANDBY: |
| 924 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
| 925 | ret = snd_soc_cache_sync(codec); |
| 926 | if (ret < 0) { |
| 927 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); |
| 928 | return ret; |
| 929 | } |
| 930 | /* enable anti-pop features */ |
| 931 | snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC, |
| 932 | WM8983_POBCTRL_MASK | WM8983_DELEN_MASK, |
| 933 | WM8983_POBCTRL | WM8983_DELEN); |
| 934 | /* enable thermal shutdown */ |
| 935 | snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL, |
| 936 | WM8983_TSDEN_MASK, WM8983_TSDEN); |
| 937 | /* enable BIASEN */ |
| 938 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 939 | WM8983_BIASEN_MASK, WM8983_BIASEN); |
| 940 | /* VMID at 100k */ |
| 941 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 942 | WM8983_VMIDSEL_MASK, |
| 943 | 1 << WM8983_VMIDSEL_SHIFT); |
| 944 | msleep(250); |
| 945 | /* disable anti-pop features */ |
| 946 | snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC, |
| 947 | WM8983_POBCTRL_MASK | |
| 948 | WM8983_DELEN_MASK, 0); |
| 949 | } |
| 950 | |
| 951 | /* VMID at 500k */ |
| 952 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 953 | WM8983_VMIDSEL_MASK, |
| 954 | 2 << WM8983_VMIDSEL_SHIFT); |
| 955 | break; |
| 956 | case SND_SOC_BIAS_OFF: |
| 957 | /* disable thermal shutdown */ |
| 958 | snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL, |
| 959 | WM8983_TSDEN_MASK, 0); |
| 960 | /* disable VMIDSEL and BIASEN */ |
| 961 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, |
| 962 | WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK, |
| 963 | 0); |
| 964 | /* wait for VMID to discharge */ |
| 965 | msleep(100); |
| 966 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0); |
| 967 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0); |
| 968 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0); |
| 969 | break; |
| 970 | } |
| 971 | |
| 972 | codec->dapm.bias_level = level; |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | #ifdef CONFIG_PM |
Lars-Peter Clausen | 84b315e | 2011-12-02 10:18:28 +0100 | [diff] [blame] | 977 | static int wm8983_suspend(struct snd_soc_codec *codec) |
Dimitris Papastamos | 6b3860b | 2011-07-15 13:51:30 +0100 | [diff] [blame] | 978 | { |
| 979 | wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int wm8983_resume(struct snd_soc_codec *codec) |
| 984 | { |
| 985 | wm8983_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 986 | return 0; |
| 987 | } |
| 988 | #else |
| 989 | #define wm8983_suspend NULL |
| 990 | #define wm8983_resume NULL |
| 991 | #endif |
| 992 | |
| 993 | static int wm8983_remove(struct snd_soc_codec *codec) |
| 994 | { |
| 995 | wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | static int wm8983_probe(struct snd_soc_codec *codec) |
| 1000 | { |
| 1001 | int ret; |
| 1002 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); |
| 1003 | int i; |
| 1004 | |
| 1005 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8983->control_type); |
| 1006 | if (ret < 0) { |
| 1007 | dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); |
| 1008 | return ret; |
| 1009 | } |
| 1010 | |
Axel Lin | 6f25e4e | 2011-10-11 17:55:00 +0800 | [diff] [blame] | 1011 | ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0); |
Dimitris Papastamos | 6b3860b | 2011-07-15 13:51:30 +0100 | [diff] [blame] | 1012 | if (ret < 0) { |
| 1013 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); |
| 1014 | return ret; |
| 1015 | } |
| 1016 | |
| 1017 | /* set the vol/gain update bits */ |
| 1018 | for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i) |
| 1019 | snd_soc_update_bits(codec, vol_update_regs[i], |
| 1020 | 0x100, 0x100); |
| 1021 | |
| 1022 | /* mute all outputs and set PGAs to minimum gain */ |
| 1023 | for (i = WM8983_LOUT1_HP_VOLUME_CTRL; |
| 1024 | i <= WM8983_OUT4_MONO_MIX_CTRL; ++i) |
| 1025 | snd_soc_update_bits(codec, i, 0x40, 0x40); |
| 1026 | |
| 1027 | /* enable soft mute */ |
| 1028 | snd_soc_update_bits(codec, WM8983_DAC_CONTROL, |
| 1029 | WM8983_SOFTMUTE_MASK, |
| 1030 | WM8983_SOFTMUTE); |
| 1031 | |
| 1032 | /* enable BIASCUT */ |
| 1033 | snd_soc_update_bits(codec, WM8983_BIAS_CTRL, |
| 1034 | WM8983_BIASCUT, WM8983_BIASCUT); |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1038 | static const struct snd_soc_dai_ops wm8983_dai_ops = { |
Dimitris Papastamos | 6b3860b | 2011-07-15 13:51:30 +0100 | [diff] [blame] | 1039 | .digital_mute = wm8983_dac_mute, |
| 1040 | .hw_params = wm8983_hw_params, |
| 1041 | .set_fmt = wm8983_set_fmt, |
| 1042 | .set_sysclk = wm8983_set_sysclk, |
| 1043 | .set_pll = wm8983_set_pll |
| 1044 | }; |
| 1045 | |
| 1046 | #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 1047 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 1048 | |
| 1049 | static struct snd_soc_dai_driver wm8983_dai = { |
| 1050 | .name = "wm8983-hifi", |
| 1051 | .playback = { |
| 1052 | .stream_name = "Playback", |
| 1053 | .channels_min = 2, |
| 1054 | .channels_max = 2, |
| 1055 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 1056 | .formats = WM8983_FORMATS, |
| 1057 | }, |
| 1058 | .capture = { |
| 1059 | .stream_name = "Capture", |
| 1060 | .channels_min = 2, |
| 1061 | .channels_max = 2, |
| 1062 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 1063 | .formats = WM8983_FORMATS, |
| 1064 | }, |
| 1065 | .ops = &wm8983_dai_ops, |
| 1066 | .symmetric_rates = 1 |
| 1067 | }; |
| 1068 | |
| 1069 | static struct snd_soc_codec_driver soc_codec_dev_wm8983 = { |
| 1070 | .probe = wm8983_probe, |
| 1071 | .remove = wm8983_remove, |
| 1072 | .suspend = wm8983_suspend, |
| 1073 | .resume = wm8983_resume, |
| 1074 | .set_bias_level = wm8983_set_bias_level, |
| 1075 | .reg_cache_size = ARRAY_SIZE(wm8983_reg_defs), |
| 1076 | .reg_word_size = sizeof(u16), |
| 1077 | .reg_cache_default = wm8983_reg_defs, |
| 1078 | .controls = wm8983_snd_controls, |
| 1079 | .num_controls = ARRAY_SIZE(wm8983_snd_controls), |
| 1080 | .dapm_widgets = wm8983_dapm_widgets, |
| 1081 | .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets), |
| 1082 | .dapm_routes = wm8983_audio_map, |
| 1083 | .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map), |
| 1084 | .readable_register = wm8983_readable |
| 1085 | }; |
| 1086 | |
| 1087 | #if defined(CONFIG_SPI_MASTER) |
| 1088 | static int __devinit wm8983_spi_probe(struct spi_device *spi) |
| 1089 | { |
| 1090 | struct wm8983_priv *wm8983; |
| 1091 | int ret; |
| 1092 | |
| 1093 | wm8983 = kzalloc(sizeof *wm8983, GFP_KERNEL); |
| 1094 | if (!wm8983) |
| 1095 | return -ENOMEM; |
| 1096 | |
| 1097 | wm8983->control_type = SND_SOC_SPI; |
| 1098 | spi_set_drvdata(spi, wm8983); |
| 1099 | |
| 1100 | ret = snd_soc_register_codec(&spi->dev, |
| 1101 | &soc_codec_dev_wm8983, &wm8983_dai, 1); |
| 1102 | if (ret < 0) |
| 1103 | kfree(wm8983); |
| 1104 | return ret; |
| 1105 | } |
| 1106 | |
| 1107 | static int __devexit wm8983_spi_remove(struct spi_device *spi) |
| 1108 | { |
| 1109 | snd_soc_unregister_codec(&spi->dev); |
| 1110 | kfree(spi_get_drvdata(spi)); |
| 1111 | return 0; |
| 1112 | } |
| 1113 | |
| 1114 | static struct spi_driver wm8983_spi_driver = { |
| 1115 | .driver = { |
| 1116 | .name = "wm8983", |
| 1117 | .owner = THIS_MODULE, |
| 1118 | }, |
| 1119 | .probe = wm8983_spi_probe, |
| 1120 | .remove = __devexit_p(wm8983_spi_remove) |
| 1121 | }; |
| 1122 | #endif |
| 1123 | |
| 1124 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1125 | static __devinit int wm8983_i2c_probe(struct i2c_client *i2c, |
| 1126 | const struct i2c_device_id *id) |
| 1127 | { |
| 1128 | struct wm8983_priv *wm8983; |
| 1129 | int ret; |
| 1130 | |
| 1131 | wm8983 = kzalloc(sizeof *wm8983, GFP_KERNEL); |
| 1132 | if (!wm8983) |
| 1133 | return -ENOMEM; |
| 1134 | |
| 1135 | wm8983->control_type = SND_SOC_I2C; |
| 1136 | i2c_set_clientdata(i2c, wm8983); |
| 1137 | |
| 1138 | ret = snd_soc_register_codec(&i2c->dev, |
| 1139 | &soc_codec_dev_wm8983, &wm8983_dai, 1); |
| 1140 | if (ret < 0) |
| 1141 | kfree(wm8983); |
| 1142 | return ret; |
| 1143 | } |
| 1144 | |
| 1145 | static __devexit int wm8983_i2c_remove(struct i2c_client *client) |
| 1146 | { |
| 1147 | snd_soc_unregister_codec(&client->dev); |
| 1148 | kfree(i2c_get_clientdata(client)); |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | static const struct i2c_device_id wm8983_i2c_id[] = { |
| 1153 | { "wm8983", 0 }, |
| 1154 | { } |
| 1155 | }; |
| 1156 | MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id); |
| 1157 | |
| 1158 | static struct i2c_driver wm8983_i2c_driver = { |
| 1159 | .driver = { |
| 1160 | .name = "wm8983", |
| 1161 | .owner = THIS_MODULE, |
| 1162 | }, |
| 1163 | .probe = wm8983_i2c_probe, |
| 1164 | .remove = __devexit_p(wm8983_i2c_remove), |
| 1165 | .id_table = wm8983_i2c_id |
| 1166 | }; |
| 1167 | #endif |
| 1168 | |
| 1169 | static int __init wm8983_modinit(void) |
| 1170 | { |
| 1171 | int ret = 0; |
| 1172 | |
| 1173 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1174 | ret = i2c_add_driver(&wm8983_i2c_driver); |
| 1175 | if (ret) { |
| 1176 | printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n", |
| 1177 | ret); |
| 1178 | } |
| 1179 | #endif |
| 1180 | #if defined(CONFIG_SPI_MASTER) |
| 1181 | ret = spi_register_driver(&wm8983_spi_driver); |
| 1182 | if (ret != 0) { |
| 1183 | printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n", |
| 1184 | ret); |
| 1185 | } |
| 1186 | #endif |
| 1187 | return ret; |
| 1188 | } |
| 1189 | module_init(wm8983_modinit); |
| 1190 | |
| 1191 | static void __exit wm8983_exit(void) |
| 1192 | { |
| 1193 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1194 | i2c_del_driver(&wm8983_i2c_driver); |
| 1195 | #endif |
| 1196 | #if defined(CONFIG_SPI_MASTER) |
| 1197 | spi_unregister_driver(&wm8983_spi_driver); |
| 1198 | #endif |
| 1199 | } |
| 1200 | module_exit(wm8983_exit); |
| 1201 | |
| 1202 | MODULE_DESCRIPTION("ASoC WM8983 driver"); |
| 1203 | MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); |
| 1204 | MODULE_LICENSE("GPL"); |