blob: 1bfb09198ce378ce4a45bc300fad743ed0cfe4bf [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
10 */
11#include <linux/config.h>
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15
16#include <asm/cpu.h>
17#include <asm/bootinfo.h>
18#include <asm/mmu_context.h>
19#include <asm/pgtable.h>
20#include <asm/system.h>
21
22extern void build_tlb_refill_handler(void);
23
24#define TFP_TLB_SIZE 384
25#define TFP_TLB_SET_SHIFT 7
26
27/* CP0 hazard avoidance. */
28#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
29 "nop; nop; nop; nop; nop; nop;\n\t" \
30 ".set reorder\n\t")
31
32void local_flush_tlb_all(void)
33{
34 unsigned long flags;
35 unsigned long old_ctx;
36 int entry;
37
38 local_irq_save(flags);
39 /* Save old context and create impossible VPN2 value */
40 old_ctx = read_c0_entryhi();
41 write_c0_entrylo(0);
42
43 for (entry = 0; entry < TFP_TLB_SIZE; entry++) {
44 write_c0_tlbset(entry >> TFP_TLB_SET_SHIFT);
45 write_c0_vaddr(entry << PAGE_SHIFT);
46 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
47 mtc0_tlbw_hazard();
48 tlb_write();
49 }
50 tlbw_use_hazard();
51 write_c0_entryhi(old_ctx);
52 local_irq_restore(flags);
53}
54
55void local_flush_tlb_mm(struct mm_struct *mm)
56{
57 int cpu = smp_processor_id();
58
59 if (cpu_context(cpu, mm) != 0)
60 drop_mmu_context(mm,cpu);
61}
62
63void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
64 unsigned long end)
65{
66 struct mm_struct *mm = vma->vm_mm;
67 int cpu = smp_processor_id();
68 unsigned long flags;
69 int oldpid, newpid, size;
70
71 if (!cpu_context(cpu, mm))
72 return;
73
74 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
75 size = (size + 1) >> 1;
76
77 local_irq_save(flags);
78
79 if (size > TFP_TLB_SIZE / 2) {
80 drop_mmu_context(mm, cpu);
81 goto out_restore;
82 }
83
84 oldpid = read_c0_entryhi();
85 newpid = cpu_asid(cpu, mm);
86
87 write_c0_entrylo(0);
88
89 start &= PAGE_MASK;
90 end += (PAGE_SIZE - 1);
91 end &= PAGE_MASK;
92 while (start < end) {
93 signed long idx;
94
95 write_c0_vaddr(start);
96 write_c0_entryhi(start);
97 start += PAGE_SIZE;
98 tlb_probe();
99 idx = read_c0_tlbset();
100 if (idx < 0)
101 continue;
102
103 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
104 tlb_write();
105 }
106 write_c0_entryhi(oldpid);
107
108out_restore:
109 local_irq_restore(flags);
110}
111
112/* Usable for KV1 addresses only! */
113void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
114{
115 unsigned long flags;
116 int size;
117
118 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
119 size = (size + 1) >> 1;
120
121 if (size > TFP_TLB_SIZE / 2) {
122 local_flush_tlb_all();
123 return;
124 }
125
126 local_irq_save(flags);
127
128 write_c0_entrylo(0);
129
130 start &= PAGE_MASK;
131 end += (PAGE_SIZE - 1);
132 end &= PAGE_MASK;
133 while (start < end) {
134 signed long idx;
135
136 write_c0_vaddr(start);
137 write_c0_entryhi(start);
138 start += PAGE_SIZE;
139 tlb_probe();
140 idx = read_c0_tlbset();
141 if (idx < 0)
142 continue;
143
144 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
145 tlb_write();
146 }
147
148 local_irq_restore(flags);
149}
150
151void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
152{
153 int cpu = smp_processor_id();
154 unsigned long flags;
155 int oldpid, newpid;
156 signed long idx;
157
158 if (!cpu_context(cpu, vma->vm_mm))
159 return;
160
161 newpid = cpu_asid(cpu, vma->vm_mm);
162 page &= PAGE_MASK;
163 local_irq_save(flags);
164 oldpid = read_c0_entryhi();
165 write_c0_vaddr(page);
166 write_c0_entryhi(newpid);
167 tlb_probe();
168 idx = read_c0_tlbset();
169 if (idx < 0)
170 goto finish;
171
172 write_c0_entrylo(0);
173 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
174 tlb_write();
175
176finish:
177 write_c0_entryhi(oldpid);
178 local_irq_restore(flags);
179}
180
181/*
182 * We will need multiple versions of update_mmu_cache(), one that just
183 * updates the TLB with the new pte(s), and another which also checks
184 * for the R4k "end of page" hardware bug and does the needy.
185 */
186void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
187{
188 unsigned long flags;
189 pgd_t *pgdp;
190 pmd_t *pmdp;
191 pte_t *ptep;
192 int pid;
193
194 /*
195 * Handle debugger faulting in for debugee.
196 */
197 if (current->active_mm != vma->vm_mm)
198 return;
199
200 pid = read_c0_entryhi() & ASID_MASK;
201
202 local_irq_save(flags);
203 address &= PAGE_MASK;
204 write_c0_vaddr(address);
205 write_c0_entryhi(pid);
206 pgdp = pgd_offset(vma->vm_mm, address);
207 pmdp = pmd_offset(pgdp, address);
208 ptep = pte_offset_map(pmdp, address);
209 tlb_probe();
210
211 write_c0_entrylo(pte_val(*ptep++) >> 6);
212 tlb_write();
213
214 write_c0_entryhi(pid);
215 local_irq_restore(flags);
216}
217
218static void __init probe_tlb(unsigned long config)
219{
220 struct cpuinfo_mips *c = &current_cpu_data;
221
222 c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
223}
224
225void __init tlb_init(void)
226{
227 unsigned int config = read_c0_config();
228 unsigned long status;
229
230 probe_tlb(config);
231
232 status = read_c0_status();
233 status &= ~(ST0_UPS | ST0_KPS);
234#ifdef CONFIG_PAGE_SIZE_4KB
235 status |= (TFP_PAGESIZE_4K << 32) | (TFP_PAGESIZE_4K << 36);
236#elif defined(CONFIG_PAGE_SIZE_8KB)
237 status |= (TFP_PAGESIZE_8K << 32) | (TFP_PAGESIZE_8K << 36);
238#elif defined(CONFIG_PAGE_SIZE_16KB)
239 status |= (TFP_PAGESIZE_16K << 32) | (TFP_PAGESIZE_16K << 36);
240#elif defined(CONFIG_PAGE_SIZE_64KB)
241 status |= (TFP_PAGESIZE_64K << 32) | (TFP_PAGESIZE_64K << 36);
242#endif
243 write_c0_status(status);
244
245 write_c0_wired(0);
246
247 local_flush_tlb_all();
248
249 build_tlb_refill_handler();
250}