Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* $Id: he.h,v 1.4 2003/05/06 22:48:00 chas Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | |
| 5 | he.h |
| 6 | |
| 7 | ForeRunnerHE ATM Adapter driver for ATM on Linux |
| 8 | Copyright (C) 1999-2001 Naval Research Laboratory |
| 9 | |
| 10 | This library is free software; you can redistribute it and/or |
| 11 | modify it under the terms of the GNU Lesser General Public |
| 12 | License as published by the Free Software Foundation; either |
| 13 | version 2.1 of the License, or (at your option) any later version. |
| 14 | |
| 15 | This library is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | Lesser General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU Lesser General Public |
| 21 | License along with this library; if not, write to the Free Software |
| 22 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | |
| 24 | */ |
| 25 | |
| 26 | /* |
| 27 | |
| 28 | he.h |
| 29 | |
| 30 | ForeRunnerHE ATM Adapter driver for ATM on Linux |
| 31 | Copyright (C) 1999-2000 Naval Research Laboratory |
| 32 | |
| 33 | Permission to use, copy, modify and distribute this software and its |
| 34 | documentation is hereby granted, provided that both the copyright |
| 35 | notice and this permission notice appear in all copies of the software, |
| 36 | derivative works or modified versions, and any portions thereof, and |
| 37 | that both notices appear in supporting documentation. |
| 38 | |
| 39 | NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND |
| 40 | DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER |
| 41 | RESULTING FROM THE USE OF THIS SOFTWARE. |
| 42 | |
| 43 | */ |
| 44 | |
| 45 | #ifndef _HE_H_ |
| 46 | #define _HE_H_ |
| 47 | |
| 48 | #define DEV_LABEL "he" |
| 49 | |
| 50 | #define CONFIG_DEFAULT_VCIBITS 12 |
| 51 | #define CONFIG_DEFAULT_VPIBITS 0 |
| 52 | |
| 53 | #define CONFIG_IRQ_SIZE 128 |
| 54 | #define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2) |
| 55 | |
| 56 | #define CONFIG_NUMTPDS 256 |
| 57 | |
| 58 | #define CONFIG_TPDRQ_SIZE 512 |
| 59 | #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) |
| 60 | |
| 61 | #define CONFIG_RBRQ_SIZE 512 |
| 62 | #define CONFIG_RBRQ_THRESH 400 |
| 63 | #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) |
| 64 | |
| 65 | #define CONFIG_TBRQ_SIZE 512 |
| 66 | #define CONFIG_TBRQ_THRESH 400 |
| 67 | #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) |
| 68 | |
| 69 | #define CONFIG_RBPL_SIZE 512 |
| 70 | #define CONFIG_RBPL_THRESH 64 |
| 71 | #define CONFIG_RBPL_BUFSIZE 4096 |
| 72 | #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) |
| 73 | |
| 74 | #define CONFIG_RBPS_SIZE 1024 |
| 75 | #define CONFIG_RBPS_THRESH 64 |
| 76 | #define CONFIG_RBPS_BUFSIZE 128 |
| 77 | #define RBPS_MASK(x) (((unsigned long)(x))&((CONFIG_RBPS_SIZE<<3)-1)) |
| 78 | |
| 79 | /* 5.1.3 initialize connection memory */ |
| 80 | |
| 81 | #define CONFIG_RSRA 0x00000 |
| 82 | #define CONFIG_RCMLBM 0x08000 |
| 83 | #define CONFIG_RCMABR 0x0d800 |
| 84 | #define CONFIG_RSRB 0x0e000 |
| 85 | |
| 86 | #define CONFIG_TSRA 0x00000 |
| 87 | #define CONFIG_TSRB 0x08000 |
| 88 | #define CONFIG_TSRC 0x0c000 |
| 89 | #define CONFIG_TSRD 0x0e000 |
| 90 | #define CONFIG_TMABR 0x0f000 |
| 91 | #define CONFIG_TPDBA 0x10000 |
| 92 | |
| 93 | #define HE_MAXCIDBITS 12 |
| 94 | |
| 95 | /* 2.9.3.3 interrupt encodings */ |
| 96 | |
| 97 | struct he_irq { |
| 98 | volatile u32 isw; |
| 99 | }; |
| 100 | |
| 101 | #define IRQ_ALIGNMENT 0x1000 |
| 102 | |
| 103 | #define NEXT_ENTRY(base, tail, mask) \ |
| 104 | (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) |
| 105 | |
| 106 | #define ITYPE_INVALID 0xffffffff |
| 107 | #define ITYPE_TBRQ_THRESH (0<<3) |
| 108 | #define ITYPE_TPD_COMPLETE (1<<3) |
| 109 | #define ITYPE_RBPS_THRESH (2<<3) |
| 110 | #define ITYPE_RBPL_THRESH (3<<3) |
| 111 | #define ITYPE_RBRQ_THRESH (4<<3) |
| 112 | #define ITYPE_RBRQ_TIMER (5<<3) |
| 113 | #define ITYPE_PHY (6<<3) |
| 114 | #define ITYPE_OTHER 0x80 |
| 115 | #define ITYPE_PARITY 0x81 |
| 116 | #define ITYPE_ABORT 0x82 |
| 117 | |
| 118 | #define ITYPE_GROUP(x) (x & 0x7) |
| 119 | #define ITYPE_TYPE(x) (x & 0xf8) |
| 120 | |
| 121 | #define HE_NUM_GROUPS 8 |
| 122 | |
| 123 | /* 2.1.4 transmit packet descriptor */ |
| 124 | |
| 125 | struct he_tpd { |
| 126 | |
| 127 | /* read by the adapter */ |
| 128 | |
| 129 | volatile u32 status; |
| 130 | volatile u32 reserved; |
| 131 | |
| 132 | #define TPD_MAXIOV 3 |
| 133 | struct { |
| 134 | u32 addr, len; |
| 135 | } iovec[TPD_MAXIOV]; |
| 136 | |
| 137 | #define address0 iovec[0].addr |
| 138 | #define length0 iovec[0].len |
| 139 | |
| 140 | /* linux-atm extensions */ |
| 141 | |
| 142 | struct sk_buff *skb; |
| 143 | struct atm_vcc *vcc; |
| 144 | |
| 145 | #ifdef USE_TPD_POOL |
| 146 | struct list_head entry; |
| 147 | #else |
| 148 | u32 inuse; |
| 149 | char padding[32 - sizeof(u32) - (2*sizeof(void*))]; |
| 150 | #endif |
| 151 | }; |
| 152 | |
| 153 | #define TPD_ALIGNMENT 64 |
| 154 | #define TPD_LEN_MASK 0xffff |
| 155 | |
| 156 | #define TPD_ADDR_SHIFT 6 |
| 157 | #define TPD_MASK 0xffffffc0 |
| 158 | #define TPD_ADDR(x) ((x) & TPD_MASK) |
| 159 | #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) |
| 160 | |
| 161 | |
| 162 | /* table 2.3 transmit buffer return elements */ |
| 163 | |
| 164 | struct he_tbrq { |
| 165 | volatile u32 tbre; |
| 166 | }; |
| 167 | |
| 168 | #define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE |
| 169 | |
| 170 | #define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0) |
| 171 | #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3)) |
| 172 | #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1)) |
| 173 | |
| 174 | /* table 2.21 receive buffer return queue element field organization */ |
| 175 | |
| 176 | struct he_rbrq { |
| 177 | volatile u32 addr; |
| 178 | volatile u32 cidlen; |
| 179 | }; |
| 180 | |
| 181 | #define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE |
| 182 | |
| 183 | #define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0) |
| 184 | #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5)) |
| 185 | #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4)) |
| 186 | #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3)) |
| 187 | #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2)) |
| 188 | #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1)) |
| 189 | #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1) |
| 190 | #define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff) |
| 191 | #define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff) |
| 192 | |
| 193 | /* figure 2.3 transmit packet descriptor ready queue */ |
| 194 | |
| 195 | struct he_tpdrq { |
| 196 | volatile u32 tpd; |
| 197 | volatile u32 cid; |
| 198 | }; |
| 199 | |
| 200 | #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE |
| 201 | |
| 202 | /* table 2.30 host status page detail */ |
| 203 | |
| 204 | #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */ |
| 205 | |
| 206 | struct he_hsp { |
| 207 | struct he_hsp_entry { |
| 208 | volatile u32 tbrq_tail; |
| 209 | volatile u32 reserved1[15]; |
| 210 | volatile u32 rbrq_tail; |
| 211 | volatile u32 reserved2[15]; |
| 212 | } group[HE_NUM_GROUPS]; |
| 213 | }; |
| 214 | |
| 215 | /* figure 2.9 receive buffer pools */ |
| 216 | |
| 217 | struct he_rbp { |
| 218 | volatile u32 phys; |
| 219 | volatile u32 status; |
| 220 | }; |
| 221 | |
| 222 | /* NOTE: it is suggested that virt be the virtual address of the host |
| 223 | buffer. on a 64-bit machine, this would not work. Instead, we |
| 224 | store the real virtual address in another list, and store an index |
| 225 | (and buffer status) in the virt member. |
| 226 | */ |
| 227 | |
| 228 | #define RBP_INDEX_OFF 6 |
| 229 | #define RBP_INDEX(x) (((long)(x) >> RBP_INDEX_OFF) & 0xffff) |
| 230 | #define RBP_LOANED 0x80000000 |
| 231 | #define RBP_SMALLBUF 0x40000000 |
| 232 | |
| 233 | struct he_virt { |
| 234 | void *virt; |
| 235 | }; |
| 236 | |
| 237 | #define RBPL_ALIGNMENT CONFIG_RBPL_SIZE |
| 238 | #define RBPS_ALIGNMENT CONFIG_RBPS_SIZE |
| 239 | |
| 240 | #ifdef notyet |
| 241 | struct he_group { |
| 242 | u32 rpbs_size, rpbs_qsize; |
| 243 | struct he_rbp rbps_ba; |
| 244 | |
| 245 | u32 rpbl_size, rpbl_qsize; |
| 246 | struct he_rpb_entry *rbpl_ba; |
| 247 | }; |
| 248 | #endif |
| 249 | |
| 250 | #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc) |
| 251 | |
| 252 | struct he_vcc_table |
| 253 | { |
| 254 | struct atm_vcc *vcc; |
| 255 | }; |
| 256 | |
| 257 | struct he_cs_stper |
| 258 | { |
| 259 | long pcr; |
| 260 | int inuse; |
| 261 | }; |
| 262 | |
| 263 | #define HE_NUM_CS_STPER 16 |
| 264 | |
| 265 | struct he_dev { |
| 266 | unsigned int number; |
| 267 | unsigned int irq; |
| 268 | void __iomem *membase; |
| 269 | |
| 270 | char prod_id[30]; |
| 271 | char mac_addr[6]; |
| 272 | int media; /* |
| 273 | * 0x26 = HE155 MM |
| 274 | * 0x27 = HE622 MM |
| 275 | * 0x46 = HE155 SM |
| 276 | * 0x47 = HE622 SM |
| 277 | */ |
| 278 | |
| 279 | |
| 280 | unsigned int vcibits, vpibits; |
| 281 | unsigned int cells_per_row; |
| 282 | unsigned int bytes_per_row; |
| 283 | unsigned int cells_per_lbuf; |
| 284 | unsigned int r0_numrows, r0_startrow, r0_numbuffs; |
| 285 | unsigned int r1_numrows, r1_startrow, r1_numbuffs; |
| 286 | unsigned int tx_numrows, tx_startrow, tx_numbuffs; |
| 287 | unsigned int buffer_limit; |
| 288 | |
| 289 | struct he_vcc_table *he_vcc_table; |
| 290 | |
| 291 | #ifdef notyet |
| 292 | struct he_group group[HE_NUM_GROUPS]; |
| 293 | #endif |
| 294 | struct he_cs_stper cs_stper[HE_NUM_CS_STPER]; |
| 295 | unsigned total_bw; |
| 296 | |
| 297 | dma_addr_t irq_phys; |
| 298 | struct he_irq *irq_base, *irq_head, *irq_tail; |
| 299 | volatile unsigned *irq_tailoffset; |
| 300 | int irq_peak; |
| 301 | |
| 302 | #ifdef USE_TASKLET |
| 303 | struct tasklet_struct tasklet; |
| 304 | #endif |
| 305 | #ifdef USE_TPD_POOL |
| 306 | struct pci_pool *tpd_pool; |
| 307 | struct list_head outstanding_tpds; |
| 308 | #else |
| 309 | struct he_tpd *tpd_head, *tpd_base, *tpd_end; |
| 310 | dma_addr_t tpd_base_phys; |
| 311 | #endif |
| 312 | |
| 313 | dma_addr_t tpdrq_phys; |
| 314 | struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head; |
| 315 | |
| 316 | spinlock_t global_lock; /* 8.1.5 pci transaction ordering |
| 317 | error problem */ |
| 318 | dma_addr_t rbrq_phys; |
| 319 | struct he_rbrq *rbrq_base, *rbrq_head; |
| 320 | int rbrq_peak; |
| 321 | |
| 322 | #ifdef USE_RBPL_POOL |
| 323 | struct pci_pool *rbpl_pool; |
| 324 | #else |
| 325 | void *rbpl_pages; |
| 326 | dma_addr_t rbpl_pages_phys; |
| 327 | #endif |
| 328 | dma_addr_t rbpl_phys; |
| 329 | struct he_rbp *rbpl_base, *rbpl_tail; |
| 330 | struct he_virt *rbpl_virt; |
| 331 | int rbpl_peak; |
| 332 | |
| 333 | #ifdef USE_RBPS |
| 334 | #ifdef USE_RBPS_POOL |
| 335 | struct pci_pool *rbps_pool; |
| 336 | #else |
| 337 | void *rbps_pages; |
| 338 | dma_addr_t rbps_pages_phys; |
| 339 | #endif |
| 340 | #endif |
| 341 | dma_addr_t rbps_phys; |
| 342 | struct he_rbp *rbps_base, *rbps_tail; |
| 343 | struct he_virt *rbps_virt; |
| 344 | int rbps_peak; |
| 345 | |
| 346 | dma_addr_t tbrq_phys; |
| 347 | struct he_tbrq *tbrq_base, *tbrq_head; |
| 348 | int tbrq_peak; |
| 349 | |
| 350 | dma_addr_t hsp_phys; |
| 351 | struct he_hsp *hsp; |
| 352 | |
| 353 | struct pci_dev *pci_dev; |
| 354 | struct atm_dev *atm_dev; |
| 355 | struct he_dev *next; |
| 356 | }; |
| 357 | |
| 358 | struct he_iovec |
| 359 | { |
| 360 | u32 iov_base; |
| 361 | u32 iov_len; |
| 362 | }; |
| 363 | |
| 364 | #define HE_MAXIOV 20 |
| 365 | |
| 366 | struct he_vcc |
| 367 | { |
| 368 | struct he_iovec iov_head[HE_MAXIOV]; |
| 369 | struct he_iovec *iov_tail; |
| 370 | int pdu_len; |
| 371 | |
| 372 | int rc_index; |
| 373 | |
| 374 | wait_queue_head_t rx_waitq; |
| 375 | wait_queue_head_t tx_waitq; |
| 376 | }; |
| 377 | |
| 378 | #define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data)) |
| 379 | |
| 380 | #define PCI_VENDOR_ID_FORE 0x1127 |
| 381 | #define PCI_DEVICE_ID_FORE_HE 0x400 |
| 382 | |
| 383 | #define HE_DMA_MASK 0xffffffff |
| 384 | |
| 385 | #define GEN_CNTL_0 0x40 |
| 386 | #define INT_PROC_ENBL (1<<25) |
| 387 | #define SLAVE_ENDIAN_MODE (1<<16) |
| 388 | #define MRL_ENB (1<<5) |
| 389 | #define MRM_ENB (1<<4) |
| 390 | #define INIT_ENB (1<<2) |
| 391 | #define IGNORE_TIMEOUT (1<<1) |
| 392 | #define ENBL_64 (1<<0) |
| 393 | |
| 394 | #define MIN_PCI_LATENCY 32 /* errata 8.1.3 */ |
| 395 | |
| 396 | #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data) |
| 397 | |
| 398 | #define he_is622(dev) ((dev)->media & 0x1) |
| 399 | |
| 400 | #define HE_REGMAP_SIZE 0x100000 |
| 401 | |
| 402 | #define RESET_CNTL 0x80000 |
| 403 | #define BOARD_RST_STATUS (1<<6) |
| 404 | |
| 405 | #define HOST_CNTL 0x80004 |
| 406 | #define PCI_BUS_SIZE64 (1<<27) |
| 407 | #define DESC_RD_STATIC_64 (1<<26) |
| 408 | #define DATA_RD_STATIC_64 (1<<25) |
| 409 | #define DATA_WR_STATIC_64 (1<<24) |
| 410 | #define ID_CS (1<<12) |
| 411 | #define ID_WREN (1<<11) |
| 412 | #define ID_DOUT (1<<10) |
| 413 | #define ID_DOFFSET 10 |
| 414 | #define ID_DIN (1<<9) |
| 415 | #define ID_CLOCK (1<<8) |
| 416 | #define QUICK_RD_RETRY (1<<7) |
| 417 | #define QUICK_WR_RETRY (1<<6) |
| 418 | #define OUTFF_ENB (1<<5) |
| 419 | #define CMDFF_ENB (1<<4) |
| 420 | #define PERR_INT_ENB (1<<2) |
| 421 | #define IGNORE_INTR (1<<0) |
| 422 | |
| 423 | #define LB_SWAP 0x80008 |
| 424 | #define SWAP_RNUM_MAX(x) (x<<27) |
| 425 | #define DATA_WR_SWAP (1<<20) |
| 426 | #define DESC_RD_SWAP (1<<19) |
| 427 | #define DATA_RD_SWAP (1<<18) |
| 428 | #define INTR_SWAP (1<<17) |
| 429 | #define DESC_WR_SWAP (1<<16) |
| 430 | #define SDRAM_INIT (1<<15) |
| 431 | #define BIG_ENDIAN_HOST (1<<14) |
| 432 | #define XFER_SIZE (1<<7) |
| 433 | |
| 434 | #define LB_MEM_ADDR 0x8000c |
| 435 | #define LB_MEM_DATA 0x80010 |
| 436 | |
| 437 | #define LB_MEM_ACCESS 0x80014 |
| 438 | #define LB_MEM_HNDSHK (1<<30) |
| 439 | #define LM_MEM_WRITE (0x7) |
| 440 | #define LM_MEM_READ (0x3) |
| 441 | |
| 442 | #define SDRAM_CTL 0x80018 |
| 443 | #define LB_64_ENB (1<<3) |
| 444 | #define LB_TWR (1<<2) |
| 445 | #define LB_TRP (1<<1) |
| 446 | #define LB_TRAS (1<<0) |
| 447 | |
| 448 | #define INT_FIFO 0x8001c |
| 449 | #define INT_MASK_D (1<<15) |
| 450 | #define INT_MASK_C (1<<14) |
| 451 | #define INT_MASK_B (1<<13) |
| 452 | #define INT_MASK_A (1<<12) |
| 453 | #define INT_CLEAR_D (1<<11) |
| 454 | #define INT_CLEAR_C (1<<10) |
| 455 | #define INT_CLEAR_B (1<<9) |
| 456 | #define INT_CLEAR_A (1<<8) |
| 457 | |
| 458 | #define ABORT_ADDR 0x80020 |
| 459 | |
| 460 | #define IRQ0_BASE 0x80080 |
| 461 | #define IRQ_BASE(x) (x<<12) |
| 462 | #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */ |
| 463 | #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK) |
| 464 | #define IRQ0_HEAD 0x80084 |
| 465 | #define IRQ_SIZE(x) (x<<22) |
| 466 | #define IRQ_THRESH(x) (x<<12) |
| 467 | #define IRQ_HEAD(x) (x<<2) |
| 468 | /* #define IRQ_PENDING (1) conflict with linux/irq.h */ |
| 469 | #define IRQ0_CNTL 0x80088 |
| 470 | #define IRQ_ADDRSEL(x) (x<<2) |
| 471 | #define IRQ_INT_A (0<<2) |
| 472 | #define IRQ_INT_B (1<<2) |
| 473 | #define IRQ_INT_C (2<<2) |
| 474 | #define IRQ_INT_D (3<<2) |
| 475 | #define IRQ_TYPE_ADDR 0x1 |
| 476 | #define IRQ_TYPE_LINE 0x0 |
| 477 | #define IRQ0_DATA 0x8008c |
| 478 | |
| 479 | #define IRQ1_BASE 0x80090 |
| 480 | #define IRQ1_HEAD 0x80094 |
| 481 | #define IRQ1_CNTL 0x80098 |
| 482 | #define IRQ1_DATA 0x8009c |
| 483 | |
| 484 | #define IRQ2_BASE 0x800a0 |
| 485 | #define IRQ2_HEAD 0x800a4 |
| 486 | #define IRQ2_CNTL 0x800a8 |
| 487 | #define IRQ2_DATA 0x800ac |
| 488 | |
| 489 | #define IRQ3_BASE 0x800b0 |
| 490 | #define IRQ3_HEAD 0x800b4 |
| 491 | #define IRQ3_CNTL 0x800b8 |
| 492 | #define IRQ3_DATA 0x800bc |
| 493 | |
| 494 | #define GRP_10_MAP 0x800c0 |
| 495 | #define GRP_32_MAP 0x800c4 |
| 496 | #define GRP_54_MAP 0x800c8 |
| 497 | #define GRP_76_MAP 0x800cc |
| 498 | |
| 499 | #define G0_RBPS_S 0x80400 |
| 500 | #define G0_RBPS_T 0x80404 |
| 501 | #define RBP_TAIL(x) ((x)<<3) |
| 502 | #define RBP_MASK(x) ((x)|0x1fff) |
| 503 | #define G0_RBPS_QI 0x80408 |
| 504 | #define RBP_QSIZE(x) ((x)<<14) |
| 505 | #define RBP_INT_ENB (1<<13) |
| 506 | #define RBP_THRESH(x) (x) |
| 507 | #define G0_RBPS_BS 0x8040c |
| 508 | #define G0_RBPL_S 0x80410 |
| 509 | #define G0_RBPL_T 0x80414 |
| 510 | #define G0_RBPL_QI 0x80418 |
| 511 | #define G0_RBPL_BS 0x8041c |
| 512 | |
| 513 | #define G1_RBPS_S 0x80420 |
| 514 | #define G1_RBPS_T 0x80424 |
| 515 | #define G1_RBPS_QI 0x80428 |
| 516 | #define G1_RBPS_BS 0x8042c |
| 517 | #define G1_RBPL_S 0x80430 |
| 518 | #define G1_RBPL_T 0x80434 |
| 519 | #define G1_RBPL_QI 0x80438 |
| 520 | #define G1_RBPL_BS 0x8043c |
| 521 | |
| 522 | #define G2_RBPS_S 0x80440 |
| 523 | #define G2_RBPS_T 0x80444 |
| 524 | #define G2_RBPS_QI 0x80448 |
| 525 | #define G2_RBPS_BS 0x8044c |
| 526 | #define G2_RBPL_S 0x80450 |
| 527 | #define G2_RBPL_T 0x80454 |
| 528 | #define G2_RBPL_QI 0x80458 |
| 529 | #define G2_RBPL_BS 0x8045c |
| 530 | |
| 531 | #define G3_RBPS_S 0x80460 |
| 532 | #define G3_RBPS_T 0x80464 |
| 533 | #define G3_RBPS_QI 0x80468 |
| 534 | #define G3_RBPS_BS 0x8046c |
| 535 | #define G3_RBPL_S 0x80470 |
| 536 | #define G3_RBPL_T 0x80474 |
| 537 | #define G3_RBPL_QI 0x80478 |
| 538 | #define G3_RBPL_BS 0x8047c |
| 539 | |
| 540 | #define G4_RBPS_S 0x80480 |
| 541 | #define G4_RBPS_T 0x80484 |
| 542 | #define G4_RBPS_QI 0x80488 |
| 543 | #define G4_RBPS_BS 0x8048c |
| 544 | #define G4_RBPL_S 0x80490 |
| 545 | #define G4_RBPL_T 0x80494 |
| 546 | #define G4_RBPL_QI 0x80498 |
| 547 | #define G4_RBPL_BS 0x8049c |
| 548 | |
| 549 | #define G5_RBPS_S 0x804a0 |
| 550 | #define G5_RBPS_T 0x804a4 |
| 551 | #define G5_RBPS_QI 0x804a8 |
| 552 | #define G5_RBPS_BS 0x804ac |
| 553 | #define G5_RBPL_S 0x804b0 |
| 554 | #define G5_RBPL_T 0x804b4 |
| 555 | #define G5_RBPL_QI 0x804b8 |
| 556 | #define G5_RBPL_BS 0x804bc |
| 557 | |
| 558 | #define G6_RBPS_S 0x804c0 |
| 559 | #define G6_RBPS_T 0x804c4 |
| 560 | #define G6_RBPS_QI 0x804c8 |
| 561 | #define G6_RBPS_BS 0x804cc |
| 562 | #define G6_RBPL_S 0x804d0 |
| 563 | #define G6_RBPL_T 0x804d4 |
| 564 | #define G6_RBPL_QI 0x804d8 |
| 565 | #define G6_RBPL_BS 0x804dc |
| 566 | |
| 567 | #define G7_RBPS_S 0x804e0 |
| 568 | #define G7_RBPS_T 0x804e4 |
| 569 | #define G7_RBPS_QI 0x804e8 |
| 570 | #define G7_RBPS_BS 0x804ec |
| 571 | |
| 572 | #define G7_RBPL_S 0x804f0 |
| 573 | #define G7_RBPL_T 0x804f4 |
| 574 | #define G7_RBPL_QI 0x804f8 |
| 575 | #define G7_RBPL_BS 0x804fc |
| 576 | |
| 577 | #define G0_RBRQ_ST 0x80500 |
| 578 | #define G0_RBRQ_H 0x80504 |
| 579 | #define G0_RBRQ_Q 0x80508 |
| 580 | #define RBRQ_THRESH(x) ((x)<<13) |
| 581 | #define RBRQ_SIZE(x) (x) |
| 582 | #define G0_RBRQ_I 0x8050c |
| 583 | #define RBRQ_TIME(x) ((x)<<8) |
| 584 | #define RBRQ_COUNT(x) (x) |
| 585 | |
| 586 | /* fill in 1 ... 7 later */ |
| 587 | |
| 588 | #define G0_TBRQ_B_T 0x80600 |
| 589 | #define G0_TBRQ_H 0x80604 |
| 590 | #define G0_TBRQ_S 0x80608 |
| 591 | #define G0_TBRQ_THRESH 0x8060c |
| 592 | #define TBRQ_THRESH(x) (x) |
| 593 | |
| 594 | /* fill in 1 ... 7 later */ |
| 595 | |
| 596 | #define RH_CONFIG 0x805c0 |
| 597 | #define PHY_INT_ENB (1<<10) |
| 598 | #define OAM_GID(x) (x<<7) |
| 599 | #define PTMR_PRE(x) (x) |
| 600 | |
| 601 | #define G0_INMQ_S 0x80580 |
| 602 | #define G0_INMQ_L 0x80584 |
| 603 | #define G1_INMQ_S 0x80588 |
| 604 | #define G1_INMQ_L 0x8058c |
| 605 | #define G2_INMQ_S 0x80590 |
| 606 | #define G2_INMQ_L 0x80594 |
| 607 | #define G3_INMQ_S 0x80598 |
| 608 | #define G3_INMQ_L 0x8059c |
| 609 | #define G4_INMQ_S 0x805a0 |
| 610 | #define G4_INMQ_L 0x805a4 |
| 611 | #define G5_INMQ_S 0x805a8 |
| 612 | #define G5_INMQ_L 0x805ac |
| 613 | #define G6_INMQ_S 0x805b0 |
| 614 | #define G6_INMQ_L 0x805b4 |
| 615 | #define G7_INMQ_S 0x805b8 |
| 616 | #define G7_INMQ_L 0x805bc |
| 617 | |
| 618 | #define TPDRQ_B_H 0x80680 |
| 619 | #define TPDRQ_T 0x80684 |
| 620 | #define TPDRQ_S 0x80688 |
| 621 | |
| 622 | #define UBUFF_BA 0x8068c |
| 623 | |
| 624 | #define RLBF0_H 0x806c0 |
| 625 | #define RLBF0_T 0x806c4 |
| 626 | #define RLBF1_H 0x806c8 |
| 627 | #define RLBF1_T 0x806cc |
| 628 | #define RLBC_H 0x806d0 |
| 629 | #define RLBC_T 0x806d4 |
| 630 | #define RLBC_H2 0x806d8 |
| 631 | #define TLBF_H 0x806e0 |
| 632 | #define TLBF_T 0x806e4 |
| 633 | #define RLBF0_C 0x806e8 |
| 634 | #define RLBF1_C 0x806ec |
| 635 | #define RXTHRSH 0x806f0 |
| 636 | #define LITHRSH 0x806f4 |
| 637 | |
| 638 | #define LBARB 0x80700 |
| 639 | #define SLICE_X(x) (x<<28) |
| 640 | #define ARB_RNUM_MAX(x) (x<<23) |
| 641 | #define TH_PRTY(x) (x<<21) |
| 642 | #define RH_PRTY(x) (x<<19) |
| 643 | #define TL_PRTY(x) (x<<17) |
| 644 | #define RL_PRTY(x) (x<<15) |
| 645 | #define BUS_MULTI(x) (x<<8) |
| 646 | #define NET_PREF(x) (x) |
| 647 | |
| 648 | #define SDRAMCON 0x80704 |
| 649 | #define BANK_ON (1<<14) |
| 650 | #define WIDE_DATA (1<<13) |
| 651 | #define TWR_WAIT (1<<12) |
| 652 | #define TRP_WAIT (1<<11) |
| 653 | #define TRAS_WAIT (1<<10) |
| 654 | #define REF_RATE(x) (x) |
| 655 | |
| 656 | #define LBSTAT 0x80708 |
| 657 | |
| 658 | #define RCC_STAT 0x8070c |
| 659 | #define RCC_BUSY (1) |
| 660 | |
| 661 | #define TCMCONFIG 0x80740 |
| 662 | #define TM_DESL2 (1<<10) |
| 663 | #define TM_BANK_WAIT(x) (x<<6) |
| 664 | #define TM_ADD_BANK4(x) (x<<4) |
| 665 | #define TM_PAR_CHECK(x) (x<<3) |
| 666 | #define TM_RW_WAIT(x) (x<<2) |
| 667 | #define TM_SRAM_TYPE(x) (x) |
| 668 | |
| 669 | #define TSRB_BA 0x80744 |
| 670 | #define TSRC_BA 0x80748 |
| 671 | #define TMABR_BA 0x8074c |
| 672 | #define TPD_BA 0x80750 |
| 673 | #define TSRD_BA 0x80758 |
| 674 | |
| 675 | #define TX_CONFIG 0x80760 |
| 676 | #define DRF_THRESH(x) (x<<22) |
| 677 | #define TX_UT_MODE(x) (x<<21) |
| 678 | #define TX_VCI_MASK(x) (x<<17) |
| 679 | #define LBFREE_CNT(x) (x) |
| 680 | |
| 681 | #define TXAAL5_PROTO 0x80764 |
| 682 | #define CPCS_UU(x) (x<<8) |
| 683 | #define CPI(x) (x) |
| 684 | |
| 685 | #define RCMCONFIG 0x80780 |
| 686 | #define RM_DESL2(x) (x<<10) |
| 687 | #define RM_BANK_WAIT(x) (x<<6) |
| 688 | #define RM_ADD_BANK(x) (x<<4) |
| 689 | #define RM_PAR_CHECK(x) (x<<3) |
| 690 | #define RM_RW_WAIT(x) (x<<2) |
| 691 | #define RM_SRAM_TYPE(x) (x) |
| 692 | |
| 693 | #define RCMRSRB_BA 0x80784 |
| 694 | #define RCMLBM_BA 0x80788 |
| 695 | #define RCMABR_BA 0x8078c |
| 696 | |
| 697 | #define RC_CONFIG 0x807c0 |
| 698 | #define UT_RD_DELAY(x) (x<<11) |
| 699 | #define WRAP_MODE(x) (x<<10) |
| 700 | #define RC_UT_MODE(x) (x<<9) |
| 701 | #define RX_ENABLE (1<<8) |
| 702 | #define RX_VALVP(x) (x<<4) |
| 703 | #define RX_VALVC(x) (x) |
| 704 | |
| 705 | #define MCC 0x807c4 |
| 706 | #define OEC 0x807c8 |
| 707 | #define DCC 0x807cc |
| 708 | #define CEC 0x807d0 |
| 709 | |
| 710 | #define HSP_BA 0x807f0 |
| 711 | |
| 712 | #define LB_CONFIG 0x807f4 |
| 713 | #define LB_SIZE(x) (x) |
| 714 | |
| 715 | #define CON_DAT 0x807f8 |
| 716 | #define CON_CTL 0x807fc |
| 717 | #define CON_CTL_MBOX (2<<30) |
| 718 | #define CON_CTL_TCM (1<<30) |
| 719 | #define CON_CTL_RCM (0<<30) |
| 720 | #define CON_CTL_WRITE (1<<29) |
| 721 | #define CON_CTL_READ (0<<29) |
| 722 | #define CON_CTL_BUSY (1<<28) |
| 723 | #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */ |
| 724 | #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */ |
| 725 | #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */ |
| 726 | #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */ |
| 727 | #define CON_CTL_ADDR(x) (x) |
| 728 | |
| 729 | #define FRAMER 0x80800 /* to 0x80bfc */ |
| 730 | |
| 731 | /* 3.3 network controller (internal) mailbox registers */ |
| 732 | |
| 733 | #define CS_STPER0 0x0 |
| 734 | /* ... */ |
| 735 | #define CS_STPER31 0x01f |
| 736 | |
| 737 | #define CS_STTIM0 0x020 |
| 738 | /* ... */ |
| 739 | #define CS_STTIM31 0x03f |
| 740 | |
| 741 | #define CS_TGRLD0 0x040 |
| 742 | /* ... */ |
| 743 | #define CS_TGRLD15 0x04f |
| 744 | |
| 745 | #define CS_ERTHR0 0x050 |
| 746 | #define CS_ERTHR1 0x051 |
| 747 | #define CS_ERTHR2 0x052 |
| 748 | #define CS_ERTHR3 0x053 |
| 749 | #define CS_ERTHR4 0x054 |
| 750 | #define CS_ERCTL0 0x055 |
| 751 | #define TX_ENABLE (1<<28) |
| 752 | #define ER_ENABLE (1<<27) |
| 753 | #define CS_ERCTL1 0x056 |
| 754 | #define CS_ERCTL2 0x057 |
| 755 | #define CS_ERSTAT0 0x058 |
| 756 | #define CS_ERSTAT1 0x059 |
| 757 | |
| 758 | #define CS_RTCCT 0x060 |
| 759 | #define CS_RTFWC 0x061 |
| 760 | #define CS_RTFWR 0x062 |
| 761 | #define CS_RTFTC 0x063 |
| 762 | #define CS_RTATR 0x064 |
| 763 | |
| 764 | #define CS_TFBSET 0x070 |
| 765 | #define CS_TFBADD 0x071 |
| 766 | #define CS_TFBSUB 0x072 |
| 767 | #define CS_WCRMAX 0x073 |
| 768 | #define CS_WCRMIN 0x074 |
| 769 | #define CS_WCRINC 0x075 |
| 770 | #define CS_WCRDEC 0x076 |
| 771 | #define CS_WCRCEIL 0x077 |
| 772 | #define CS_BWDCNT 0x078 |
| 773 | |
| 774 | #define CS_OTPPER 0x080 |
| 775 | #define CS_OTWPER 0x081 |
| 776 | #define CS_OTTLIM 0x082 |
| 777 | #define CS_OTTCNT 0x083 |
| 778 | |
| 779 | #define CS_HGRRT0 0x090 |
| 780 | /* ... */ |
| 781 | #define CS_HGRRT7 0x097 |
| 782 | |
| 783 | #define CS_ORPTRS 0x0a0 |
| 784 | |
| 785 | #define RXCON_CLOSE 0x100 |
| 786 | |
| 787 | |
| 788 | #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */ |
| 789 | #define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */ |
| 790 | |
| 791 | /* 2.5 transmit connection memory registers */ |
| 792 | |
| 793 | #define TSR0_CONN_STATE(x) ((x>>28) & 0x7) |
| 794 | #define TSR0_USE_WMIN (1<<23) |
| 795 | #define TSR0_GROUP(x) ((x & 0x7)<<18) |
| 796 | #define TSR0_ABR (2<<16) |
| 797 | #define TSR0_UBR (1<<16) |
| 798 | #define TSR0_CBR (0<<16) |
| 799 | #define TSR0_PROT (1<<15) |
| 800 | #define TSR0_AAL0_SDU (2<<12) |
| 801 | #define TSR0_AAL0 (1<<12) |
| 802 | #define TSR0_AAL5 (0<<12) |
| 803 | #define TSR0_HALT_ER (1<<11) |
| 804 | #define TSR0_MARK_CI (1<<10) |
| 805 | #define TSR0_MARK_ER (1<<9) |
| 806 | #define TSR0_UPDATE_GER (1<<8) |
| 807 | #define TSR0_RC_INDEX(x) (x & 0x1F) |
| 808 | |
| 809 | #define TSR1_PCR(x) ((x & 0x7FFF)<<16) |
| 810 | #define TSR1_MCR(x) (x & 0x7FFF) |
| 811 | |
| 812 | #define TSR2_ACR(x) ((x & 0x7FFF)<<16) |
| 813 | |
| 814 | #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24) |
| 815 | #define TSR3_CRM_CNT(x) (x & 0xFFFF) |
| 816 | |
| 817 | #define TSR4_FLUSH_CONN (1<<31) |
| 818 | #define TSR4_SESSION_ENDED (1<<30) |
| 819 | #define TSR4_CRC10 (1<<28) |
| 820 | #define TSR4_NULL_CRC10 (1<<27) |
| 821 | #define TSR4_PROT (1<<26) |
| 822 | #define TSR4_AAL0_SDU (2<<23) |
| 823 | #define TSR4_AAL0 (1<<23) |
| 824 | #define TSR4_AAL5 (0<<23) |
| 825 | |
| 826 | #define TSR9_OPEN_CONN (1<<20) |
| 827 | |
| 828 | #define TSR11_ICR(x) ((x & 0x7FFF)<<16) |
| 829 | #define TSR11_TRM(x) ((x & 0x7)<<13) |
| 830 | #define TSR11_NRM(x) ((x & 0x7)<<10) |
| 831 | #define TSR11_ADTF(x) (x & 0x3FF) |
| 832 | |
| 833 | #define TSR13_RDF(x) ((x & 0xF)<<23) |
| 834 | #define TSR13_RIF(x) ((x & 0xF)<<19) |
| 835 | #define TSR13_CDF(x) ((x & 0x7)<<16) |
| 836 | #define TSR13_CRM(x) (x & 0xFFFF) |
| 837 | |
| 838 | #define TSR14_DELETE (1<<31) |
| 839 | #define TSR14_ABR_CLOSE (1<<16) |
| 840 | |
| 841 | /* 2.7.1 per connection receieve state registers */ |
| 842 | |
| 843 | #define RSR0_START_PDU (1<<10) |
| 844 | #define RSR0_OPEN_CONN (1<<6) |
| 845 | #define RSR0_CLOSE_CONN (0<<6) |
| 846 | #define RSR0_PPD_ENABLE (1<<5) |
| 847 | #define RSR0_EPD_ENABLE (1<<4) |
| 848 | #define RSR0_TCP_CKSUM (1<<3) |
| 849 | #define RSR0_AAL5 (0) |
| 850 | #define RSR0_AAL0 (1) |
| 851 | #define RSR0_AAL0_SDU (2) |
| 852 | #define RSR0_RAWCELL (3) |
| 853 | #define RSR0_RAWCELL_CRC10 (4) |
| 854 | |
| 855 | #define RSR1_AQI_ENABLE (1<<20) |
| 856 | #define RSR1_RBPL_ONLY (1<<19) |
| 857 | #define RSR1_GROUP(x) ((x)<<16) |
| 858 | |
| 859 | #define RSR4_AQI_ENABLE (1<<30) |
| 860 | #define RSR4_GROUP(x) ((x)<<27) |
| 861 | #define RSR4_RBPL_ONLY (1<<26) |
| 862 | |
| 863 | /* 2.1.4 transmit packet descriptor */ |
| 864 | |
| 865 | #define TPD_USERCELL 0x0 |
| 866 | #define TPD_SEGMENT_OAMF5 0x4 |
| 867 | #define TPD_END2END_OAMF5 0x5 |
| 868 | #define TPD_RMCELL 0x6 |
| 869 | #define TPD_CELLTYPE(x) (x<<3) |
| 870 | #define TPD_EOS (1<<2) |
| 871 | #define TPD_CLP (1<<1) |
| 872 | #define TPD_INT (1<<0) |
| 873 | #define TPD_LST (1<<31) |
| 874 | |
| 875 | /* table 4.3 serial eeprom information */ |
| 876 | |
| 877 | #define PROD_ID 0x08 /* char[] */ |
| 878 | #define PROD_ID_LEN 30 |
| 879 | #define HW_REV 0x26 /* char[] */ |
| 880 | #define M_SN 0x3a /* integer */ |
| 881 | #define MEDIA 0x3e /* integer */ |
| 882 | #define HE155MM 0x26 |
| 883 | #define HE155SM 0x27 |
| 884 | #define HE622MM 0x46 |
| 885 | #define HE622SM 0x47 |
| 886 | #define MAC_ADDR 0x42 /* char[] */ |
| 887 | |
| 888 | #define CS_LOW 0x0 |
| 889 | #define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */ |
| 890 | #define CLK_LOW 0x0 |
| 891 | #define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */ |
| 892 | #define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */ |
| 893 | #define EEPROM_DELAY 400 /* microseconds */ |
| 894 | |
| 895 | #endif /* _HE_H_ */ |