blob: 0af8fa5f53e1697f8fc5ac2e8028b2e80f8c1bd7 [file] [log] [blame]
Pushkar Joshiecbf7e02012-12-06 10:45:34 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Pushkar Joshifaf92a72012-10-29 17:45:27 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/ {
14 tmc_etr: tmc@fc322000 {
15 compatible = "arm,coresight-tmc";
16 reg = <0xfc322000 0x1000>,
17 <0xfc37c000 0x3000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080018 reg-names = "tmc-etr-base", "tmc-etr-bam-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070019
20 qcom,memory-reservation-type = "EBI1";
Pushkar Joshi558ec8f2013-02-25 15:39:10 -080021 qcom,memory-reservation-size = <0x20000>; /* 128K EBI1 buffer */
Pushkar Joshifaf92a72012-10-29 17:45:27 -070022
23 coresight-id = <0>;
24 coresight-name = "coresight-tmc-etr";
25 coresight-nr-inports = <1>;
Pratik Patel52ea7f72013-02-08 11:56:19 -080026 coresight-ctis = <&cti0 &cti8>;
Pushkar Joshifaf92a72012-10-29 17:45:27 -070027 };
28
29 tpiu: tpiu@fc318000 {
30 compatible = "arm,coresight-tpiu";
31 reg = <0xfc318000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080032 reg-names = "tpiu-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070033
34 coresight-id = <1>;
35 coresight-name = "coresight-tpiu";
36 coresight-nr-inports = <1>;
37 };
38
39 replicator: replicator@fc31c000 {
40 compatible = "qcom,coresight-replicator";
41 reg = <0xfc31c000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080042 reg-names = "replicator-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070043
44 coresight-id = <2>;
45 coresight-name = "coresight-replicator";
46 coresight-nr-inports = <1>;
47 coresight-outports = <0 1>;
48 coresight-child-list = <&tmc_etr &tpiu>;
49 coresight-child-ports = <0 0>;
50 };
51
52 tmc_etf: tmc@fc307000 {
53 compatible = "arm,coresight-tmc";
54 reg = <0xfc307000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080055 reg-names = "tmc-etf-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070056
57 coresight-id = <3>;
58 coresight-name = "coresight-tmc-etf";
59 coresight-nr-inports = <1>;
60 coresight-outports = <0>;
61 coresight-child-list = <&replicator>;
62 coresight-child-ports = <0>;
63 coresight-default-sink;
Pratik Patel52ea7f72013-02-08 11:56:19 -080064 coresight-ctis = <&cti0 &cti8>;
Pushkar Joshifaf92a72012-10-29 17:45:27 -070065 };
66
67 funnel_merg: funnel@fc31b000 {
68 compatible = "arm,coresight-funnel";
69 reg = <0xfc31b000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080070 reg-names = "funnel-merg-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070071
72 coresight-id = <4>;
73 coresight-name = "coresight-funnel-merg";
74 coresight-nr-inports = <2>;
75 coresight-outports = <0>;
76 coresight-child-list = <&tmc_etf>;
77 coresight-child-ports = <0>;
78 };
79
80 funnel_in0: funnel@fc319000 {
81 compatible = "arm,coresight-funnel";
82 reg = <0xfc319000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080083 reg-names = "funnel-in0-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070084
85 coresight-id = <5>;
86 coresight-name = "coresight-funnel-in0";
87 coresight-nr-inports = <8>;
88 coresight-outports = <0>;
89 coresight-child-list = <&funnel_merg>;
90 coresight-child-ports = <0>;
91 };
92
93 funnel_in1: funnel@fc31a000 {
94 compatible = "arm,coresight-funnel";
95 reg = <0xfc31a000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -080096 reg-names = "funnel-in1-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -070097
98 coresight-id = <6>;
99 coresight-name = "coresight-funnel-in1";
100 coresight-nr-inports = <8>;
101 coresight-outports = <0>;
102 coresight-child-list = <&funnel_merg>;
103 coresight-child-ports = <1>;
104 };
105
106 stm: stm@fc321000 {
107 compatible = "arm,coresight-stm";
108 reg = <0xfc321000 0x1000>,
109 <0xfa280000 0x180000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -0800110 reg-names = "stm-base", "stm-data-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700111
112 coresight-id = <7>;
113 coresight-name = "coresight-stm";
114 coresight-nr-inports = <0>;
115 coresight-outports = <0>;
116 coresight-child-list = <&funnel_in1>;
117 coresight-child-ports = <7>;
118 };
119
Pushkar Joshiecbf7e02012-12-06 10:45:34 -0800120 etm: etm@fc332000 {
121 compatible = "arm,coresight-etm";
122 reg = <0xfc332000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -0800123 reg-names = "etm-base";
Pushkar Joshiecbf7e02012-12-06 10:45:34 -0800124
125 coresight-id = <8>;
126 coresight-name = "coresight-etm";
127 coresight-nr-inports = <0>;
128 coresight-outports = <0>;
129 coresight-child-list = <&funnel_in0>;
130 coresight-child-ports = <4>;
Pratik Patele8a14432013-01-22 18:44:17 -0800131
132 qcom,round-robin;
Pushkar Joshiecbf7e02012-12-06 10:45:34 -0800133 };
134
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700135 csr: csr@fc302000 {
136 compatible = "qcom,coresight-csr";
137 reg = <0xfc302000 0x1000>;
Pratik Patel4ec2cd12013-02-07 16:56:44 -0800138 reg-names = "csr-base";
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700139
Pushkar Joshiecbf7e02012-12-06 10:45:34 -0800140 coresight-id = <9>;
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700141 coresight-name = "coresight-csr";
142 coresight-nr-inports = <0>;
Pratik Patel99bac0f2013-01-14 22:24:25 -0800143
144 qcom,blk-size = <1>;
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700145 };
Pratik Patel52ea7f72013-02-08 11:56:19 -0800146
147 cti0: cti@fc308000 {
148 compatible = "arm,coresight-cti";
149 reg = <0xfc308000 0x1000>;
150 reg-names = "cti0-base";
151
152 coresight-id = <10>;
153 coresight-name = "coresight-cti0";
154 coresight-nr-inports = <0>;
155 };
156
157 cti1: cti@fc309000 {
158 compatible = "arm,coresight-cti";
159 reg = <0xfc309000 0x1000>;
160 reg-names = "cti1-base";
161
162 coresight-id = <11>;
163 coresight-name = "coresight-cti1";
164 coresight-nr-inports = <0>;
165 };
166
167 cti2: cti@fc30a000 {
168 compatible = "arm,coresight-cti";
169 reg = <0xfc30a000 0x1000>;
170 reg-names = "cti2-base";
171
172 coresight-id = <12>;
173 coresight-name = "coresight-cti2";
174 coresight-nr-inports = <0>;
175 };
176
177 cti3: cti@fc30b000 {
178 compatible = "arm,coresight-cti";
179 reg = <0xfc30b000 0x1000>;
180 reg-names = "cti3-base";
181
182 coresight-id = <13>;
183 coresight-name = "coresight-cti3";
184 coresight-nr-inports = <0>;
185 };
186
187 cti4: cti@fc30c000 {
188 compatible = "arm,coresight-cti";
189 reg = <0xfc30c000 0x1000>;
190 reg-names = "cti4-base";
191
192 coresight-id = <14>;
193 coresight-name = "coresight-cti4";
194 coresight-nr-inports = <0>;
195 };
196
197 cti5: cti@fc30d000 {
198 compatible = "arm,coresight-cti";
199 reg = <0xfc30d000 0x1000>;
200 reg-names = "cti5-base";
201
202 coresight-id = <15>;
203 coresight-name = "coresight-cti5";
204 coresight-nr-inports = <0>;
205 };
206
207 cti6: cti@fc30e000 {
208 compatible = "arm,coresight-cti";
209 reg = <0xfc30e000 0x1000>;
210 reg-names = "cti6-base";
211
212 coresight-id = <16>;
213 coresight-name = "coresight-cti6";
214 coresight-nr-inports = <0>;
215 };
216
217 cti7: cti@fc30f000 {
218 compatible = "arm,coresight-cti";
219 reg = <0xfc30f000 0x1000>;
220 reg-names = "cti7-base";
221
222 coresight-id = <17>;
223 coresight-name = "coresight-cti7";
224 coresight-nr-inports = <0>;
225 };
226
227 cti8: cti@fc310000 {
228 compatible = "arm,coresight-cti";
229 reg = <0xfc310000 0x1000>;
230 reg-names = "cti8-base";
231
232 coresight-id = <18>;
233 coresight-name = "coresight-cti8";
234 coresight-nr-inports = <0>;
235 };
236
237 cti_cpu: cti@fc333000 {
238 compatible = "arm,coresight-cti";
239 reg = <0xfc333000 0x1000>;
240 reg-names = "cti-cpu-base";
241
242 coresight-id = <19>;
243 coresight-name = "coresight-cti-cpu";
244 coresight-nr-inports = <0>;
245 };
Pushkar Joshifaf92a72012-10-29 17:45:27 -0700246};