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Manoj Rao7708a3a2012-12-13 18:30:58 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Manoj Rao14648742012-03-30 19:42:12 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#ifndef __MHL_SPEC_DEFS_H__
14#define __MHL_SPEC_DEFS_H__
15
16enum DevCapOffset_e {
17 DEVCAP_OFFSET_DEV_STATE = 0x00,
18 DEVCAP_OFFSET_MHL_VERSION = 0x01,
19 DEVCAP_OFFSET_DEV_CAT = 0x02,
20 DEVCAP_OFFSET_ADOPTER_ID_H = 0x03,
21 DEVCAP_OFFSET_ADOPTER_ID_L = 0x04,
22 DEVCAP_OFFSET_VID_LINK_MODE = 0x05,
23 DEVCAP_OFFSET_AUD_LINK_MODE = 0x06,
24 DEVCAP_OFFSET_VIDEO_TYPE = 0x07,
25 DEVCAP_OFFSET_LOG_DEV_MAP = 0x08,
26 DEVCAP_OFFSET_BANDWIDTH = 0x09,
27 DEVCAP_OFFSET_FEATURE_FLAG = 0x0A,
28 DEVCAP_OFFSET_DEVICE_ID_H = 0x0B,
29 DEVCAP_OFFSET_DEVICE_ID_L = 0x0C,
30 DEVCAP_OFFSET_SCRATCHPAD_SIZE = 0x0D,
31 DEVCAP_OFFSET_INT_STAT_SIZE = 0x0E,
32 DEVCAP_OFFSET_RESERVED = 0x0F,
33 /* this one must be last */
34 DEVCAP_SIZE
35};
36
37#ifndef __MHL_MSM_8334_REGS_H__
38#define __MHL_MSM_8334_REGS_H__
39
40#define BIT0 0x01
41#define BIT1 0x02
42#define BIT2 0x04
43#define BIT3 0x08
44#define BIT4 0x10
45#define BIT5 0x20
46#define BIT6 0x40
47#define BIT7 0x80
48
49#define LOW 0
50#define HIGH 1
51
52#define MAX_PAGES 8
53#endif
54
55
56/* Version that this chip supports*/
57/* bits 4..7 */
58#define MHL_VER_MAJOR (0x01 << 4)
59/* bits 0..3 */
Abhishek Kharbandad80b5d32013-02-22 12:35:19 -080060#define MHL_VER_MINOR 0x02
Manoj Rao14648742012-03-30 19:42:12 -070061#define MHL_VERSION (MHL_VER_MAJOR | MHL_VER_MINOR)
62
63/*Device Category*/
64#define MHL_DEV_CATEGORY_OFFSET DEVCAP_OFFSET_DEV_CAT
65#define MHL_DEV_CATEGORY_POW_BIT (BIT4)
66
67#define MHL_DEV_CAT_SOURCE 0x02
68
69/*Video Link Mode*/
70#define MHL_DEV_VID_LINK_SUPPRGB444 0x01
71#define MHL_DEV_VID_LINK_SUPPYCBCR444 0x02
72#define MHL_DEV_VID_LINK_SUPPYCBCR422 0x04
73#define MHL_DEV_VID_LINK_SUPP_PPIXEL 0x08
74#define MHL_DEV_VID_LINK_SUPP_ISLANDS 0x10
75
76/*Audio Link Mode Support*/
77#define MHL_DEV_AUD_LINK_2CH 0x01
78#define MHL_DEV_AUD_LINK_8CH 0x02
79
80
81/*Feature Flag in the devcap*/
82#define MHL_DEV_FEATURE_FLAG_OFFSET DEVCAP_OFFSET_FEATURE_FLAG
83/* Dongles have freedom to not support RCP */
84#define MHL_FEATURE_RCP_SUPPORT BIT0
85/* Dongles have freedom to not support RAP */
86#define MHL_FEATURE_RAP_SUPPORT BIT1
87/* Dongles have freedom to not support SCRATCHPAD */
88#define MHL_FEATURE_SP_SUPPORT BIT2
89
90/*Logical Dev Map*/
91#define MHL_DEV_LD_DISPLAY (0x01 << 0)
92#define MHL_DEV_LD_VIDEO (0x01 << 1)
93#define MHL_DEV_LD_AUDIO (0x01 << 2)
94#define MHL_DEV_LD_MEDIA (0x01 << 3)
95#define MHL_DEV_LD_TUNER (0x01 << 4)
96#define MHL_DEV_LD_RECORD (0x01 << 5)
97#define MHL_DEV_LD_SPEAKER (0x01 << 6)
98#define MHL_DEV_LD_GUI (0x01 << 7)
99
100/*Bandwidth*/
101/* 225 MHz */
102#define MHL_BANDWIDTH_LIMIT 22
103
104
105#define MHL_STATUS_REG_CONNECTED_RDY 0x30
106#define MHL_STATUS_REG_LINK_MODE 0x31
107
108#define MHL_STATUS_DCAP_RDY BIT0
109
110#define MHL_STATUS_CLK_MODE_MASK 0x07
111#define MHL_STATUS_CLK_MODE_PACKED_PIXEL 0x02
112#define MHL_STATUS_CLK_MODE_NORMAL 0x03
113#define MHL_STATUS_PATH_EN_MASK 0x08
114#define MHL_STATUS_PATH_ENABLED 0x08
115#define MHL_STATUS_PATH_DISABLED 0x00
116#define MHL_STATUS_MUTED_MASK 0x10
117
118#define MHL_RCHANGE_INT 0x20
119#define MHL_DCHANGE_INT 0x21
120
121#define MHL_INT_DCAP_CHG BIT0
122#define MHL_INT_DSCR_CHG BIT1
123#define MHL_INT_REQ_WRT BIT2
124#define MHL_INT_GRT_WRT BIT3
125
126/* On INTR_1 the EDID_CHG is located at BIT 0*/
127#define MHL_INT_EDID_CHG BIT1
128
129/* This contains one nibble each - max offset */
130#define MHL_INT_AND_STATUS_SIZE 0x33
Manoj Rao455c8c72013-01-21 16:44:08 -0800131#define MHL_SCRATCHPAD_OFFSET 0x40
Manoj Rao14648742012-03-30 19:42:12 -0700132#define MHL_SCRATCHPAD_SIZE 16
Manoj Rao455c8c72013-01-21 16:44:08 -0800133#define MAX_SCRATCHPAD_TRANSFER_SIZE 64
134#define ADOPTER_ID_SIZE 2
135
Manoj Rao14648742012-03-30 19:42:12 -0700136/* manually define highest number */
137#define MHL_MAX_BUFFER_SIZE MHL_SCRATCHPAD_SIZE
138
139
140
141enum {
142 /* RCP sub-command */
143 MHL_MSC_MSG_RCP = 0x10,
144 /* RCP Acknowledge sub-command */
145 MHL_MSC_MSG_RCPK = 0x11,
146 /* RCP Error sub-command */
147 MHL_MSC_MSG_RCPE = 0x12,
148 /* Mode Change Warning sub-command */
149 MHL_MSC_MSG_RAP = 0x20,
150 /* MCW Acknowledge sub-command */
151 MHL_MSC_MSG_RAPK = 0x21,
152};
153
Manoj Raof7110b82012-07-29 22:29:02 -0700154#define MHL_RCPE_NO_ERROR 0x00
155#define MHL_RCPE_UNSUPPORTED_KEY_CODE 0x01
Manoj Rao7708a3a2012-12-13 18:30:58 -0800156#define MHL_RCPE_INEFFECTIVE_KEY_CODE 0x01
Manoj Raof7110b82012-07-29 22:29:02 -0700157#define MHL_RCPE_BUSY 0x02
158
159#define MHL_RAPK_NO_ERROR 0x00
160#define MHL_RAPK_UNRECOGNIZED_ACTION_CODE 0x01
161#define MHL_RAPK_UNSUPPORTED_ACTION_CODE 0x02
162#define MHL_RAPK_BUSY 0x03
163
Manoj Rao7708a3a2012-12-13 18:30:58 -0800164#define T_ABORT_NEXT (2050)
165
Manoj Rao14648742012-03-30 19:42:12 -0700166/* MHL spec related defines*/
167enum {
168 /* Command or Data byte acknowledge */
169 MHL_ACK = 0x33,
170 /* Command or Data byte not acknowledge */
171 MHL_NACK = 0x34,
172 /* Transaction abort */
173 MHL_ABORT = 0x35,
174 /* 0xE0 - Write one status register strip top bit */
175 MHL_WRITE_STAT = 0x60 | 0x80,
176 /* Write one interrupt register */
177 MHL_SET_INT = 0x60,
178 /* Read one register */
179 MHL_READ_DEVCAP = 0x61,
180 /* Read CBUS revision level from follower */
181 MHL_GET_STATE = 0x62,
182 /* Read vendor ID value from follower. */
183 MHL_GET_VENDOR_ID = 0x63,
184 /* Set Hot Plug Detect in follower */
185 MHL_SET_HPD = 0x64,
186 /* Clear Hot Plug Detect in follower */
187 MHL_CLR_HPD = 0x65,
188 /* Set Capture ID for downstream device. */
189 MHL_SET_CAP_ID = 0x66,
190 /* Get Capture ID from downstream device. */
191 MHL_GET_CAP_ID = 0x67,
192 /* VS command to send RCP sub-commands */
193 MHL_MSC_MSG = 0x68,
194 /* Get Vendor-Specific command error code. */
195 MHL_GET_SC1_ERRORCODE = 0x69,
196 /* Get DDC channel command error code. */
197 MHL_GET_DDC_ERRORCODE = 0x6A,
198 /* Get MSC command error code. */
199 MHL_GET_MSC_ERRORCODE = 0x6B,
200 /* Write 1-16 bytes to responder's scratchpad. */
201 MHL_WRITE_BURST = 0x6C,
202 /* Get channel 3 command error code. */
203 MHL_GET_SC3_ERRORCODE = 0x6D,
204};
205
Manoj Rao7708a3a2012-12-13 18:30:58 -0800206/* Polling. */
207#define MHL_RAP_POLL 0x00
Manoj Rao14648742012-03-30 19:42:12 -0700208/* Turn content streaming ON. */
209#define MHL_RAP_CONTENT_ON 0x10
210/* Turn content streaming OFF. */
211#define MHL_RAP_CONTENT_OFF 0x11
212
213/*
214 *
215 * MHL Timings applicable to this driver.
216 *
217 */
218/* 100 - 1000 milliseconds. Per MHL 1.0 Specs */
219#define T_SRC_VBUS_CBUS_TO_STABLE (200)
220/* 20 milliseconds. Per MHL 1.0 Specs */
221#define T_SRC_WAKE_PULSE_WIDTH_1 (20)
222/* 60 milliseconds. Per MHL 1.0 Specs */
223#define T_SRC_WAKE_PULSE_WIDTH_2 (60)
224
225/* 100 - 1000 milliseconds. Per MHL 1.0 Specs */
226#define T_SRC_WAKE_TO_DISCOVER (500)
227
228#define T_SRC_VBUS_CBUS_T0_STABLE (500)
229
230/* Allow RSEN to stay low this much before reacting.*/
231#define T_SRC_RSEN_DEGLITCH (100)
232
233/* Wait this much after connection before reacting to RSEN (300-500ms)*/
234/* Per specs between 300 to 500 ms*/
235#define T_SRC_RXSENSE_CHK (400)
236
237#endif /* __MHL_SPEC_DEFS_H__ */