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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Paul Walmsley0d8e2d02010-11-24 16:49:05 -070031#include <linux/console.h>
Jean Pihet5e7c58d2011-03-03 11:25:43 +010032#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070033
Russell King2c74a0c2011-06-22 17:41:48 +010034#include <asm/suspend.h>
35
Tony Lindgrence491cf2009-10-20 09:40:47 -070036#include <plat/sram.h>
Paul Walmsley1540f2142010-12-21 21:05:15 -070037#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070038#include "powerdomain.h"
Tony Lindgrence491cf2009-10-20 09:40:47 -070039#include <plat/serial.h>
Rajendra Nayak61255ab2008-09-26 17:49:56 +053040#include <plat/sdrc.h>
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053041#include <plat/prcm.h>
42#include <plat/gpmc.h>
Tero Kristof2d11852008-08-28 13:13:31 +000043#include <plat/dma.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070044
Paul Walmsley59fb6592010-12-21 15:30:55 -070045#include "cm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070046#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
48
Paul Walmsley59fb6592010-12-21 15:30:55 -070049#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070050#include "pm.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030051#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030053
Kevin Hilmane83df172010-12-08 22:40:40 +000054#ifdef CONFIG_SUSPEND
55static suspend_state_t suspend_state = PM_SUSPEND_ON;
56static inline bool is_suspending(void)
57{
Kevin Hilmandca2d0e2011-09-13 11:18:44 -070058 return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
Kevin Hilmane83df172010-12-08 22:40:40 +000059}
60#else
61static inline bool is_suspending(void)
62{
63 return false;
64}
65#endif
66
Nishanth Menon8cdfd832010-12-20 14:05:05 -060067/* pm34xx errata defined in pm.h */
68u16 pm34xx_errata;
69
Kevin Hilman8bd22942009-05-28 10:56:16 -070070struct power_state {
71 struct powerdomain *pwrdm;
72 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070073#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070074 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070075#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070076 struct list_head node;
77};
78
79static LIST_HEAD(pwrst_list);
80
Tero Kristo27d59a42008-10-13 13:15:00 +030081static int (*_omap_save_secure_sram)(u32 *addr);
Jean Pihet46e130d2011-06-29 18:40:23 +020082void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030083
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053084static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85static struct powerdomain *core_pwrdm, *per_pwrdm;
Tero Kristoc16c3f62008-12-11 16:46:57 +020086static struct powerdomain *cam_pwrdm;
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053087
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053088static inline void omap3_per_save_context(void)
89{
90 omap_gpio_save_context();
91}
92
93static inline void omap3_per_restore_context(void)
94{
95 omap_gpio_restore_context();
96}
97
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020098static void omap3_enable_io_chain(void)
99{
100 int timeout = 0;
101
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600102 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
103 PM_WKEN);
104 /* Do a readback to assure write has been done */
105 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200106
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600107 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
108 OMAP3430_ST_IO_CHAIN_MASK)) {
109 timeout++;
110 if (timeout > 1000) {
111 pr_err("Wake up daisy chain activation failed.\n");
112 return;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200113 }
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600114 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
115 WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200116 }
117}
118
119static void omap3_disable_io_chain(void)
120{
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600121 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
122 PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200123}
124
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530125static void omap3_core_save_context(void)
126{
Paul Walmsley596efe42010-12-21 21:05:16 -0700127 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +0200128
129 /*
130 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +0100131 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +0200132 */
133 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
134 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
135
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530136 /* Save the Interrupt controller context */
137 omap_intc_save_context();
138 /* Save the GPMC context */
139 omap3_gpmc_save_context();
140 /* Save the system control module context, padconf already save above*/
141 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000142 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530143}
144
145static void omap3_core_restore_context(void)
146{
147 /* Restore the control module context, padconf restored by h/w */
148 omap3_control_restore_context();
149 /* Restore the GPMC context */
150 omap3_gpmc_restore_context();
151 /* Restore the interrupt controller context */
152 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000153 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530154}
155
Tero Kristo9d971402008-12-12 11:20:05 +0200156/*
157 * FIXME: This function should be called before entering off-mode after
158 * OMAP3 secure services have been accessed. Currently it is only called
159 * once during boot sequence, but this works as we are not using secure
160 * services.
161 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800162static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300163{
164 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800165 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300166
167 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300168 /*
169 * MPU next state must be set to POWER_ON temporarily,
170 * otherwise the WFI executed inside the ROM code
171 * will hang the system.
172 */
173 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
174 ret = _omap_save_secure_sram((u32 *)
175 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800176 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300177 /* Following is for error tracking, it should not happen */
178 if (ret) {
179 printk(KERN_ERR "save_secure_sram() returns %08x\n",
180 ret);
181 while (1)
182 ;
183 }
184 }
185}
186
Jon Hunter77da2d92009-06-27 00:07:25 -0500187/*
188 * PRCM Interrupt Handler Helper Function
189 *
190 * The purpose of this function is to clear any wake-up events latched
191 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
192 * may occur whilst attempting to clear a PM_WKST_x register and thus
193 * set another bit in this register. A while loop is used to ensure
194 * that any peripheral wake-up events occurring while attempting to
195 * clear the PM_WKST_x are detected and cleared.
196 */
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700197static int prcm_clear_mod_irqs(s16 module, u8 regs)
Jon Hunter77da2d92009-06-27 00:07:25 -0500198{
Vikram Pandita71a80772009-07-17 19:33:09 -0500199 u32 wkst, fclk, iclk, clken;
Jon Hunter77da2d92009-06-27 00:07:25 -0500200 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
201 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
202 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
Paul Walmsley5d805972009-07-22 10:18:07 -0700203 u16 grpsel_off = (regs == 3) ?
204 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700205 int c = 0;
Jon Hunter77da2d92009-06-27 00:07:25 -0500206
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700207 wkst = omap2_prm_read_mod_reg(module, wkst_off);
208 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500209 if (wkst) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700210 iclk = omap2_cm_read_mod_reg(module, iclk_off);
211 fclk = omap2_cm_read_mod_reg(module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500212 while (wkst) {
Vikram Pandita71a80772009-07-17 19:33:09 -0500213 clken = wkst;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700214 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
Vikram Pandita71a80772009-07-17 19:33:09 -0500215 /*
216 * For USBHOST, we don't know whether HOST1 or
217 * HOST2 woke us up, so enable both f-clocks
218 */
219 if (module == OMAP3430ES2_USBHOST_MOD)
220 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700221 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
222 omap2_prm_write_mod_reg(wkst, module, wkst_off);
223 wkst = omap2_prm_read_mod_reg(module, wkst_off);
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700224 c++;
Jon Hunter77da2d92009-06-27 00:07:25 -0500225 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700226 omap2_cm_write_mod_reg(iclk, module, iclk_off);
227 omap2_cm_write_mod_reg(fclk, module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500228 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700229
230 return c;
231}
232
233static int _prcm_int_handle_wakeup(void)
234{
235 int c;
236
237 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
238 c += prcm_clear_mod_irqs(CORE_MOD, 1);
239 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
240 if (omap_rev() > OMAP3430_REV_ES1_0) {
241 c += prcm_clear_mod_irqs(CORE_MOD, 3);
242 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
243 }
244
245 return c;
Jon Hunter77da2d92009-06-27 00:07:25 -0500246}
247
248/*
249 * PRCM Interrupt Handler
250 *
251 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
252 * interrupts from the PRCM for the MPU. These bits must be cleared in
253 * order to clear the PRCM interrupt. The PRCM interrupt handler is
254 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
255 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
256 * register indicates that a wake-up event is pending for the MPU and
257 * this bit can only be cleared if the all the wake-up events latched
258 * in the various PM_WKST_x registers have been cleared. The interrupt
259 * handler is implemented using a do-while loop so that if a wake-up
260 * event occurred during the processing of the prcm interrupt handler
261 * (setting a bit in the corresponding PM_WKST_x register and thus
262 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
263 * this would be handled.
264 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700265static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
266{
Kevin Hilmand6290a32010-04-26 14:59:09 -0700267 u32 irqenable_mpu, irqstatus_mpu;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700268 int c = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700269
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700270 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700271 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700272 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700273 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
274 irqstatus_mpu &= irqenable_mpu;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700275
Kevin Hilmand6290a32010-04-26 14:59:09 -0700276 do {
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600277 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
278 OMAP3430_IO_ST_MASK)) {
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700279 c = _prcm_int_handle_wakeup();
280
281 /*
282 * Is the MPU PRCM interrupt handler racing with the
283 * IVA2 PRCM interrupt handler ?
284 */
285 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
286 "but no wakeup sources are marked\n");
287 } else {
288 /* XXX we need to expand our PRCM interrupt handler */
289 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
290 "no code to handle it (%08x)\n", irqstatus_mpu);
291 }
292
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700293 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
Jon Hunter77da2d92009-06-27 00:07:25 -0500294 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700295
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700296 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700297 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
298 irqstatus_mpu &= irqenable_mpu;
299
300 } while (irqstatus_mpu);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700301
302 return IRQ_HANDLED;
303}
304
Russell Kingcbe26342011-06-30 08:45:49 +0100305static void omap34xx_save_context(u32 *save)
306{
307 u32 val;
308
309 /* Read Auxiliary Control Register */
310 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
311 *save++ = 1;
312 *save++ = val;
313
314 /* Read L2 AUX ctrl register */
315 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
316 *save++ = 1;
317 *save++ = val;
318}
319
Russell King29cb3cd2011-07-02 09:54:01 +0100320static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530321{
Russell Kingcbe26342011-06-30 08:45:49 +0100322 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100323 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530324}
325
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530326void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700327{
328 /* Variable to tell what needs to be saved and restored
329 * in omap_sram_idle*/
330 /* save_state = 0 => Nothing to save and restored */
331 /* save_state = 1 => Only L1 and logic lost */
332 /* save_state = 2 => Only L2 lost */
333 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530334 int save_state = 0;
335 int mpu_next_state = PWRDM_POWER_ON;
336 int per_next_state = PWRDM_POWER_ON;
337 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700338 int per_going_off;
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530339 int core_prev_state, per_prev_state;
Tero Kristo13a6fe02008-10-13 13:17:06 +0300340 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700341
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530342 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
343 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
344 pwrdm_clear_all_prev_pwrst(core_pwrdm);
345 pwrdm_clear_all_prev_pwrst(per_pwrdm);
346
Kevin Hilman8bd22942009-05-28 10:56:16 -0700347 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
348 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530349 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700350 case PWRDM_POWER_RET:
351 /* No need to save context */
352 save_state = 0;
353 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530354 case PWRDM_POWER_OFF:
355 save_state = 3;
356 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700357 default:
358 /* Invalid state */
359 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
360 return;
361 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300362
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530363 /* NEON control */
364 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200365 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530366
Mike Chan40742fa2010-05-03 16:04:06 -0700367 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800368 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200369 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Kevin Hilmand5c47d72010-08-10 16:04:35 -0700370 if (omap3_has_io_wakeup() &&
371 (per_next_state < PWRDM_POWER_ON ||
372 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700373 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600374 if (omap3_has_io_chain_ctrl())
375 omap3_enable_io_chain();
Mike Chan40742fa2010-05-03 16:04:06 -0700376 }
377
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700378 /* Block console output in case it is on one of the OMAP UARTs */
Kevin Hilmane83df172010-12-08 22:40:40 +0000379 if (!is_suspending())
380 if (per_next_state < PWRDM_POWER_ON ||
381 core_next_state < PWRDM_POWER_ON)
Torben Hohnac751ef2011-01-25 15:07:35 -0800382 if (!console_trylock())
Kevin Hilmane83df172010-12-08 22:40:40 +0000383 goto console_still_active;
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700384
Charulatha Vff2f8e52011-09-13 18:32:37 +0530385 pwrdm_pre_transition();
386
Mike Chan40742fa2010-05-03 16:04:06 -0700387 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800388 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700389 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Kevin Hilman658ce972008-11-04 20:50:52 -0800390 omap_uart_prepare_idle(2);
Govindraj.Rcd4f1fa2010-09-27 20:20:32 +0530391 omap_uart_prepare_idle(3);
Paul Walmsley72e06d02010-12-21 21:05:16 -0700392 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700393 if (per_next_state == PWRDM_POWER_OFF)
Tero Kristoecf157d2008-12-01 13:17:29 +0200394 omap3_per_save_context();
Kevin Hilman658ce972008-11-04 20:50:52 -0800395 }
396
397 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530398 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530399 omap_uart_prepare_idle(0);
400 omap_uart_prepare_idle(1);
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530401 if (core_next_state == PWRDM_POWER_OFF) {
402 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700403 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530404 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530405 }
Mike Chan40742fa2010-05-03 16:04:06 -0700406
Tero Kristof18cc2f2009-10-23 19:03:50 +0300407 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700408
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530409 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600410 * On EMU/HS devices ROM code restores a SRDC value
411 * from scratchpad which has automatic self refresh on timeout
412 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
413 * Hence store/restore the SDRC_POWER register here.
414 */
415 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
416 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
417 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530418 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe02008-10-13 13:17:06 +0300419 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe02008-10-13 13:17:06 +0300420
421 /*
Russell King076f2cc2011-06-22 15:42:54 +0100422 * omap3_arm_context is the location where some ARM context
423 * get saved. The rest is placed on the stack, and restored
424 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530425 */
Russell Kingcbe26342011-06-30 08:45:49 +0100426 if (save_state)
427 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100428 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100429 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100430 else
431 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700432
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530433 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600434 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
435 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
436 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe02008-10-13 13:17:06 +0300437 core_next_state == PWRDM_POWER_OFF)
438 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
439
Kevin Hilman658ce972008-11-04 20:50:52 -0800440 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530441 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530442 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
443 if (core_prev_state == PWRDM_POWER_OFF) {
444 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700445 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530446 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300447 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530448 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800449 omap_uart_resume_idle(0);
450 omap_uart_resume_idle(1);
451 if (core_next_state == PWRDM_POWER_OFF)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700452 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
Kevin Hilman658ce972008-11-04 20:50:52 -0800453 OMAP3430_GR_MOD,
454 OMAP3_PRM_VOLTCTRL_OFFSET);
455 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300456 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800457
Charulatha Vff2f8e52011-09-13 18:32:37 +0530458 pwrdm_post_transition();
459
Kevin Hilman658ce972008-11-04 20:50:52 -0800460 /* PER */
461 if (per_next_state < PWRDM_POWER_ON) {
462 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
Kevin Hilman43ffcd92009-01-27 11:09:24 -0800463 omap2_gpio_resume_after_idle();
464 if (per_prev_state == PWRDM_POWER_OFF)
Kevin Hilman658ce972008-11-04 20:50:52 -0800465 omap3_per_restore_context();
Tero Kristoecf157d2008-12-01 13:17:29 +0200466 omap_uart_resume_idle(2);
Govindraj.Rcd4f1fa2010-09-27 20:20:32 +0530467 omap_uart_resume_idle(3);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530468 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300469
Kevin Hilmane83df172010-12-08 22:40:40 +0000470 if (!is_suspending())
Torben Hohnac751ef2011-01-25 15:07:35 -0800471 console_unlock();
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700472
473console_still_active:
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200474 /* Disable IO-PAD and IO-CHAIN wakeup */
Kevin Hilman58a55592010-08-16 09:21:19 +0300475 if (omap3_has_io_wakeup() &&
476 (per_next_state < PWRDM_POWER_ON ||
477 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700478 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
479 PM_WKEN);
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600480 if (omap3_has_io_chain_ctrl())
481 omap3_disable_io_chain();
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200482 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800483
Rajendra Nayak5cd19372011-02-25 16:06:48 -0700484 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700485}
486
Rajendra Nayak20b01662008-10-08 17:31:22 +0530487int omap3_can_sleep(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700488{
Kevin Hilman4af40162009-02-04 10:51:40 -0800489 if (!omap_uart_can_sleep())
490 return 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700491 return 1;
492}
493
Kevin Hilman8bd22942009-05-28 10:56:16 -0700494static void omap3_pm_idle(void)
495{
496 local_irq_disable();
497 local_fiq_disable();
498
499 if (!omap3_can_sleep())
500 goto out;
501
Tero Kristocf228542009-03-20 15:21:02 +0200502 if (omap_irq_pending() || need_resched())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700503 goto out;
504
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100505 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
506 trace_cpu_idle(1, smp_processor_id());
507
Kevin Hilman8bd22942009-05-28 10:56:16 -0700508 omap_sram_idle();
509
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100510 trace_power_end(smp_processor_id());
511 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
512
Kevin Hilman8bd22942009-05-28 10:56:16 -0700513out:
514 local_fiq_enable();
515 local_irq_enable();
516}
517
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700518#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700519static int omap3_pm_suspend(void)
520{
521 struct power_state *pwrst;
522 int state, ret = 0;
523
524 /* Read current next_pwrsts */
525 list_for_each_entry(pwrst, &pwrst_list, node)
526 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
527 /* Set ones wanted by suspend */
528 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530529 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700530 goto restore;
531 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
532 goto restore;
533 }
534
Kevin Hilman4af40162009-02-04 10:51:40 -0800535 omap_uart_prepare_suspend();
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300536 omap3_intc_suspend();
537
Kevin Hilman8bd22942009-05-28 10:56:16 -0700538 omap_sram_idle();
539
540restore:
541 /* Restore next_pwrsts */
542 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700543 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
544 if (state > pwrst->next_state) {
545 printk(KERN_INFO "Powerdomain (%s) didn't enter "
546 "target state %d\n",
547 pwrst->pwrdm->name, pwrst->next_state);
548 ret = -1;
549 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530550 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700551 }
552 if (ret)
553 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
554 else
555 printk(KERN_INFO "Successfully put all powerdomains "
556 "to target state\n");
557
558 return ret;
559}
560
Tero Kristo24662112009-03-05 16:32:23 +0200561static int omap3_pm_enter(suspend_state_t unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700562{
563 int ret = 0;
564
Tero Kristo24662112009-03-05 16:32:23 +0200565 switch (suspend_state) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700566 case PM_SUSPEND_STANDBY:
567 case PM_SUSPEND_MEM:
568 ret = omap3_pm_suspend();
569 break;
570 default:
571 ret = -EINVAL;
572 }
573
574 return ret;
575}
576
Tero Kristo24662112009-03-05 16:32:23 +0200577/* Hooks to enable / disable UART interrupts during suspend */
578static int omap3_pm_begin(suspend_state_t state)
579{
Jean Pihetc1663812010-12-09 18:39:58 +0100580 disable_hlt();
Tero Kristo24662112009-03-05 16:32:23 +0200581 suspend_state = state;
582 omap_uart_enable_irqs(0);
583 return 0;
584}
585
586static void omap3_pm_end(void)
587{
588 suspend_state = PM_SUSPEND_ON;
589 omap_uart_enable_irqs(1);
Jean Pihetc1663812010-12-09 18:39:58 +0100590 enable_hlt();
Tero Kristo24662112009-03-05 16:32:23 +0200591 return;
592}
593
Lionel Debroux2f55ac02010-11-16 14:14:02 +0100594static const struct platform_suspend_ops omap_pm_ops = {
Tero Kristo24662112009-03-05 16:32:23 +0200595 .begin = omap3_pm_begin,
596 .end = omap3_pm_end,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700597 .enter = omap3_pm_enter,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700598 .valid = suspend_valid_only_mem,
599};
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700600#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700601
Kevin Hilman1155e422008-11-25 11:48:24 -0800602
603/**
604 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
605 * retention
606 *
607 * In cases where IVA2 is activated by bootcode, it may prevent
608 * full-chip retention or off-mode because it is not idle. This
609 * function forces the IVA2 into idle state so it can go
610 * into retention/off and thus allow full-chip retention/off.
611 *
612 **/
613static void __init omap3_iva_idle(void)
614{
615 /* ensure IVA2 clock is disabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700616 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800617
618 /* if no clock activity, nothing else to do */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700619 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
Kevin Hilman1155e422008-11-25 11:48:24 -0800620 OMAP3430_CLKACTIVITY_IVA2_MASK))
621 return;
622
623 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700624 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600625 OMAP3430_RST2_IVA2_MASK |
626 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700627 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800628
629 /* Enable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700630 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
Kevin Hilman1155e422008-11-25 11:48:24 -0800631 OMAP3430_IVA2_MOD, CM_FCLKEN);
632
633 /* Set IVA2 boot mode to 'idle' */
634 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
635 OMAP343X_CONTROL_IVA2_BOOTMOD);
636
637 /* Un-reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700638 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800639
640 /* Disable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700641 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800642
643 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700644 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600645 OMAP3430_RST2_IVA2_MASK |
646 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700647 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800648}
649
Kevin Hilman8111b222009-04-28 15:27:44 -0700650static void __init omap3_d2d_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700651{
Kevin Hilman8111b222009-04-28 15:27:44 -0700652 u16 mask, padconf;
653
654 /* In a stand alone OMAP3430 where there is not a stacked
655 * modem for the D2D Idle Ack and D2D MStandby must be pulled
656 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
657 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
658 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
659 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
660 padconf |= mask;
661 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
662
663 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
664 padconf |= mask;
665 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
666
Kevin Hilman8bd22942009-05-28 10:56:16 -0700667 /* reset modem */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700668 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600669 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700670 CORE_MOD, OMAP2_RM_RSTCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700671 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman8111b222009-04-28 15:27:44 -0700672}
Kevin Hilman8bd22942009-05-28 10:56:16 -0700673
Kevin Hilman8111b222009-04-28 15:27:44 -0700674static void __init prcm_setup_regs(void)
675{
Govindraj.Re5863682010-09-27 20:20:25 +0530676 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
677 OMAP3630_EN_UART4_MASK : 0;
678 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
679 OMAP3630_GRPSEL_UART4_MASK : 0;
680
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700681 /* XXX This should be handled by hwmod code or SCM init code */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600682 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
Tero Kristob296c812009-10-23 19:03:49 +0300683
Kevin Hilman8bd22942009-05-28 10:56:16 -0700684 /*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700685 * Enable control of expternal oscillator through
686 * sys_clkreq. In the long run clock framework should
687 * take care of this.
688 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700689 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700690 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
691 OMAP3430_GR_MOD,
692 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
693
694 /* setup wakup source */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700695 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600696 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700697 WKUP_MOD, PM_WKEN);
698 /* No need to write EN_IO, that is always enabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700699 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600700 OMAP3430_GRPSEL_GPT1_MASK |
701 OMAP3430_GRPSEL_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700702 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
703 /* For some reason IO doesn't generate wakeup event even if
704 * it is selected to mpu wakeup goup */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700705 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700706 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
Kevin Hilman1155e422008-11-25 11:48:24 -0800707
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530708 /* Enable PM_WKEN to support DSS LPR */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700709 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530710 OMAP3430_DSS_MOD, PM_WKEN);
711
Kevin Hilmanb427f922009-10-22 14:48:13 -0700712 /* Enable wakeups in PER */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700713 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530714 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600715 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
716 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
717 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
718 OMAP3430_EN_MCBSP4_MASK,
Kevin Hilmanb427f922009-10-22 14:48:13 -0700719 OMAP3430_PER_MOD, PM_WKEN);
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000720 /* and allow them to wake up MPU */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700721 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530722 OMAP3430_GRPSEL_GPIO2_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600723 OMAP3430_GRPSEL_GPIO3_MASK |
724 OMAP3430_GRPSEL_GPIO4_MASK |
725 OMAP3430_GRPSEL_GPIO5_MASK |
726 OMAP3430_GRPSEL_GPIO6_MASK |
727 OMAP3430_GRPSEL_UART3_MASK |
728 OMAP3430_GRPSEL_MCBSP2_MASK |
729 OMAP3430_GRPSEL_MCBSP3_MASK |
730 OMAP3430_GRPSEL_MCBSP4_MASK,
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000731 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
732
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700733 /* Don't attach IVA interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700734 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
735 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
736 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
737 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700738
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700739 /* Clear any pending 'reset' flags */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700740 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
741 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
742 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
743 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
744 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
745 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
746 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700747
Kevin Hilman014c46d2009-04-27 07:50:23 -0700748 /* Clear any pending PRCM interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700749 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman014c46d2009-04-27 07:50:23 -0700750
Kevin Hilman1155e422008-11-25 11:48:24 -0800751 omap3_iva_idle();
Kevin Hilman8111b222009-04-28 15:27:44 -0700752 omap3_d2d_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700753}
754
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700755void omap3_pm_off_mode_enable(int enable)
756{
757 struct power_state *pwrst;
758 u32 state;
759
760 if (enable)
761 state = PWRDM_POWER_OFF;
762 else
763 state = PWRDM_POWER_RET;
764
765 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600766 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
767 pwrst->pwrdm == core_pwrdm &&
768 state == PWRDM_POWER_OFF) {
769 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200770 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600771 __func__);
772 } else {
773 pwrst->next_state = state;
774 }
775 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700776 }
777}
778
Tero Kristo68d47782008-11-26 12:26:24 +0200779int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
780{
781 struct power_state *pwrst;
782
783 list_for_each_entry(pwrst, &pwrst_list, node) {
784 if (pwrst->pwrdm == pwrdm)
785 return pwrst->next_state;
786 }
787 return -EINVAL;
788}
789
790int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
791{
792 struct power_state *pwrst;
793
794 list_for_each_entry(pwrst, &pwrst_list, node) {
795 if (pwrst->pwrdm == pwrdm) {
796 pwrst->next_state = state;
797 return 0;
798 }
799 }
800 return -EINVAL;
801}
802
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300803static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700804{
805 struct power_state *pwrst;
806
807 if (!pwrdm->pwrsts)
808 return 0;
809
Ming Leid3d381c2009-08-22 21:20:26 +0800810 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700811 if (!pwrst)
812 return -ENOMEM;
813 pwrst->pwrdm = pwrdm;
814 pwrst->next_state = PWRDM_POWER_RET;
815 list_add(&pwrst->node, &pwrst_list);
816
817 if (pwrdm_has_hdwr_sar(pwrdm))
818 pwrdm_enable_hdwr_sar(pwrdm);
819
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530820 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700821}
822
823/*
824 * Enable hw supervised mode for all clockdomains if it's
825 * supported. Initiate sleep transition for other clockdomains, if
826 * they are not used
827 */
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300828static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700829{
830 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
Rajendra Nayak5cd19372011-02-25 16:06:48 -0700831 clkdm_allow_idle(clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700832 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
833 atomic_read(&clkdm->usecount) == 0)
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700834 clkdm_sleep(clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700835 return 0;
836}
837
Jean Pihet46e130d2011-06-29 18:40:23 +0200838/*
839 * Push functions to SRAM
840 *
841 * The minimum set of functions is pushed to SRAM for execution:
842 * - omap3_do_wfi for erratum i581 WA,
843 * - save_secure_ram_context for security extensions.
844 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530845void omap_push_sram_idle(void)
846{
Jean Pihet46e130d2011-06-29 18:40:23 +0200847 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
848
Tero Kristo27d59a42008-10-13 13:15:00 +0300849 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
850 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
851 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530852}
853
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600854static void __init pm_errata_configure(void)
855{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600856 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600857 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600858 /* Enable the l2 cache toggling in sleep logic */
859 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600860 if (omap_rev() < OMAP3630_REV_ES1_2)
861 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600862 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600863}
864
Kevin Hilman7cc515f2009-06-10 09:02:25 -0700865static int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700866{
867 struct power_state *pwrst, *tmp;
Paul Walmsley55ed9692010-01-26 20:12:59 -0700868 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700869 int ret;
870
871 if (!cpu_is_omap34xx())
872 return -ENODEV;
873
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600874 if (!omap3_has_io_chain_ctrl())
875 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
876
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600877 pm_errata_configure();
878
Kevin Hilman8bd22942009-05-28 10:56:16 -0700879 /* XXX prcm_setup_regs needs to be before enabling hw
880 * supervised mode for powerdomains */
881 prcm_setup_regs();
882
883 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
884 (irq_handler_t)prcm_interrupt_handler,
885 IRQF_DISABLED, "prcm", NULL);
886 if (ret) {
887 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
888 INT_34XX_PRCM_MPU_IRQ);
889 goto err1;
890 }
891
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300892 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700893 if (ret) {
894 printk(KERN_ERR "Failed to setup powerdomains\n");
895 goto err2;
896 }
897
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300898 (void) clkdm_for_each(clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700899
900 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
901 if (mpu_pwrdm == NULL) {
902 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
903 goto err2;
904 }
905
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530906 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
907 per_pwrdm = pwrdm_lookup("per_pwrdm");
908 core_pwrdm = pwrdm_lookup("core_pwrdm");
Tero Kristoc16c3f62008-12-11 16:46:57 +0200909 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530910
Paul Walmsley55ed9692010-01-26 20:12:59 -0700911 neon_clkdm = clkdm_lookup("neon_clkdm");
912 mpu_clkdm = clkdm_lookup("mpu_clkdm");
913 per_clkdm = clkdm_lookup("per_clkdm");
914 core_clkdm = clkdm_lookup("core_clkdm");
915
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700916#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700917 suspend_set_ops(&omap_pm_ops);
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700918#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700919
920 pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300921 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700922
Nishanth Menon458e9992010-12-20 14:05:06 -0600923 /*
924 * RTA is disabled during initialization as per erratum i608
925 * it is safer to disable RTA by the bootloader, but we would like
926 * to be doubly sure here and prevent any mishaps.
927 */
928 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
929 omap3630_ctrl_disable_rta();
930
Paul Walmsley55ed9692010-01-26 20:12:59 -0700931 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300932 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
933 omap3_secure_ram_storage =
934 kmalloc(0x803F, GFP_KERNEL);
935 if (!omap3_secure_ram_storage)
936 printk(KERN_ERR "Memory allocation failed when"
937 "allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300938
Tero Kristo9d971402008-12-12 11:20:05 +0200939 local_irq_disable();
940 local_fiq_disable();
941
942 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800943 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200944 omap_dma_global_context_restore();
945
946 local_irq_enable();
947 local_fiq_enable();
948 }
949
950 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700951err1:
952 return ret;
953err2:
954 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
955 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
956 list_del(&pwrst->node);
957 kfree(pwrst);
958 }
959 return ret;
960}
961
962late_initcall(omap3_pm_init);