Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-tegra/gpio.c |
| 3 | * |
| 4 | * Copyright (c) 2010 Google, Inc |
| 5 | * |
| 6 | * Author: |
| 7 | * Erik Gilling <konkers@google.com> |
| 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and |
| 11 | * may be copied, distributed, and modified under those terms. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/irq.h> |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 23 | |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/gpio.h> |
Grant Likely | df22122 | 2011-06-15 14:54:14 -0600 | [diff] [blame] | 26 | #include <linux/of.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 27 | |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 28 | #include <asm/mach/irq.h> |
| 29 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 30 | #include <mach/iomap.h> |
Colin Cross | 2ea67fd | 2010-10-04 08:49:49 -0700 | [diff] [blame] | 31 | #include <mach/suspend.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 32 | |
| 33 | #define GPIO_BANK(x) ((x) >> 5) |
| 34 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) |
| 35 | #define GPIO_BIT(x) ((x) & 0x7) |
| 36 | |
| 37 | #define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \ |
| 38 | GPIO_BANK(x) * 0x80 + \ |
| 39 | GPIO_PORT(x) * 4) |
| 40 | |
| 41 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) |
| 42 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) |
| 43 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) |
| 44 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) |
| 45 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) |
| 46 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) |
| 47 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) |
| 48 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) |
| 49 | |
| 50 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) |
| 51 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) |
| 52 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) |
| 53 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) |
| 54 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) |
| 55 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) |
| 56 | |
| 57 | #define GPIO_INT_LVL_MASK 0x010101 |
| 58 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 |
| 59 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 |
| 60 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 |
| 61 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 |
| 62 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 |
| 63 | |
| 64 | struct tegra_gpio_bank { |
| 65 | int bank; |
| 66 | int irq; |
| 67 | spinlock_t lvl_lock[4]; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 68 | #ifdef CONFIG_PM |
| 69 | u32 cnf[4]; |
| 70 | u32 out[4]; |
| 71 | u32 oe[4]; |
| 72 | u32 int_enb[4]; |
| 73 | u32 int_lvl[4]; |
| 74 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | |
| 78 | static struct tegra_gpio_bank tegra_gpio_banks[] = { |
| 79 | {.bank = 0, .irq = INT_GPIO1}, |
| 80 | {.bank = 1, .irq = INT_GPIO2}, |
| 81 | {.bank = 2, .irq = INT_GPIO3}, |
| 82 | {.bank = 3, .irq = INT_GPIO4}, |
| 83 | {.bank = 4, .irq = INT_GPIO5}, |
| 84 | {.bank = 5, .irq = INT_GPIO6}, |
| 85 | {.bank = 6, .irq = INT_GPIO7}, |
| 86 | }; |
| 87 | |
| 88 | static int tegra_gpio_compose(int bank, int port, int bit) |
| 89 | { |
| 90 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); |
| 91 | } |
| 92 | |
| 93 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) |
| 94 | { |
| 95 | u32 val; |
| 96 | |
| 97 | val = 0x100 << GPIO_BIT(gpio); |
| 98 | if (value) |
| 99 | val |= 1 << GPIO_BIT(gpio); |
| 100 | __raw_writel(val, reg); |
| 101 | } |
| 102 | |
| 103 | void tegra_gpio_enable(int gpio) |
| 104 | { |
| 105 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); |
| 106 | } |
| 107 | |
| 108 | void tegra_gpio_disable(int gpio) |
| 109 | { |
| 110 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); |
| 111 | } |
| 112 | |
| 113 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 114 | { |
| 115 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); |
| 116 | } |
| 117 | |
| 118 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 119 | { |
| 120 | return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
| 121 | } |
| 122 | |
| 123 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 124 | { |
| 125 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 130 | int value) |
| 131 | { |
| 132 | tegra_gpio_set(chip, offset, value); |
| 133 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); |
| 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | |
| 138 | |
| 139 | static struct gpio_chip tegra_gpio_chip = { |
| 140 | .label = "tegra-gpio", |
| 141 | .direction_input = tegra_gpio_direction_input, |
| 142 | .get = tegra_gpio_get, |
| 143 | .direction_output = tegra_gpio_direction_output, |
| 144 | .set = tegra_gpio_set, |
| 145 | .base = 0, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 146 | .ngpio = TEGRA_NR_GPIOS, |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 147 | }; |
| 148 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 149 | static void tegra_gpio_irq_ack(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 150 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 151 | int gpio = d->irq - INT_GPIO_BASE; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 152 | |
| 153 | __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
| 154 | } |
| 155 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 156 | static void tegra_gpio_irq_mask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 157 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 158 | int gpio = d->irq - INT_GPIO_BASE; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 159 | |
| 160 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); |
| 161 | } |
| 162 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 163 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 164 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 165 | int gpio = d->irq - INT_GPIO_BASE; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 166 | |
| 167 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); |
| 168 | } |
| 169 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 170 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 171 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 172 | int gpio = d->irq - INT_GPIO_BASE; |
| 173 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 174 | int port = GPIO_PORT(gpio); |
| 175 | int lvl_type; |
| 176 | int val; |
| 177 | unsigned long flags; |
| 178 | |
| 179 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 180 | case IRQ_TYPE_EDGE_RISING: |
| 181 | lvl_type = GPIO_INT_LVL_EDGE_RISING; |
| 182 | break; |
| 183 | |
| 184 | case IRQ_TYPE_EDGE_FALLING: |
| 185 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; |
| 186 | break; |
| 187 | |
| 188 | case IRQ_TYPE_EDGE_BOTH: |
| 189 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; |
| 190 | break; |
| 191 | |
| 192 | case IRQ_TYPE_LEVEL_HIGH: |
| 193 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; |
| 194 | break; |
| 195 | |
| 196 | case IRQ_TYPE_LEVEL_LOW: |
| 197 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; |
| 198 | break; |
| 199 | |
| 200 | default: |
| 201 | return -EINVAL; |
| 202 | } |
| 203 | |
| 204 | spin_lock_irqsave(&bank->lvl_lock[port], flags); |
| 205 | |
| 206 | val = __raw_readl(GPIO_INT_LVL(gpio)); |
| 207 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
| 208 | val |= lvl_type << GPIO_BIT(gpio); |
| 209 | __raw_writel(val, GPIO_INT_LVL(gpio)); |
| 210 | |
| 211 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
| 212 | |
| 213 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 214 | __irq_set_handler_locked(d->irq, handle_level_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 215 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 216 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 222 | { |
| 223 | struct tegra_gpio_bank *bank; |
| 224 | int port; |
| 225 | int pin; |
| 226 | int unmasked = 0; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 227 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 228 | |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 229 | chained_irq_enter(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 230 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 231 | bank = irq_get_handler_data(irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 232 | |
| 233 | for (port = 0; port < 4; port++) { |
| 234 | int gpio = tegra_gpio_compose(bank->bank, port, 0); |
| 235 | unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) & |
| 236 | __raw_readl(GPIO_INT_ENB(gpio)); |
| 237 | u32 lvl = __raw_readl(GPIO_INT_LVL(gpio)); |
| 238 | |
| 239 | for_each_set_bit(pin, &sta, 8) { |
| 240 | __raw_writel(1 << pin, GPIO_INT_CLR(gpio)); |
| 241 | |
| 242 | /* if gpio is edge triggered, clear condition |
| 243 | * before executing the hander so that we don't |
| 244 | * miss edges |
| 245 | */ |
| 246 | if (lvl & (0x100 << pin)) { |
| 247 | unmasked = 1; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 248 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | generic_handle_irq(gpio_to_irq(gpio + pin)); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | if (!unmasked) |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 256 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 257 | |
| 258 | } |
| 259 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 260 | #ifdef CONFIG_PM |
| 261 | void tegra_gpio_resume(void) |
| 262 | { |
| 263 | unsigned long flags; |
Colin Cross | c8309ef | 2011-03-30 00:24:43 -0700 | [diff] [blame] | 264 | int b; |
| 265 | int p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 266 | |
| 267 | local_irq_save(flags); |
| 268 | |
| 269 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { |
| 270 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
| 271 | |
| 272 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
| 273 | unsigned int gpio = (b<<5) | (p<<3); |
| 274 | __raw_writel(bank->cnf[p], GPIO_CNF(gpio)); |
| 275 | __raw_writel(bank->out[p], GPIO_OUT(gpio)); |
| 276 | __raw_writel(bank->oe[p], GPIO_OE(gpio)); |
| 277 | __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); |
| 278 | __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | local_irq_restore(flags); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | void tegra_gpio_suspend(void) |
| 286 | { |
| 287 | unsigned long flags; |
Colin Cross | c8309ef | 2011-03-30 00:24:43 -0700 | [diff] [blame] | 288 | int b; |
| 289 | int p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 290 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 291 | local_irq_save(flags); |
| 292 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { |
| 293 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
| 294 | |
| 295 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
| 296 | unsigned int gpio = (b<<5) | (p<<3); |
| 297 | bank->cnf[p] = __raw_readl(GPIO_CNF(gpio)); |
| 298 | bank->out[p] = __raw_readl(GPIO_OUT(gpio)); |
| 299 | bank->oe[p] = __raw_readl(GPIO_OE(gpio)); |
| 300 | bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio)); |
| 301 | bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio)); |
| 302 | } |
| 303 | } |
| 304 | local_irq_restore(flags); |
| 305 | } |
| 306 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 307 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 308 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 309 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 310 | return irq_set_irq_wake(bank->irq, enable); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 311 | } |
| 312 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 313 | |
| 314 | static struct irq_chip tegra_gpio_irq_chip = { |
| 315 | .name = "GPIO", |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 316 | .irq_ack = tegra_gpio_irq_ack, |
| 317 | .irq_mask = tegra_gpio_irq_mask, |
| 318 | .irq_unmask = tegra_gpio_irq_unmask, |
| 319 | .irq_set_type = tegra_gpio_irq_set_type, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 320 | #ifdef CONFIG_PM |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 321 | .irq_set_wake = tegra_gpio_wake_enable, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 322 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 323 | }; |
| 324 | |
| 325 | |
| 326 | /* This lock class tells lockdep that GPIO irqs are in a different |
| 327 | * category than their parents, so it won't report false recursion. |
| 328 | */ |
| 329 | static struct lock_class_key gpio_lock_class; |
| 330 | |
| 331 | static int __init tegra_gpio_init(void) |
| 332 | { |
| 333 | struct tegra_gpio_bank *bank; |
| 334 | int i; |
| 335 | int j; |
| 336 | |
| 337 | for (i = 0; i < 7; i++) { |
| 338 | for (j = 0; j < 4; j++) { |
| 339 | int gpio = tegra_gpio_compose(i, j, 0); |
| 340 | __raw_writel(0x00, GPIO_INT_ENB(gpio)); |
| 341 | } |
| 342 | } |
| 343 | |
Grant Likely | df22122 | 2011-06-15 14:54:14 -0600 | [diff] [blame] | 344 | #ifdef CONFIG_OF_GPIO |
| 345 | /* |
| 346 | * This isn't ideal, but it gets things hooked up until this |
| 347 | * driver is converted into a platform_device |
| 348 | */ |
| 349 | tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL, |
Stephen Warren | f7f678a | 2011-07-05 14:15:18 -0600 | [diff] [blame] | 350 | "nvidia,tegra20-gpio"); |
Grant Likely | df22122 | 2011-06-15 14:54:14 -0600 | [diff] [blame] | 351 | #endif /* CONFIG_OF_GPIO */ |
| 352 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 353 | gpiochip_add(&tegra_gpio_chip); |
| 354 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 355 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 356 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; |
| 357 | |
Thomas Gleixner | 1475b85 | 2011-03-22 17:11:09 +0100 | [diff] [blame] | 358 | irq_set_lockdep_class(i, &gpio_lock_class); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 359 | irq_set_chip_data(i, bank); |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 360 | irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, |
| 361 | handle_simple_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 362 | set_irq_flags(i, IRQF_VALID); |
| 363 | } |
| 364 | |
| 365 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { |
| 366 | bank = &tegra_gpio_banks[i]; |
| 367 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 368 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
| 369 | irq_set_handler_data(bank->irq, bank); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 370 | |
| 371 | for (j = 0; j < 4; j++) |
| 372 | spin_lock_init(&bank->lvl_lock[j]); |
| 373 | } |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | postcore_initcall(tegra_gpio_init); |
| 379 | |
Olof Johansson | 632095e | 2011-02-13 19:12:27 -0800 | [diff] [blame] | 380 | void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) |
| 381 | { |
| 382 | int i; |
| 383 | |
| 384 | for (i = 0; i < num; i++) { |
| 385 | int gpio = table[i].gpio; |
| 386 | |
| 387 | if (table[i].enable) |
| 388 | tegra_gpio_enable(gpio); |
| 389 | else |
| 390 | tegra_gpio_disable(gpio); |
| 391 | } |
| 392 | } |
| 393 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 394 | #ifdef CONFIG_DEBUG_FS |
| 395 | |
| 396 | #include <linux/debugfs.h> |
| 397 | #include <linux/seq_file.h> |
| 398 | |
| 399 | static int dbg_gpio_show(struct seq_file *s, void *unused) |
| 400 | { |
| 401 | int i; |
| 402 | int j; |
| 403 | |
| 404 | for (i = 0; i < 7; i++) { |
| 405 | for (j = 0; j < 4; j++) { |
| 406 | int gpio = tegra_gpio_compose(i, j, 0); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 407 | seq_printf(s, |
| 408 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", |
| 409 | i, j, |
| 410 | __raw_readl(GPIO_CNF(gpio)), |
| 411 | __raw_readl(GPIO_OE(gpio)), |
| 412 | __raw_readl(GPIO_OUT(gpio)), |
| 413 | __raw_readl(GPIO_IN(gpio)), |
| 414 | __raw_readl(GPIO_INT_STA(gpio)), |
| 415 | __raw_readl(GPIO_INT_ENB(gpio)), |
| 416 | __raw_readl(GPIO_INT_LVL(gpio))); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 417 | } |
| 418 | } |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | static int dbg_gpio_open(struct inode *inode, struct file *file) |
| 423 | { |
| 424 | return single_open(file, dbg_gpio_show, &inode->i_private); |
| 425 | } |
| 426 | |
| 427 | static const struct file_operations debug_fops = { |
| 428 | .open = dbg_gpio_open, |
| 429 | .read = seq_read, |
| 430 | .llseek = seq_lseek, |
| 431 | .release = single_release, |
| 432 | }; |
| 433 | |
| 434 | static int __init tegra_gpio_debuginit(void) |
| 435 | { |
| 436 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, |
| 437 | NULL, NULL, &debug_fops); |
| 438 | return 0; |
| 439 | } |
| 440 | late_initcall(tegra_gpio_debuginit); |
| 441 | #endif |