| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | .text |
| 15 | |
| 16 | #ifdef CONFIG_MSM_CPU_AVS |
| 17 | .global avs_test_delays |
| 18 | avs_test_delays: |
| 19 | |
| 20 | /* Read r1=CPMR and enable Never Sleep for VSLPDLY */ |
| 21 | mrc p15, 7, r1, c15, c0, 5 |
| 22 | orr r12, r1, #3, 24 |
| 23 | mcr p15, 7, r12, c15, c0, 5 |
| 24 | |
| 25 | /* Read r2=CPACR and enable full access to CP10 and CP11 space */ |
| 26 | mrc p15, 0, r2, c1, c0, 2 |
| 27 | orr r12, r2, #(0xf << 20) |
| 28 | mcr p15, 0, r12, c1, c0, 2 |
| 29 | isb |
| 30 | |
| 31 | /* Read r3=FPEXC and or in FP enable, VFP/ASE enable = FPEXC[30]; */ |
| 32 | fmrx r3, fpexc |
| 33 | orr r12, r3, #1, 2 |
| 34 | fmxr fpexc, r12 |
| 35 | |
| 36 | /* |
| 37 | * Do floating-point operations to prime the VFP pipeline. Use |
| 38 | * fcpyd d0, d0 as a floating point nop. This avoids changing VFP |
| 39 | * state. |
| 40 | */ |
| 41 | fcpyd d0, d0 |
| 42 | fcpyd d0, d0 |
| 43 | fcpyd d0, d0 |
| 44 | |
| 45 | /* Read r0=AVSCSR to get status from CPU, VFP, and L2 ring oscillators */ |
| 46 | mrc p15, 7, r0, c15, c1, 7 |
| 47 | |
| 48 | /* Restore FPEXC */ |
| 49 | fmxr fpexc, r3 |
| 50 | |
| 51 | /* Restore CPACR */ |
| 52 | MCR p15, 0, r2, c1, c0, 2 |
| 53 | |
| 54 | /* Restore CPMR */ |
| 55 | mcr p15, 7, r1, c15, c0, 5 |
| 56 | isb |
| 57 | |
| 58 | bx lr |
| 59 | #endif |
| 60 | |
| 61 | |
| 62 | .global avs_get_avscsr |
| 63 | /* Read r0=AVSCSR to get status from CPU, VFP, and L2 ring oscillators */ |
| 64 | |
| 65 | avs_get_avscsr: |
| 66 | mrc p15, 7, r0, c15, c1, 7 |
| 67 | bx lr |
| 68 | |
| 69 | .global avs_get_avsdscr |
| 70 | /* Read r0=AVSDSCR to get the AVS Delay Synthesizer control settings */ |
| 71 | |
| 72 | avs_get_avsdscr: |
| 73 | mrc p15, 7, r0, c15, c0, 6 |
| 74 | bx lr |
| 75 | |
| 76 | |
| 77 | |
| 78 | |
| 79 | .global avs_get_tscsr |
| 80 | /* Read r0=TSCSR to get temperature sensor control and status */ |
| 81 | |
| 82 | avs_get_tscsr: |
| 83 | mrc p15, 7, r0, c15, c1, 0 |
| 84 | bx lr |
| 85 | |
| 86 | .global avs_set_tscsr |
| 87 | /* Write TSCSR=r0 to set temperature sensor control and status */ |
| 88 | |
| 89 | avs_set_tscsr: |
| 90 | mcr p15, 7, r0, c15, c1, 0 |
| 91 | bx lr |
| 92 | |
| 93 | |
| 94 | |
| 95 | |
| 96 | |
| 97 | .global avs_reset_delays |
| 98 | avs_reset_delays: |
| 99 | |
| 100 | /* AVSDSCR(dly) to program delay */ |
| 101 | mcr p15, 7, r0, c15, c0, 6 |
| 102 | |
| 103 | /* Read r0=AVSDSCR */ |
| 104 | mrc p15, 7, r0, c15, c0, 6 |
| 105 | |
| 106 | /* AVSCSR(0x61) to enable CPU, V and L2 AVS module */ |
| 107 | mov r3, #0x61 |
| 108 | mcr p15, 7, r3, c15, c1, 7 |
| 109 | |
| 110 | bx lr |
| 111 | |
| 112 | |
| 113 | |
| 114 | .global avs_disable |
| 115 | avs_disable: |
| 116 | |
| 117 | /* Clear AVSCSR */ |
| 118 | mov r0, #0 |
| 119 | |
| 120 | /* Write AVSCSR */ |
| 121 | mcr p15, 7, r0, c15, c1, 7 |
| 122 | |
| 123 | bx lr |
| 124 | |
| 125 | .end |
| 126 | |
| 127 | |