blob: 00f182d145b6737e3de5554a8e61c28d6255f208 [file] [log] [blame]
Patrick Daly985c14b2012-12-03 17:12:37 -08001/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/* Corner type vreg VDD values */
15#define LVL_NONE RPM_REGULATOR_CORNER_NONE
16#define LVL_LOW RPM_REGULATOR_CORNER_SVS_SOC
17#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
18#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
19
Patrick Daly66e32aa2013-05-30 15:11:52 -070020#define NUM_SPEED_BIN 8
21
Patrick Daly985c14b2012-12-03 17:12:37 -080022enum clk_src {
23 CXO,
24 PLL0,
25 ACPUPLL,
26 NUM_SRC,
27};
28
29struct src_clock {
30 struct clk *clk;
31 const char *name;
32};
33
34struct clkctl_acpu_speed {
35 bool use_for_scaling;
36 unsigned int khz;
37 int src;
38 unsigned int src_sel;
39 unsigned int src_div;
40 unsigned int vdd_cpu;
41 unsigned int vdd_mem;
42 unsigned int bw_level;
43};
44
45struct acpuclk_reg_data {
46 u32 cfg_src_mask;
47 u32 cfg_src_shift;
48 u32 cfg_div_mask;
49 u32 cfg_div_shift;
50 u32 update_mask;
51 u32 poll_mask;
52};
53
54struct acpuclk_drv_data {
55 struct mutex lock;
56 struct clkctl_acpu_speed *freq_tbl;
Patrick Daly66e32aa2013-05-30 15:11:52 -070057 struct clkctl_acpu_speed **pvs_tables;
58 void __iomem *pte_efuse_base;
Patrick Daly985c14b2012-12-03 17:12:37 -080059 struct clkctl_acpu_speed *current_speed;
60 struct msm_bus_scale_pdata *bus_scale;
61 void __iomem *apcs_rcg_config;
62 void __iomem *apcs_rcg_cmd;
63 void __iomem *apcs_cpu_pwr_ctl;
64 struct regulator *vdd_cpu;
65 unsigned long vdd_max_cpu;
66 struct regulator *vdd_mem;
67 unsigned long vdd_max_mem;
68 struct src_clock src_clocks[NUM_SRC];
69 struct acpuclk_reg_data reg_data;
Patrick Dalyaf8808e2013-03-20 12:57:00 -070070 unsigned long power_collapse_khz;
71 unsigned long wait_for_irq_khz;
Patrick Daly985c14b2012-12-03 17:12:37 -080072};
73
Patrick Daly66e32aa2013-05-30 15:11:52 -070074struct bin_info {
75 bool speed_valid;
76 int speed;
77};
78
Patrick Daly985c14b2012-12-03 17:12:37 -080079/* Instantaneous bandwidth requests in MB/s. */
80#define BW_MBPS(_bw) \
81 { \
82 .vectors = &(struct msm_bus_vectors){ \
83 .src = MSM_BUS_MASTER_AMPSS_M0, \
84 .dst = MSM_BUS_SLAVE_EBI_CH0, \
85 .ib = (_bw) * 1000000ULL, \
86 .ab = 0, \
87 }, \
88 .num_paths = 1, \
89 }
90
91int __init acpuclk_cortex_init(struct platform_device *pdev,
92 struct acpuclk_drv_data *data);
93