Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * DA8XX/OMAP L1XX platform device data |
| 3 | * |
| 4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> |
| 5 | * Derived from code that was: |
| 6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 13 | #include <linux/init.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/dma-mapping.h> |
| 16 | #include <linux/serial_8250.h> |
| 17 | |
| 18 | #include <mach/cputype.h> |
| 19 | #include <mach/common.h> |
| 20 | #include <mach/time.h> |
| 21 | #include <mach/da8xx.h> |
Sekhar Nori | 1960e69 | 2009-10-22 15:12:14 +0530 | [diff] [blame] | 22 | #include <mach/cpuidle.h> |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 23 | |
| 24 | #include "clock.h" |
| 25 | |
| 26 | #define DA8XX_TPCC_BASE 0x01c00000 |
| 27 | #define DA8XX_TPTC0_BASE 0x01c08000 |
| 28 | #define DA8XX_TPTC1_BASE 0x01c08400 |
| 29 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ |
| 30 | #define DA8XX_I2C0_BASE 0x01c22000 |
Mark A. Greer | c51df70 | 2009-09-15 18:15:54 -0700 | [diff] [blame] | 31 | #define DA8XX_RTC_BASE 0x01C23000 |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 32 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 |
| 33 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 |
| 34 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 |
| 35 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 |
| 36 | #define DA8XX_GPIO_BASE 0x01e26000 |
| 37 | #define DA8XX_I2C1_BASE 0x01e28000 |
| 38 | |
| 39 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 |
| 40 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 |
| 41 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 |
| 42 | #define DA8XX_MDIO_REG_OFFSET 0x4000 |
| 43 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K |
| 44 | |
Sekhar Nori | 6a28ade | 2009-08-31 15:47:59 +0530 | [diff] [blame] | 45 | void __iomem *da8xx_syscfg_base; |
| 46 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 47 | static struct plat_serial8250_port da8xx_serial_pdata[] = { |
| 48 | { |
| 49 | .mapbase = DA8XX_UART0_BASE, |
| 50 | .irq = IRQ_DA8XX_UARTINT0, |
| 51 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| 52 | UPF_IOREMAP, |
| 53 | .iotype = UPIO_MEM, |
| 54 | .regshift = 2, |
| 55 | }, |
| 56 | { |
| 57 | .mapbase = DA8XX_UART1_BASE, |
| 58 | .irq = IRQ_DA8XX_UARTINT1, |
| 59 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| 60 | UPF_IOREMAP, |
| 61 | .iotype = UPIO_MEM, |
| 62 | .regshift = 2, |
| 63 | }, |
| 64 | { |
| 65 | .mapbase = DA8XX_UART2_BASE, |
| 66 | .irq = IRQ_DA8XX_UARTINT2, |
| 67 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| 68 | UPF_IOREMAP, |
| 69 | .iotype = UPIO_MEM, |
| 70 | .regshift = 2, |
| 71 | }, |
| 72 | { |
| 73 | .flags = 0, |
| 74 | }, |
| 75 | }; |
| 76 | |
| 77 | struct platform_device da8xx_serial_device = { |
| 78 | .name = "serial8250", |
| 79 | .id = PLAT8250_DEV_PLATFORM, |
| 80 | .dev = { |
| 81 | .platform_data = da8xx_serial_pdata, |
| 82 | }, |
| 83 | }; |
| 84 | |
| 85 | static const s8 da8xx_dma_chan_no_event[] = { |
| 86 | 20, 21, |
| 87 | -1 |
| 88 | }; |
| 89 | |
| 90 | static const s8 da8xx_queue_tc_mapping[][2] = { |
| 91 | /* {event queue no, TC no} */ |
| 92 | {0, 0}, |
| 93 | {1, 1}, |
| 94 | {-1, -1} |
| 95 | }; |
| 96 | |
| 97 | static const s8 da8xx_queue_priority_mapping[][2] = { |
| 98 | /* {event queue no, Priority} */ |
| 99 | {0, 3}, |
| 100 | {1, 7}, |
| 101 | {-1, -1} |
| 102 | }; |
| 103 | |
| 104 | static struct edma_soc_info da8xx_edma_info[] = { |
| 105 | { |
| 106 | .n_channel = 32, |
| 107 | .n_region = 4, |
| 108 | .n_slot = 128, |
| 109 | .n_tc = 2, |
| 110 | .n_cc = 1, |
| 111 | .noevent = da8xx_dma_chan_no_event, |
| 112 | .queue_tc_mapping = da8xx_queue_tc_mapping, |
| 113 | .queue_priority_mapping = da8xx_queue_priority_mapping, |
| 114 | }, |
| 115 | }; |
| 116 | |
| 117 | static struct resource da8xx_edma_resources[] = { |
| 118 | { |
| 119 | .name = "edma_cc0", |
| 120 | .start = DA8XX_TPCC_BASE, |
| 121 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, |
| 122 | .flags = IORESOURCE_MEM, |
| 123 | }, |
| 124 | { |
| 125 | .name = "edma_tc0", |
| 126 | .start = DA8XX_TPTC0_BASE, |
| 127 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, |
| 128 | .flags = IORESOURCE_MEM, |
| 129 | }, |
| 130 | { |
| 131 | .name = "edma_tc1", |
| 132 | .start = DA8XX_TPTC1_BASE, |
| 133 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, |
| 134 | .flags = IORESOURCE_MEM, |
| 135 | }, |
| 136 | { |
| 137 | .name = "edma0", |
Sudhakar Rajashekhara | 2259bbd | 2009-07-10 06:28:52 -0400 | [diff] [blame] | 138 | .start = IRQ_DA8XX_CCINT0, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 139 | .flags = IORESOURCE_IRQ, |
| 140 | }, |
| 141 | { |
| 142 | .name = "edma0_err", |
| 143 | .start = IRQ_DA8XX_CCERRINT, |
| 144 | .flags = IORESOURCE_IRQ, |
| 145 | }, |
| 146 | }; |
| 147 | |
| 148 | static struct platform_device da8xx_edma_device = { |
| 149 | .name = "edma", |
| 150 | .id = -1, |
| 151 | .dev = { |
| 152 | .platform_data = da8xx_edma_info, |
| 153 | }, |
| 154 | .num_resources = ARRAY_SIZE(da8xx_edma_resources), |
| 155 | .resource = da8xx_edma_resources, |
| 156 | }; |
| 157 | |
| 158 | int __init da8xx_register_edma(void) |
| 159 | { |
| 160 | return platform_device_register(&da8xx_edma_device); |
| 161 | } |
| 162 | |
| 163 | static struct resource da8xx_i2c_resources0[] = { |
| 164 | { |
| 165 | .start = DA8XX_I2C0_BASE, |
| 166 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, |
| 167 | .flags = IORESOURCE_MEM, |
| 168 | }, |
| 169 | { |
| 170 | .start = IRQ_DA8XX_I2CINT0, |
| 171 | .end = IRQ_DA8XX_I2CINT0, |
| 172 | .flags = IORESOURCE_IRQ, |
| 173 | }, |
| 174 | }; |
| 175 | |
| 176 | static struct platform_device da8xx_i2c_device0 = { |
| 177 | .name = "i2c_davinci", |
| 178 | .id = 1, |
| 179 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), |
| 180 | .resource = da8xx_i2c_resources0, |
| 181 | }; |
| 182 | |
| 183 | static struct resource da8xx_i2c_resources1[] = { |
| 184 | { |
| 185 | .start = DA8XX_I2C1_BASE, |
| 186 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, |
| 187 | .flags = IORESOURCE_MEM, |
| 188 | }, |
| 189 | { |
| 190 | .start = IRQ_DA8XX_I2CINT1, |
| 191 | .end = IRQ_DA8XX_I2CINT1, |
| 192 | .flags = IORESOURCE_IRQ, |
| 193 | }, |
| 194 | }; |
| 195 | |
| 196 | static struct platform_device da8xx_i2c_device1 = { |
| 197 | .name = "i2c_davinci", |
| 198 | .id = 2, |
| 199 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), |
| 200 | .resource = da8xx_i2c_resources1, |
| 201 | }; |
| 202 | |
| 203 | int __init da8xx_register_i2c(int instance, |
| 204 | struct davinci_i2c_platform_data *pdata) |
| 205 | { |
| 206 | struct platform_device *pdev; |
| 207 | |
| 208 | if (instance == 0) |
| 209 | pdev = &da8xx_i2c_device0; |
| 210 | else if (instance == 1) |
| 211 | pdev = &da8xx_i2c_device1; |
| 212 | else |
| 213 | return -EINVAL; |
| 214 | |
| 215 | pdev->dev.platform_data = pdata; |
| 216 | return platform_device_register(pdev); |
| 217 | } |
| 218 | |
| 219 | static struct resource da8xx_watchdog_resources[] = { |
| 220 | { |
| 221 | .start = DA8XX_WDOG_BASE, |
| 222 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, |
| 223 | .flags = IORESOURCE_MEM, |
| 224 | }, |
| 225 | }; |
| 226 | |
| 227 | struct platform_device davinci_wdt_device = { |
| 228 | .name = "watchdog", |
| 229 | .id = -1, |
| 230 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), |
| 231 | .resource = da8xx_watchdog_resources, |
| 232 | }; |
| 233 | |
| 234 | int __init da8xx_register_watchdog(void) |
| 235 | { |
| 236 | return platform_device_register(&davinci_wdt_device); |
| 237 | } |
| 238 | |
| 239 | static struct resource da8xx_emac_resources[] = { |
| 240 | { |
| 241 | .start = DA8XX_EMAC_CPPI_PORT_BASE, |
| 242 | .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, |
| 243 | .flags = IORESOURCE_MEM, |
| 244 | }, |
| 245 | { |
| 246 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, |
| 247 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, |
| 248 | .flags = IORESOURCE_IRQ, |
| 249 | }, |
| 250 | { |
| 251 | .start = IRQ_DA8XX_C0_RX_PULSE, |
| 252 | .end = IRQ_DA8XX_C0_RX_PULSE, |
| 253 | .flags = IORESOURCE_IRQ, |
| 254 | }, |
| 255 | { |
| 256 | .start = IRQ_DA8XX_C0_TX_PULSE, |
| 257 | .end = IRQ_DA8XX_C0_TX_PULSE, |
| 258 | .flags = IORESOURCE_IRQ, |
| 259 | }, |
| 260 | { |
| 261 | .start = IRQ_DA8XX_C0_MISC_PULSE, |
| 262 | .end = IRQ_DA8XX_C0_MISC_PULSE, |
| 263 | .flags = IORESOURCE_IRQ, |
| 264 | }, |
| 265 | }; |
| 266 | |
| 267 | struct emac_platform_data da8xx_emac_pdata = { |
| 268 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, |
| 269 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, |
| 270 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, |
| 271 | .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, |
| 272 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, |
| 273 | .version = EMAC_VERSION_2, |
| 274 | }; |
| 275 | |
| 276 | static struct platform_device da8xx_emac_device = { |
| 277 | .name = "davinci_emac", |
| 278 | .id = 1, |
| 279 | .dev = { |
| 280 | .platform_data = &da8xx_emac_pdata, |
| 281 | }, |
| 282 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), |
| 283 | .resource = da8xx_emac_resources, |
| 284 | }; |
| 285 | |
Mark A. Greer | 31f53cf | 2009-08-28 15:02:54 -0700 | [diff] [blame] | 286 | int __init da8xx_register_emac(void) |
| 287 | { |
| 288 | return platform_device_register(&da8xx_emac_device); |
| 289 | } |
| 290 | |
Chaithrika U S | e33ef5e | 2009-08-11 17:01:59 -0400 | [diff] [blame] | 291 | static struct resource da830_mcasp1_resources[] = { |
| 292 | { |
| 293 | .name = "mcasp1", |
| 294 | .start = DAVINCI_DA830_MCASP1_REG_BASE, |
| 295 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, |
| 296 | .flags = IORESOURCE_MEM, |
| 297 | }, |
| 298 | /* TX event */ |
| 299 | { |
| 300 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, |
| 301 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, |
| 302 | .flags = IORESOURCE_DMA, |
| 303 | }, |
| 304 | /* RX event */ |
| 305 | { |
| 306 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, |
| 307 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, |
| 308 | .flags = IORESOURCE_DMA, |
| 309 | }, |
| 310 | }; |
| 311 | |
| 312 | static struct platform_device da830_mcasp1_device = { |
| 313 | .name = "davinci-mcasp", |
| 314 | .id = 1, |
| 315 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), |
| 316 | .resource = da830_mcasp1_resources, |
| 317 | }; |
| 318 | |
Chaithrika U S | 491214e | 2009-08-11 17:03:25 -0400 | [diff] [blame] | 319 | static struct resource da850_mcasp_resources[] = { |
| 320 | { |
| 321 | .name = "mcasp", |
| 322 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, |
| 323 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, |
| 324 | .flags = IORESOURCE_MEM, |
| 325 | }, |
| 326 | /* TX event */ |
| 327 | { |
| 328 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, |
| 329 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, |
| 330 | .flags = IORESOURCE_DMA, |
| 331 | }, |
| 332 | /* RX event */ |
| 333 | { |
| 334 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, |
| 335 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, |
| 336 | .flags = IORESOURCE_DMA, |
| 337 | }, |
| 338 | }; |
| 339 | |
| 340 | static struct platform_device da850_mcasp_device = { |
| 341 | .name = "davinci-mcasp", |
| 342 | .id = 0, |
| 343 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), |
| 344 | .resource = da850_mcasp_resources, |
| 345 | }; |
| 346 | |
Mark A. Greer | b8864aa | 2009-08-28 15:05:02 -0700 | [diff] [blame] | 347 | void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) |
Chaithrika U S | e33ef5e | 2009-08-11 17:01:59 -0400 | [diff] [blame] | 348 | { |
Chaithrika U S | 491214e | 2009-08-11 17:03:25 -0400 | [diff] [blame] | 349 | /* DA830/OMAP-L137 has 3 instances of McASP */ |
| 350 | if (cpu_is_davinci_da830() && id == 1) { |
Chaithrika U S | e33ef5e | 2009-08-11 17:01:59 -0400 | [diff] [blame] | 351 | da830_mcasp1_device.dev.platform_data = pdata; |
| 352 | platform_device_register(&da830_mcasp1_device); |
Chaithrika U S | 491214e | 2009-08-11 17:03:25 -0400 | [diff] [blame] | 353 | } else if (cpu_is_davinci_da850()) { |
| 354 | da850_mcasp_device.dev.platform_data = pdata; |
| 355 | platform_device_register(&da850_mcasp_device); |
Chaithrika U S | e33ef5e | 2009-08-11 17:01:59 -0400 | [diff] [blame] | 356 | } |
| 357 | } |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 358 | |
| 359 | static const struct display_panel disp_panel = { |
| 360 | QVGA, |
| 361 | 16, |
| 362 | 16, |
| 363 | COLOR_ACTIVE, |
| 364 | }; |
| 365 | |
| 366 | static struct lcd_ctrl_config lcd_cfg = { |
| 367 | &disp_panel, |
| 368 | .ac_bias = 255, |
| 369 | .ac_bias_intrpt = 0, |
| 370 | .dma_burst_sz = 16, |
| 371 | .bpp = 16, |
| 372 | .fdd = 255, |
| 373 | .tft_alt_mode = 0, |
| 374 | .stn_565_mode = 0, |
| 375 | .mono_8bit_mode = 0, |
| 376 | .invert_line_clock = 1, |
| 377 | .invert_frm_clock = 1, |
| 378 | .sync_edge = 0, |
| 379 | .sync_ctrl = 1, |
| 380 | .raster_order = 0, |
| 381 | }; |
| 382 | |
Mark A. Greer | b9e6342 | 2009-09-15 18:14:19 -0700 | [diff] [blame] | 383 | struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { |
| 384 | .manu_name = "sharp", |
| 385 | .controller_data = &lcd_cfg, |
| 386 | .type = "Sharp_LCD035Q3DG01", |
| 387 | }; |
| 388 | |
| 389 | struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { |
| 390 | .manu_name = "sharp", |
| 391 | .controller_data = &lcd_cfg, |
| 392 | .type = "Sharp_LK043T1DG01", |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | static struct resource da8xx_lcdc_resources[] = { |
| 396 | [0] = { /* registers */ |
| 397 | .start = DA8XX_LCD_CNTRL_BASE, |
| 398 | .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, |
| 399 | .flags = IORESOURCE_MEM, |
| 400 | }, |
| 401 | [1] = { /* interrupt */ |
| 402 | .start = IRQ_DA8XX_LCDINT, |
| 403 | .end = IRQ_DA8XX_LCDINT, |
| 404 | .flags = IORESOURCE_IRQ, |
| 405 | }, |
| 406 | }; |
| 407 | |
Mark A. Greer | b9e6342 | 2009-09-15 18:14:19 -0700 | [diff] [blame] | 408 | static struct platform_device da8xx_lcdc_device = { |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 409 | .name = "da8xx_lcdc", |
| 410 | .id = 0, |
| 411 | .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), |
| 412 | .resource = da8xx_lcdc_resources, |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 413 | }; |
| 414 | |
Mark A. Greer | b9e6342 | 2009-09-15 18:14:19 -0700 | [diff] [blame] | 415 | int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 416 | { |
Mark A. Greer | b9e6342 | 2009-09-15 18:14:19 -0700 | [diff] [blame] | 417 | da8xx_lcdc_device.dev.platform_data = pdata; |
| 418 | return platform_device_register(&da8xx_lcdc_device); |
Sudhakar Rajashekhara | 5cbdf27 | 2009-08-13 14:33:14 -0400 | [diff] [blame] | 419 | } |
Sudhakar Rajashekhara | 700691f | 2009-08-13 15:16:23 -0400 | [diff] [blame] | 420 | |
| 421 | static struct resource da8xx_mmcsd0_resources[] = { |
| 422 | { /* registers */ |
| 423 | .start = DA8XX_MMCSD0_BASE, |
| 424 | .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, |
| 425 | .flags = IORESOURCE_MEM, |
| 426 | }, |
| 427 | { /* interrupt */ |
| 428 | .start = IRQ_DA8XX_MMCSDINT0, |
| 429 | .end = IRQ_DA8XX_MMCSDINT0, |
| 430 | .flags = IORESOURCE_IRQ, |
| 431 | }, |
| 432 | { /* DMA RX */ |
| 433 | .start = EDMA_CTLR_CHAN(0, 16), |
| 434 | .end = EDMA_CTLR_CHAN(0, 16), |
| 435 | .flags = IORESOURCE_DMA, |
| 436 | }, |
| 437 | { /* DMA TX */ |
| 438 | .start = EDMA_CTLR_CHAN(0, 17), |
| 439 | .end = EDMA_CTLR_CHAN(0, 17), |
| 440 | .flags = IORESOURCE_DMA, |
| 441 | }, |
| 442 | }; |
| 443 | |
| 444 | static struct platform_device da8xx_mmcsd0_device = { |
| 445 | .name = "davinci_mmc", |
| 446 | .id = 0, |
| 447 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), |
| 448 | .resource = da8xx_mmcsd0_resources, |
| 449 | }; |
| 450 | |
| 451 | int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) |
| 452 | { |
| 453 | da8xx_mmcsd0_device.dev.platform_data = config; |
| 454 | return platform_device_register(&da8xx_mmcsd0_device); |
| 455 | } |
Mark A. Greer | c51df70 | 2009-09-15 18:15:54 -0700 | [diff] [blame] | 456 | |
| 457 | static struct resource da8xx_rtc_resources[] = { |
| 458 | { |
| 459 | .start = DA8XX_RTC_BASE, |
| 460 | .end = DA8XX_RTC_BASE + SZ_4K - 1, |
| 461 | .flags = IORESOURCE_MEM, |
| 462 | }, |
| 463 | { /* timer irq */ |
| 464 | .start = IRQ_DA8XX_RTC, |
| 465 | .end = IRQ_DA8XX_RTC, |
| 466 | .flags = IORESOURCE_IRQ, |
| 467 | }, |
| 468 | { /* alarm irq */ |
| 469 | .start = IRQ_DA8XX_RTC, |
| 470 | .end = IRQ_DA8XX_RTC, |
| 471 | .flags = IORESOURCE_IRQ, |
| 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static struct platform_device da8xx_rtc_device = { |
| 476 | .name = "omap_rtc", |
| 477 | .id = -1, |
| 478 | .num_resources = ARRAY_SIZE(da8xx_rtc_resources), |
| 479 | .resource = da8xx_rtc_resources, |
| 480 | }; |
| 481 | |
| 482 | int da8xx_register_rtc(void) |
| 483 | { |
Sekhar Nori | 75c99bb | 2009-11-16 17:21:31 +0530 | [diff] [blame] | 484 | int ret; |
| 485 | |
Mark A. Greer | c51df70 | 2009-09-15 18:15:54 -0700 | [diff] [blame] | 486 | /* Unlock the rtc's registers */ |
| 487 | __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c)); |
| 488 | __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70)); |
| 489 | |
Sekhar Nori | 75c99bb | 2009-11-16 17:21:31 +0530 | [diff] [blame] | 490 | ret = platform_device_register(&da8xx_rtc_device); |
| 491 | if (!ret) |
| 492 | /* Atleast on DA850, RTC is a wakeup source */ |
| 493 | device_init_wakeup(&da8xx_rtc_device.dev, true); |
| 494 | |
| 495 | return ret; |
Mark A. Greer | c51df70 | 2009-09-15 18:15:54 -0700 | [diff] [blame] | 496 | } |
Sekhar Nori | 1960e69 | 2009-10-22 15:12:14 +0530 | [diff] [blame] | 497 | |
| 498 | static struct resource da8xx_cpuidle_resources[] = { |
| 499 | { |
| 500 | .start = DA8XX_DDR2_CTL_BASE, |
| 501 | .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, |
| 502 | .flags = IORESOURCE_MEM, |
| 503 | }, |
| 504 | }; |
| 505 | |
| 506 | /* DA8XX devices support DDR2 power down */ |
| 507 | static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { |
| 508 | .ddr2_pdown = 1, |
| 509 | }; |
| 510 | |
| 511 | |
| 512 | static struct platform_device da8xx_cpuidle_device = { |
| 513 | .name = "cpuidle-davinci", |
| 514 | .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), |
| 515 | .resource = da8xx_cpuidle_resources, |
| 516 | .dev = { |
| 517 | .platform_data = &da8xx_cpuidle_pdata, |
| 518 | }, |
| 519 | }; |
| 520 | |
| 521 | int __init da8xx_register_cpuidle(void) |
| 522 | { |
| 523 | return platform_device_register(&da8xx_cpuidle_device); |
| 524 | } |
| 525 | |