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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
8 *
9 * Setup file for JMR3927.
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 ***********************************************************************
34 */
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/kdev_t.h>
39#include <linux/types.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/ide.h>
Ralf Baechle046f8f72006-07-09 20:49:41 +010043#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <linux/ioport.h>
45#include <linux/param.h> /* for HZ */
46#include <linux/delay.h>
Ralf Baechlefcdb27a2006-01-18 17:37:07 +000047#include <linux/pm.h>
Ralf Baechle5eaf7a22005-03-04 17:24:32 +000048#ifdef CONFIG_SERIAL_TXX9
49#include <linux/tty.h>
50#include <linux/serial.h>
51#include <linux/serial_core.h>
52#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54#include <asm/addrspace.h>
55#include <asm/time.h>
56#include <asm/bcache.h>
57#include <asm/irq.h>
58#include <asm/reboot.h>
59#include <asm/gdb-stub.h>
60#include <asm/jmr3927/jmr3927.h>
61#include <asm/mipsregs.h>
62#include <asm/traps.h>
63
Ralf Baechle380b9252005-11-19 21:51:56 +000064extern void puts(unsigned char *cp);
65
Linus Torvalds1da177e2005-04-16 15:20:36 -070066/* Tick Timer divider */
67#define JMR3927_TIMER_CCD 0 /* 1/2 */
68#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
69
70unsigned char led_state = 0xf;
71
72struct {
73 struct resource ram0;
74 struct resource ram1;
75 struct resource pcimem;
76 struct resource iob;
77 struct resource ioc;
78 struct resource pciio;
79 struct resource jmy1394;
80 struct resource rom1;
81 struct resource rom0;
82 struct resource sio0;
83 struct resource sio1;
84} jmr3927_resources = {
Ralf Baechle5e46c3a2006-06-04 15:14:05 -070085 {
86 .start = 0,
87 .end = 0x01FFFFFF,
88 .name = "RAM0",
89 .flags = IORESOURCE_MEM
90 }, {
91 .start = 0x02000000,
92 .end = 0x03FFFFFF,
93 .name = "RAM1",
94 .flags = IORESOURCE_MEM
95 }, {
96 .start = 0x08000000,
97 .end = 0x07FFFFFF,
98 .name = "PCIMEM",
99 .flags = IORESOURCE_MEM
100 }, {
101 .start = 0x10000000,
102 .end = 0x13FFFFFF,
103 .name = "IOB"
104 }, {
105 .start = 0x14000000,
106 .end = 0x14FFFFFF,
107 .name = "IOC"
108 }, {
109 .start = 0x15000000,
110 .end = 0x15FFFFFF,
111 .name = "PCIIO"
112 }, {
113 .start = 0x1D000000,
114 .end = 0x1D3FFFFF,
115 .name = "JMY1394"
116 }, {
117 .start = 0x1E000000,
118 .end = 0x1E3FFFFF,
119 .name = "ROM1"
120 }, {
121 .start = 0x1FC00000,
122 .end = 0x1FFFFFFF,
123 .name = "ROM0"
124 }, {
125 .start = 0xFFFEF300,
126 .end = 0xFFFEF3FF,
127 .name = "SIO0"
128 }, {
129 .start = 0xFFFEF400,
130 .end = 0xFFFEF4FF,
131 .name = "SIO1"
132 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133};
134
135/* don't enable - see errata */
136int jmr3927_ccfg_toeon = 0;
137
138static inline void do_reset(void)
139{
140#ifdef CONFIG_TC35815
141 extern void tc35815_killall(void);
142 tc35815_killall();
143#endif
144#if 1 /* Resetting PCI bus */
145 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
146 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
147 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
148 mdelay(1);
149 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
150#endif
151 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
152}
153
154static void jmr3927_machine_restart(char *command)
155{
156 local_irq_disable();
157 puts("Rebooting...");
158 do_reset();
159}
160
161static void jmr3927_machine_halt(void)
162{
163 puts("JMR-TX3927 halted.\n");
164 while (1);
165}
166
167static void jmr3927_machine_power_off(void)
168{
169 puts("JMR-TX3927 halted. Please turn off the power.\n");
170 while (1);
171}
172
Atsushi Nemoto00598562006-11-12 00:10:28 +0900173static cycle_t jmr3927_hpt_read(void)
Atsushi Nemoto16b7b2a2006-10-24 00:21:27 +0900174{
175 /* We assume this function is called xtime_lock held. */
176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
177}
178
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179#define USE_RTC_DS1742
180#ifdef USE_RTC_DS1742
181extern void rtc_ds1742_init(unsigned long base);
182#endif
183static void __init jmr3927_time_init(void)
184{
Atsushi Nemoto00598562006-11-12 00:10:28 +0900185 clocksource_mips.read = jmr3927_hpt_read;
Atsushi Nemoto16b7b2a2006-10-24 00:21:27 +0900186 mips_hpt_frequency = JMR3927_TIMER_CLK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187#ifdef USE_RTC_DS1742
188 if (jmr3927_have_nvram()) {
189 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
190 }
191#endif
192}
193
Ralf Baechle54d0a212006-07-09 21:38:56 +0100194void __init plat_timer_setup(struct irqaction *irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
197 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
198 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
199 jmr3927_tmrptr->tcr =
200 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
201
202 setup_irq(JMR3927_IRQ_TICK, irq);
203}
204
205#define USECS_PER_JIFFY (1000000/HZ)
206
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207//#undef DO_WRITE_THROUGH
208#define DO_WRITE_THROUGH
209#define DO_ENABLE_CACHE
210
211extern char * __init prom_getcmdline(void);
212static void jmr3927_board_init(void);
213extern struct resource pci_io_resource;
214extern struct resource pci_mem_resource;
215
Ralf Baechle2925aba2006-06-18 01:32:22 +0100216void __init plat_mem_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217{
218 char *argptr;
219
220 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
221
222 board_time_init = jmr3927_time_init;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
224 _machine_restart = jmr3927_machine_restart;
225 _machine_halt = jmr3927_machine_halt;
Ralf Baechlefcdb27a2006-01-18 17:37:07 +0000226 pm_power_off = jmr3927_machine_power_off;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227
228 /*
229 * IO/MEM resources.
230 */
231 ioport_resource.start = pci_io_resource.start;
232 ioport_resource.end = pci_io_resource.end;
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000233 iomem_resource.start = 0;
234 iomem_resource.end = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
236 /* Reboot on panic */
237 panic_timeout = 180;
238
239 {
240 unsigned int conf;
241 conf = read_c0_conf();
242 }
243
244#if 1
245 /* cache setup */
246 {
247 unsigned int conf;
248#ifdef DO_ENABLE_CACHE
249 int mips_ic_disable = 0, mips_dc_disable = 0;
250#else
251 int mips_ic_disable = 1, mips_dc_disable = 1;
252#endif
253#ifdef DO_WRITE_THROUGH
254 int mips_config_cwfon = 0;
255 int mips_config_wbon = 0;
256#else
257 int mips_config_cwfon = 1;
258 int mips_config_wbon = 1;
259#endif
260
261 conf = read_c0_conf();
262 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
263 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
264 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
265 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
266 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
267
268 write_c0_conf(conf);
269 write_c0_cache(0);
270 }
271#endif
272
273 /* initialize board */
274 jmr3927_board_init();
275
276 argptr = prom_getcmdline();
277
278 if ((argptr = strstr(argptr, "toeon")) != NULL) {
279 jmr3927_ccfg_toeon = 1;
280 }
281 argptr = prom_getcmdline();
282 if ((argptr = strstr(argptr, "ip=")) == NULL) {
283 argptr = prom_getcmdline();
284 strcat(argptr, " ip=bootp");
285 }
286
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000287#ifdef CONFIG_SERIAL_TXX9
288 {
289 extern int early_serial_txx9_setup(struct uart_port *port);
290 int i;
291 struct uart_port req;
292 for(i = 0; i < 2; i++) {
293 memset(&req, 0, sizeof(req));
294 req.line = i;
295 req.iotype = UPIO_MEM;
296 req.membase = (char *)TX3927_SIO_REG(i);
297 req.mapbase = TX3927_SIO_REG(i);
298 req.irq = i == 0 ?
299 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
300 if (i == 0)
301 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
302 req.uartclk = JMR3927_IMCLK;
303 early_serial_txx9_setup(&req);
304 }
305 }
306#ifdef CONFIG_SERIAL_TXX9_CONSOLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 argptr = prom_getcmdline();
308 if ((argptr = strstr(argptr, "console=")) == NULL) {
309 argptr = prom_getcmdline();
310 strcat(argptr, " console=ttyS1,115200");
311 }
312#endif
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000313#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314}
315
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316static void tx3927_setup(void);
317
318#ifdef CONFIG_PCI
319unsigned long mips_pci_io_base;
320unsigned long mips_pci_io_size;
321unsigned long mips_pci_mem_base;
322unsigned long mips_pci_mem_size;
323/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
324unsigned long mips_pci_io_pciaddr = 0;
325#endif
326
327static void __init jmr3927_board_init(void)
328{
329 char *argptr;
330
331#ifdef CONFIG_PCI
332 mips_pci_io_base = JMR3927_PCIIO;
333 mips_pci_io_size = JMR3927_PCIIO_SIZE;
334 mips_pci_mem_base = JMR3927_PCIMEM;
335 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
336#endif
337
338 tx3927_setup();
339
340 if (jmr3927_have_isac()) {
341
342#ifdef CONFIG_FB_E1355
343 argptr = prom_getcmdline();
344 if ((argptr = strstr(argptr, "video=")) == NULL) {
345 argptr = prom_getcmdline();
346 strcat(argptr, " video=e1355fb:crt16h");
347 }
348#endif
349
350#ifdef CONFIG_BLK_DEV_IDE
351 /* overrides PCI-IDE */
352#endif
353 }
354
355 /* SIO0 DTR on */
356 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
357
358 jmr3927_led_set(0);
359
360
361 if (jmr3927_have_isac())
362 jmr3927_io_led_set(0);
363 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
364 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
365 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
366 jmr3927_dipsw1(), jmr3927_dipsw2(),
367 jmr3927_dipsw3(), jmr3927_dipsw4());
368 if (jmr3927_have_isac())
369 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
370 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
371 jmr3927_io_dipsw());
372}
373
Ralf Baechleefd94122005-11-11 11:46:25 +0000374void __init tx3927_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 int i;
377
378 /* SDRAMC are configured by PROM */
379
380 /* ROMC */
381 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
382 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
383 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
384 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
385
386 /* CCFG */
387 /* enable Timeout BusError */
388 if (jmr3927_ccfg_toeon)
389 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
390
391 /* clear BusErrorOnWrite flag */
392 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
393 /* Disable PCI snoop */
394 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
395
396#ifdef DO_WRITE_THROUGH
397 /* Enable PCI SNOOP - with write through only */
398 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
399#endif
400
401 /* Pin selection */
402 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
403 tx3927_ccfgptr->pcfg |=
404 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
405 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
406
407 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
408 tx3927_ccfgptr->crir,
409 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
410
411 /* IRC */
412 /* disable interrupt control */
413 tx3927_ircptr->cer = 0;
414 /* mask all IRC interrupts */
415 tx3927_ircptr->imr = 0;
416 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
417 tx3927_ircptr->ilr[i] = 0;
418 }
419 /* setup IRC interrupt mode (Low Active) */
420 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
421 tx3927_ircptr->cr[i] = 0;
422 }
423
424 /* TMR */
425 /* disable all timers */
426 for (i = 0; i < TX3927_NR_TMR; i++) {
427 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
428 tx3927_tmrptr(i)->tisr = 0;
429 tx3927_tmrptr(i)->cpra = 0xffffffff;
430 tx3927_tmrptr(i)->itmr = 0;
431 tx3927_tmrptr(i)->ccdr = 0;
432 tx3927_tmrptr(i)->pgmr = 0;
433 }
434
435 /* DMA */
436 tx3927_dmaptr->mcr = 0;
Ahmed S. Darwish25b8ac32007-02-05 04:42:11 +0200437 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 /* reset channel */
439 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
440 tx3927_dmaptr->ch[i].ccr = 0;
441 }
442 /* enable DMA */
443#ifdef __BIG_ENDIAN
444 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
445#else
446 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
447#endif
448
449#ifdef CONFIG_PCI
450 /* PCIC */
451 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
452 tx3927_pcicptr->did, tx3927_pcicptr->vid,
453 tx3927_pcicptr->rid);
454 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
455 printk("External\n");
456 /* XXX */
457 } else {
458 printk("Internal\n");
459
460 /* Reset PCI Bus */
461 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
462 udelay(100);
463 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
464 JMR3927_IOC_RESET_ADDR);
465 udelay(100);
466 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
467
468
469 /* Disable External PCI Config. Access */
470 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
471#ifdef __BIG_ENDIAN
472 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
473 TX3927_PCIC_LBC_TIBSE |
474 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
475#endif
476 /* LB->PCI mappings */
477 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
478 tx3927_pcicptr->ilbioma = mips_pci_io_base;
479 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
480 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
481 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
482 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
483 /* PCI->LB mappings */
484 tx3927_pcicptr->iobas = 0xffffffff;
485 tx3927_pcicptr->ioba = 0;
486 tx3927_pcicptr->tlbioma = 0;
487 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
488 tx3927_pcicptr->mba = 0;
489 tx3927_pcicptr->tlbmma = 0;
490#ifndef JMR3927_INIT_INDIRECT_PCI
491 /* Enable Direct mapping Address Space Decoder */
492 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
493#endif
494
495 /* Clear All Local Bus Status */
496 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
497 /* Enable All Local Bus Interrupts */
498 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
499 /* Clear All PCI Status Error */
500 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
501 /* Enable All PCI Status Error Interrupts */
502 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
503
504 /* PCIC Int => IRC IRQ10 */
505 tx3927_pcicptr->il = TX3927_IR_PCI;
506#if 1
507 /* Target Control (per errata) */
508 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
509#endif
510
511 /* Enable Bus Arbiter */
512#if 0
513 tx3927_pcicptr->req_trace = 0x73737373;
514#endif
515 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
516
517 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
518 PCI_COMMAND_MEMORY |
519#if 1
520 PCI_COMMAND_IO |
521#endif
522 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
523 }
524#endif /* CONFIG_PCI */
525
526 /* PIO */
527 /* PIO[15:12] connected to LEDs */
528 tx3927_pioptr->dir = 0x0000f000;
529 tx3927_pioptr->maskcpu = 0;
530 tx3927_pioptr->maskext = 0;
531 {
532 unsigned int conf;
533
534 conf = read_c0_conf();
535 if (!(conf & TX39_CONF_ICE))
536 printk("TX3927 I-Cache disabled.\n");
537 if (!(conf & TX39_CONF_DCE))
538 printk("TX3927 D-Cache disabled.\n");
539 else if (!(conf & TX39_CONF_WBON))
540 printk("TX3927 D-Cache WriteThrough.\n");
541 else if (!(conf & TX39_CONF_CWFON))
542 printk("TX3927 D-Cache WriteBack.\n");
543 else
544 printk("TX3927 D-Cache WriteBack (CWF) .\n");
545 }
546}