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Yaniv Rosnercd88cce2011-01-31 04:21:34 +00001/* Copyright 2008-2011 Broadcom Corporation
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#ifndef BNX2X_LINK_H
18#define BNX2X_LINK_H
19
20
21
22/***********************************************************/
23/* Defines */
24/***********************************************************/
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000025#define DEFAULT_PHY_DEV_ADDR 3
26#define E2_DEFAULT_PHY_DEV_ADDR 5
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070027
28
29
David S. Millerc0700f92008-12-16 23:53:20 -080030#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070035
Yaniv Rosnercd88cce2011-01-31 04:21:34 +000036#define SPEED_AUTO_NEG 0
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070037#define SPEED_12000 12000
38#define SPEED_12500 12500
39#define SPEED_13000 13000
40#define SPEED_15000 15000
41#define SPEED_16000 16000
42
Eilon Greenstein4d295db2009-07-21 05:47:47 +000043#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
44#define SFP_EEPROM_VENDOR_NAME_SIZE 16
45#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
46#define SFP_EEPROM_VENDOR_OUI_SIZE 3
Yaniv Rosnercd88cce2011-01-31 04:21:34 +000047#define SFP_EEPROM_PART_NO_ADDR 0x28
48#define SFP_EEPROM_PART_NO_SIZE 16
Eilon Greenstein4d295db2009-07-21 05:47:47 +000049#define PWR_FLT_ERR_MSG_LEN 250
Yaniv Rosnerb7737c92010-09-07 11:40:54 +000050
51#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
52 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
53#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
54 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
55 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
56#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
57 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
58
Yaniv Rosnere10bc842010-09-07 11:40:50 +000059/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
60#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
61/* Single Media board contains single external phy */
62#define SINGLE_MEDIA(params) (params->num_phys == 2)
Yaniv Rosnera22f0782010-09-07 11:41:20 +000063/* Dual Media board contains two external phy with different media */
64#define DUAL_MEDIA(params) (params->num_phys == 3)
Yaniv Rosnercd88cce2011-01-31 04:21:34 +000065#define FW_PARAM_MDIO_CTRL_OFFSET 16
Yaniv Rosnera22f0782010-09-07 11:41:20 +000066#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
67 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +000068
69#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE 170
70#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE 0
71
72#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE 250
73#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE 0
74
75#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE 10
76#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE 90
77
78#define PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE 50
79#define PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE 250
80
81#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
82#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
83
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070084/***********************************************************/
85/* Structs */
86/***********************************************************/
Yaniv Rosnere10bc842010-09-07 11:40:50 +000087#define INT_PHY 0
88#define EXT_PHY1 1
Yaniv Rosnera22f0782010-09-07 11:41:20 +000089#define EXT_PHY2 2
90#define MAX_PHYS 3
Yaniv Rosnere10bc842010-09-07 11:40:50 +000091
Yaniv Rosnerb7737c92010-09-07 11:40:54 +000092/* Same configuration is shared between the XGXS and the first external phy */
93#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
94#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
95 0 : (_phy_idx - 1))
Yaniv Rosnere10bc842010-09-07 11:40:50 +000096/***********************************************************/
97/* bnx2x_phy struct */
98/* Defines the required arguments and function per phy */
99/***********************************************************/
100struct link_vars;
101struct link_params;
102struct bnx2x_phy;
103
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000104typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
105 struct link_vars *vars);
106typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
107 struct link_vars *vars);
108typedef void (*link_reset_t)(struct bnx2x_phy *phy,
109 struct link_params *params);
110typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
111 struct link_params *params);
112typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
113typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
114typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
115 struct link_params *params, u8 mode);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000116typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
117 struct link_params *params, u32 action);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000118
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000119struct bnx2x_phy {
120 u32 type;
121
122 /* Loaded during init */
123 u8 addr;
124
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000125 u8 flags;
126 /* Require HW lock */
127#define FLAGS_HW_LOCK_REQUIRED (1<<0)
128 /* No Over-Current detection */
129#define FLAGS_NOC (1<<1)
130 /* Fan failure detection required */
131#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
132 /* Initialize first the XGXS and only then the phy itself */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000133#define FLAGS_INIT_XGXS_FIRST (1<<3)
134#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
135#define FLAGS_SFP_NOT_APPROVED (1<<7)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000136
137 u8 def_md_devad;
138 u8 reserved;
139 /* preemphasis values for the rx side */
140 u16 rx_preemphasis[4];
141
142 /* preemphasis values for the tx side */
143 u16 tx_preemphasis[4];
144
145 /* EMAC address for access MDIO */
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000146 u32 mdio_ctrl;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000147
148 u32 supported;
149
150 u32 media_type;
151#define ETH_PHY_UNSPECIFIED 0x0
152#define ETH_PHY_SFP_FIBER 0x1
153#define ETH_PHY_XFP_FIBER 0x2
154#define ETH_PHY_DA_TWINAX 0x3
155#define ETH_PHY_BASE_T 0x4
156#define ETH_PHY_NOT_PRESENT 0xff
157
158 /* The address in which version is located*/
159 u32 ver_addr;
160
161 u16 req_flow_ctrl;
162
163 u16 req_line_speed;
164
165 u32 speed_cap_mask;
166
167 u16 req_duplex;
168 u16 rsrv;
169 /* Called per phy/port init, and it configures LASI, speed, autoneg,
170 duplex, flow control negotiation, etc. */
171 config_init_t config_init;
172
173 /* Called due to interrupt. It determines the link, speed */
174 read_status_t read_status;
175
176 /* Called when driver is unloading. Should reset the phy */
177 link_reset_t link_reset;
178
179 /* Set the loopback configuration for the phy */
180 config_loopback_t config_loopback;
181
182 /* Format the given raw number into str up to len */
183 format_fw_ver_t format_fw_ver;
184
185 /* Reset the phy (both ports) */
186 hw_reset_t hw_reset;
187
188 /* Set link led mode (on/off/oper)*/
189 set_link_led_t set_link_led;
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000190
191 /* PHY Specific tasks */
192 phy_specific_func_t phy_specific_func;
193#define DISABLE_TX 1
194#define ENABLE_TX 2
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000195};
196
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700197/* Inputs parameters to the CLC */
198struct link_params {
199
200 u8 port;
201
202 /* Default / User Configuration */
203 u8 loopback_mode;
Yaniv Rosnercd88cce2011-01-31 04:21:34 +0000204#define LOOPBACK_NONE 0
205#define LOOPBACK_EMAC 1
206#define LOOPBACK_BMAC 2
Yaniv Rosnerde6eae12010-09-07 11:41:13 +0000207#define LOOPBACK_XGXS 3
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700208#define LOOPBACK_EXT_PHY 4
Yaniv Rosnercd88cce2011-01-31 04:21:34 +0000209#define LOOPBACK_EXT 5
210#define LOOPBACK_UMAC 6
211#define LOOPBACK_XMAC 7
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700212
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700213 /* Device parameters */
214 u8 mac_addr[6];
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -0700215
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000216 u16 req_duplex[LINK_CONFIG_SIZE];
217 u16 req_flow_ctrl[LINK_CONFIG_SIZE];
218
219 u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
220
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700221 /* shmem parameters */
222 u32 shmem_base;
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000223 u32 shmem2_base;
224 u32 speed_cap_mask[LINK_CONFIG_SIZE];
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700225 u32 switch_cfg;
226#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
227#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
228#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
229
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700230 u32 lane_config;
Eilon Greenstein659bc5c2009-08-12 08:24:02 +0000231
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700232 /* Phy register parameter */
233 u32 chip_id;
234
Yaniv Rosnercd88cce2011-01-31 04:21:34 +0000235 /* features */
Eilon Greenstein589abe32009-02-12 08:36:55 +0000236 u32 feature_config_flags;
Yaniv Rosnercd88cce2011-01-31 04:21:34 +0000237#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
238#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
239#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000240#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000241 /* Will be populated during common init */
242 struct bnx2x_phy phy[MAX_PHYS];
243
244 /* Will be populated during common init */
245 u8 num_phys;
Eilon Greenstein1ef70b92009-08-12 08:23:59 +0000246
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000247 u8 rsrv;
248 u16 hw_led_mode; /* part of the hw_config read from the shmem */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000249 u32 multi_phy_config;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +0000250
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700251 /* Device pointer passed to all callback functions */
252 struct bnx2x *bp;
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000253 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
254 req_flow_ctrl is set to AUTO */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700255};
256
257/* Output parameters */
258struct link_vars {
Eilon Greenstein1ef70b92009-08-12 08:23:59 +0000259 u8 phy_flags;
260
261 u8 mac_type;
262#define MAC_TYPE_NONE 0
263#define MAC_TYPE_EMAC 1
264#define MAC_TYPE_BMAC 2
265
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700266 u8 phy_link_up; /* internal phy link indication */
267 u8 link_up;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700268
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700269 u16 line_speed;
Eilon Greenstein1ef70b92009-08-12 08:23:59 +0000270 u16 duplex;
271
272 u16 flow_ctrl;
273 u16 ieee_fc;
274
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700275 /* The same definitions as the shmem parameter */
276 u32 link_status;
277};
278
279/***********************************************************/
280/* Functions */
281/***********************************************************/
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700282u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
283
Eilon Greenstein589abe32009-02-12 08:36:55 +0000284/* Reset the link. Should be called when driver or interface goes down
285 Before calling phy firmware upgrade, the reset_ext_phy should be set
286 to 0 */
287u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
288 u8 reset_ext_phy);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700289
290/* bnx2x_link_update should be called upon link interrupt */
291u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
292
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000293/* use the following phy functions to read/write from external_phy
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700294 In order to use it to read/write internal phy registers, use
295 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700296 the register */
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000297u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
298 u8 devad, u16 reg, u16 *ret_val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700299
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000300u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
301 u8 devad, u16 reg, u16 val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700302/* Reads the link_status from the shmem,
Eilon Greenstein33471622008-08-13 15:59:08 -0700303 and update the link vars accordingly */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700304void bnx2x_link_status_update(struct link_params *input,
305 struct link_vars *output);
306/* returns string representing the fw_version of the external phy */
307u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
308 u8 *version, u16 len);
309
310/* Set/Unset the led
311 Basically, the CLC takes care of the led for the link, but in case one needs
Eilon Greenstein33471622008-08-13 15:59:08 -0700312 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700313 blink the led, and LED_MODE_OFF to set the led off.*/
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +0000314u8 bnx2x_set_led(struct link_params *params, struct link_vars *vars,
315 u8 mode, u32 speed);
316#define LED_MODE_OFF 0
317#define LED_MODE_ON 1
318#define LED_MODE_OPER 2
319#define LED_MODE_FRONT_PANEL_OFF 3
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700320
Eilon Greenstein589abe32009-02-12 08:36:55 +0000321/* bnx2x_handle_module_detect_int should be called upon module detection
322 interrupt */
323void bnx2x_handle_module_detect_int(struct link_params *params);
324
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700325/* Get the actual link status. In case it returns 0, link is up,
326 otherwise link is down*/
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000327u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars,
328 u8 is_serdes);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700329
Yaniv Rosner6bbca912008-08-13 15:57:28 -0700330/* One-time initialization for external phy after power up */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000331u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
332 u32 shmem2_base_path[], u32 chip_id);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700333
Eilon Greensteinf57a6022009-08-12 08:23:11 +0000334/* Reset the external PHY using GPIO */
335void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
336
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000337/* Reset the external of SFX7101 */
338void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
Eilon Greenstein356e2382009-02-12 08:38:32 +0000339
Yaniv Rosner65a001b2011-01-31 04:22:03 +0000340/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
341u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
342 struct link_params *params, u16 addr,
343 u8 byte_cnt, u8 *o_buf);
344
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +0000345void bnx2x_hw_reset_phy(struct link_params *params);
346
347/* Checks if HW lock is required for this phy/board type */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000348u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
349 u32 shmem2_base);
350
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000351/* Check swap bit and adjust PHY order */
352u32 bnx2x_phy_selection(struct link_params *params);
353
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000354/* Probe the phys on board, and populate them in "params" */
355u8 bnx2x_phy_probe(struct link_params *params);
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +0000356/* Checks if fan failure detection is required on one of the phys on board */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000357u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
358 u32 shmem2_base, u8 port);
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +0000359
Vladislav Zolotarove4901dd2010-12-13 05:44:18 +0000360/* PFC port configuration params */
361struct bnx2x_nig_brb_pfc_port_params {
362 /* NIG */
363 u32 pause_enable;
364 u32 llfc_out_en;
365 u32 llfc_enable;
366 u32 pkt_priority_to_cos;
367 u32 rx_cos0_priority_mask;
368 u32 rx_cos1_priority_mask;
369 u32 llfc_high_priority_classes;
370 u32 llfc_low_priority_classes;
371 /* BRB */
372 u32 cos0_pauseable;
373 u32 cos1_pauseable;
374};
375
376/**
377 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
378 * when link is already up
379 */
380void bnx2x_update_pfc(struct link_params *params,
381 struct link_vars *vars,
382 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
383
384
385/* Used to configure the ETS to disable */
386void bnx2x_ets_disabled(struct link_params *params);
387
388/* Used to configure the ETS to BW limited */
389void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
Yaniv Rosnercd88cce2011-01-31 04:21:34 +0000390 const u32 cos1_bw);
Vladislav Zolotarove4901dd2010-12-13 05:44:18 +0000391
392/* Used to configure the ETS to strict */
393u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
394
395/* Read pfc statistic*/
396void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
397 u32 pfc_frames_sent[2],
398 u32 pfc_frames_received[2]);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700399#endif /* BNX2X_LINK_H */