blob: c3cabc2536584d615d77f74c62244961587f245a [file] [log] [blame]
Madan Mohan Koyyalamudif2e7dcc2013-06-18 13:03:26 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __NFC_NCI_H
14#define __NFC_NCI_H
15
16#include <linux/i2c.h>
17#include <linux/types.h>
18#include <linux/version.h>
19
20#include <linux/semaphore.h>
21#include <linux/completion.h>
22
23#include <linux/ioctl.h>
24#include <linux/cdev.h>
25#include <linux/miscdevice.h>
26
27struct nfc_device {
28 struct cdev cdev;
29 struct class *char_class;
30};
31
32enum ehandler_mode {
Bansidhar Gopalachari25fc8742013-07-16 00:46:19 -070033 UNSOLICITED_MODE = 0,
34 SOLICITED_MODE,
35 UNSOLICITED_FTM_RAW_MODE,
36 SOLICITED_FTM_RAW_MODE
Madan Mohan Koyyalamudif2e7dcc2013-06-18 13:03:26 -070037};
38
39enum ekernel_logging_mode {
40 LEVEL_0 = 0, /* For Basic Comms, such asNCI TX/TX to NFCC */
41 LEVEL_1, /* Other Debug e.g. Notifications, ISR hit, etc ..*/
42 LEVEL_2,
43 LEVEL_3,
44 LEVEL_4,
45 LEVEL_5
46};
47
Bansidhar Gopalachari25fc8742013-07-16 00:46:19 -070048struct devicemode {
Madan Mohan Koyyalamudif2e7dcc2013-06-18 13:03:26 -070049 enum ehandler_mode handle_flavour;
Bansidhar Gopalachari25fc8742013-07-16 00:46:19 -070050} tdevicemode;
Madan Mohan Koyyalamudif2e7dcc2013-06-18 13:03:26 -070051
52#define NFC_DRIVER_NAME "nfc-nci"
53#define NFC_I2C_DRIVER_NAME "NCI NFC I2C Interface",
54
55#define NCI_I2C_SLAVE (0x2C)
56#define NFC_I2C_BUS 3 /* 6, 10, 4, 5 */
57#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
58#define NFCC_MODE _IOW(0xE9, 0x02, unsigned int)
59#define NFC_KERNEL_LOGGING_MODE _IOW(0xE9, 0x03, unsigned int)
60#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
61#define SET_EMULATOR_TEST_POINT _IOW(0xE9, 0x05, unsigned int)
62
63#define NFC_MAX_I2C_TRANSFER (0x0400)
64#define NFC_MSG_MAX_SIZE (0x21)
65
66#define NFC_RX_BUFFER_CNT_START (0x0)
67
68#define NFC_RX_BUFFER_BLOCK_SIZE (0x120) /* Bytes per Block */
69#define NFC_RX_BUFFER_PAGE_SIZE (0x1000) /* Page size Bytes */
70#define NFC_RX_BUFFER_PAGES (0x8)
71#define NFC_RX_ORDER_FREE_PAGES (0x3) /* Free 8 Pages */
72
73/* The total no. of Blocks */
74#define NFC_RX_BUFFER_CNT_LIMIT (unsigned short)( \
75 ( \
76 ((NFC_RX_BUFFER_PAGE_SIZE) *\
77 (NFC_RX_BUFFER_PAGES))/\
78 (NFC_RX_BUFFER_BLOCK_SIZE)\
79 ) \
80 ) \
81
82#define PAYLOAD_HEADER_LENGTH (0x3)
83#define PAYLOAD_LENGTH_MAX (256)
84#define BYTE (0x8)
85#define NCI_IDENTIFIER (0x10)
86
87/** Power Management Related **/
88
89#define NFCC_WAKE (0x01)
90#define NFCC_SLEEP (0x00)
91
92#define XTAL_CLOCK (0X00)
93#define REFERENCE_CLOCK (0X01)
94
95/* LDO Trim Settings */
96#define IPTAT_TRIM (0x1F)
97#define V1P1_TRIM (0x0F)
98#define V1P8_TRIM (0x0F)
99#define VBATT_OK_THRESHOLD (0x07)
100
101#define PWR_EN (0x08) /* Enable 1.1V LDO Regulator */
102#define LS_EN (0x04) /* Enable 1.1V->1.8V Level Shifters */
103
104/* Write '1' to cause wake event to NFCC. If set NFCC will not go to SLEEP */
105#define NCI_WAKE (0x02)
106
107#define NCI_ENA (0x01) /* Write '1' to enable PLL */
108#define FREQ_SEL (0x00) /* XO Frequency Select */
109#define FREQ_SEL_13 (0x00) /* XO Frequency Select = 13.56MHz */
110#define FREQ_SEL_19 (0x01) /* XO Frequency Select = 19.20 MHz */
111#define FREQ_SEL_26 (0x02) /* XO Frequency Select = 26.00 MHz */
112#define FREQ_SEL_27 (0x03) /* XO Frequency Select = 27.12 MHz */
113#define FREQ_SEL_37 (0x04) /* XO Frequency Select = 37.40 MHz */
114#define FREQ_SEL_38 (0x05) /* XO Frequency Select = 38.40 MHz */
115#define FREQ_SEL_40 (0x06) /* XO Frequency Select = 40.00 MHz */
116#define FREQ_SEL_48 (0x07) /* XO Frequency Select = 48.00 MHz */
117#define FREQ_SEL_27 (0x03) /* XO Frequency Select */
118
119
120#define QUALIFY_REFCLK (0x80)
121#define QUALIFY_OSC (0x40)
122#define LOCALBIASXTAL (0x20)
123#define BIAS2X_FORCE (0x10)
124#define BIAS2X (0x08)
125#define LBIAS2X (0x04)
126#define SMALLRF (0x02)
127#define SMALLRBIAS (0x01)
128
129/* Select as appropriate */
130#define CRYSTAL_OSC ((QUALIFY_REFCLK) | (QUALIFY_OSC) | \
131 (LOCALBIASXTAL) | (BIAS2X_FORCE) | \
132 (BIAS2X) | (LBIAS2X) | (SMALLRF) | (SMALLRBIAS))
133
134#define CDACIN (0x3F) /* Tuning range for load capacitor at X1*/
135#define CDACOUT (0x3F) /* Tuning range for load capacitor at X2*/
136
137#define RAW(reg, value) (raw_##reg[1] = value)
138
139/* Logging macro with threshold control */
140#define PRINTK(LEVEL, THRESHOLD, pString, ...) ( \
141 if (LEVEL > THRESHOLD) { \
142 pr_info(pString, ##__VA_ARGS__); \
143 } \
144 )
145
146/* board config */
147struct nfc_platform_data {
148 int (*request_resources) (struct i2c_client *client);
149 void (*free_resources) (void);
150 void (*enable) (int fw);
151 int (*test) (void);
152 void (*disable) (void);
153};
154/*
155 * Internal NFCC Hardware states. At present these may not be possible to
156 * detect in software as possibly no power when
157 * in monitor state! Also, need to detect DISABLE control GPIO from PMIC.
158 */
159enum nfcc_hardware_state {
160 NFCC_STATE_MONITOR, /* VBAT < h/w Critcal Voltage */
161 /* VBAT > H/W Critical Voltage;
162 Lowest Power Mode - DISABLE = 1; only
163 possible when phone is ON */
164 NFCC_STATE_HPD,
165 /* VBAT > H/W Critical Voltage; DISABLE = 0;
166 Only possible when phone is ON */
167 NFCC_STSTE_ULPM,
168 /* VBAT > H/W Critical Voltage; DISABLE = 0;
169 Powered by PMIC & VBAT; 1.8V I/O supply on; VDDPX available, boot is
170 initiated by host over I2C */
171 NFCC_STATE_NORMAL_REGION1,
172 /* VBAT > H/W Critical Voltage; DISABLE = 0;
173 Powered by VBAT; 1.8V I/O supply on; VDDPX available, boot is initiated
174 by host over I2C */
175 NFCC_STATE_NORMAL_REGION2,
176};
177
178/* We assume here that VBATT > h/w Critical Voltage */
179enum nfcc_state {
180 /* Assume In ULPM state, ready for initialisation, cannot detect for
181 Monitor or HPD states */
182 NFCC_STATE_COLD,
183 /* (VDDPX==1) && (Following I2C initialisation). In Region 1 or Region2
184 state WAKE */
185 NFCC_STATE_NORMAL_WAKE,
186 /* (VDDPX==1) && (Following I2C initialisation). In Region 1 or Region2
187 state SLEEP */
188 NFCC_STATE_NORMAL_SLEEP,
189};
190
191
192enum nfcc_irq {
193 NFCC_NO_INT,
194 NFCC_INT,
195};
196
197
198struct nfc_info {
199 struct miscdevice miscdev;
200 struct i2c_client *i2c_dev;
201 struct regulator_bulk_data regs[3];
202 enum nfcc_state state;
203 wait_queue_head_t read_wait;
204 loff_t read_offset;
205 struct mutex read_mutex;
206 struct mutex mutex;
207 u8 *buf;
208 size_t buflen;
209 spinlock_t irq_enabled_lock;
210 unsigned int count_irq;
211 enum nfcc_irq read_irq;
212};
213
214
215struct nfc_i2c_platform_data {
216 unsigned int nfc_irq_gpio;
217 unsigned int nfc_clk_en_gpio;
218 unsigned int dis_gpio;
219 unsigned int irq_gpio;
220 unsigned int ven_gpio;
221 unsigned int firm_gpio;
222 unsigned int reg;
223};
224#endif