Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 1 | #ifndef _LINUX_IRQ_H |
| 2 | #define _LINUX_IRQ_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | |
| 4 | /* |
| 5 | * Please do not include this file in generic code. There is currently |
| 6 | * no requirement for any architecture to implement anything held |
| 7 | * within this file. |
| 8 | * |
| 9 | * Thanks. --rmk |
| 10 | */ |
| 11 | |
Adrian Bunk | 23f9b31 | 2005-12-21 02:27:50 +0100 | [diff] [blame] | 12 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 14 | #ifndef CONFIG_S390 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | #include <linux/linkage.h> |
| 17 | #include <linux/cache.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/cpumask.h> |
Ralf Baechle | 503e576 | 2009-03-29 12:59:50 +0200 | [diff] [blame] | 20 | #include <linux/gfp.h> |
Jan Beulich | 908dcec | 2006-06-23 02:06:00 -0700 | [diff] [blame] | 21 | #include <linux/irqreturn.h> |
Thomas Gleixner | dd3a1db | 2008-10-16 18:20:58 +0200 | [diff] [blame] | 22 | #include <linux/irqnr.h> |
David Howells | 77904fd | 2007-02-28 20:13:26 -0800 | [diff] [blame] | 23 | #include <linux/errno.h> |
Ralf Baechle | 503e576 | 2009-03-29 12:59:50 +0200 | [diff] [blame] | 24 | #include <linux/topology.h> |
Thomas Gleixner | 3aa551c | 2009-03-23 18:28:15 +0100 | [diff] [blame] | 25 | #include <linux/wait.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
| 27 | #include <asm/irq.h> |
| 28 | #include <asm/ptrace.h> |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 29 | #include <asm/irq_regs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Thomas Gleixner | ab7798f | 2011-03-25 16:48:50 +0100 | [diff] [blame] | 31 | struct seq_file; |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 32 | struct irq_desc; |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 33 | struct irq_data; |
Harvey Harrison | ec70158 | 2008-02-08 04:19:55 -0800 | [diff] [blame] | 34 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 35 | struct irq_desc *desc); |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 36 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | /* |
| 39 | * IRQ line status. |
Thomas Gleixner | 6e21361 | 2006-07-01 19:29:03 -0700 | [diff] [blame] | 40 | * |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 41 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
Thomas Gleixner | 6e21361 | 2006-07-01 19:29:03 -0700 | [diff] [blame] | 42 | * |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 43 | * IRQ_TYPE_NONE - default, unspecified type |
| 44 | * IRQ_TYPE_EDGE_RISING - rising edge triggered |
| 45 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered |
| 46 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered |
| 47 | * IRQ_TYPE_LEVEL_HIGH - high level triggered |
| 48 | * IRQ_TYPE_LEVEL_LOW - low level triggered |
| 49 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits |
| 50 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits |
| 51 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
| 52 | * |
| 53 | * Bits which can be modified via irq_set/clear/modify_status_flags() |
| 54 | * IRQ_LEVEL - Interrupt is level type. Will be also |
| 55 | * updated in the code when the above trigger |
Geert Uytterhoeven | 0911f12 | 2011-04-10 11:01:51 +0200 | [diff] [blame] | 56 | * bits are modified via irq_set_irq_type() |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 57 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
| 58 | * it from affinity setting |
| 59 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing |
| 60 | * IRQ_NOREQUEST - Interrupt cannot be requested via |
| 61 | * request_irq() |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 62 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 63 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
| 64 | * request/setup_irq() |
| 65 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) |
| 66 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context |
| 67 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | */ |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 69 | enum { |
| 70 | IRQ_TYPE_NONE = 0x00000000, |
| 71 | IRQ_TYPE_EDGE_RISING = 0x00000001, |
| 72 | IRQ_TYPE_EDGE_FALLING = 0x00000002, |
| 73 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), |
| 74 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, |
| 75 | IRQ_TYPE_LEVEL_LOW = 0x00000008, |
| 76 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), |
| 77 | IRQ_TYPE_SENSE_MASK = 0x0000000f, |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 78 | |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 79 | IRQ_TYPE_PROBE = 0x00000010, |
Thomas Gleixner | 6e21361 | 2006-07-01 19:29:03 -0700 | [diff] [blame] | 80 | |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 81 | IRQ_LEVEL = (1 << 8), |
| 82 | IRQ_PER_CPU = (1 << 9), |
| 83 | IRQ_NOPROBE = (1 << 10), |
| 84 | IRQ_NOREQUEST = (1 << 11), |
| 85 | IRQ_NOAUTOEN = (1 << 12), |
| 86 | IRQ_NO_BALANCING = (1 << 13), |
| 87 | IRQ_MOVE_PCNTXT = (1 << 14), |
| 88 | IRQ_NESTED_THREAD = (1 << 15), |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 89 | IRQ_NOTHREAD = (1 << 16), |
Thomas Gleixner | 5d4d8fc | 2011-02-08 17:27:18 +0100 | [diff] [blame] | 90 | }; |
Thomas Gleixner | 950f442 | 2007-02-16 01:27:24 -0800 | [diff] [blame] | 91 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 92 | #define IRQF_MODIFY_MASK \ |
| 93 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ |
Thomas Gleixner | 872434d | 2011-02-05 16:25:25 +0100 | [diff] [blame] | 94 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
Thomas Gleixner | 6f91a52 | 2011-02-14 13:33:16 +0100 | [diff] [blame] | 95 | IRQ_PER_CPU | IRQ_NESTED_THREAD) |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 96 | |
Thomas Gleixner | 8f53f92 | 2011-02-08 16:50:00 +0100 | [diff] [blame] | 97 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
| 98 | |
Thomas Gleixner | 3b8249e | 2011-02-07 16:02:20 +0100 | [diff] [blame] | 99 | /* |
| 100 | * Return value for chip->irq_set_affinity() |
| 101 | * |
| 102 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity |
| 103 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity |
| 104 | */ |
| 105 | enum { |
| 106 | IRQ_SET_MASK_OK = 0, |
| 107 | IRQ_SET_MASK_OK_NOCOPY, |
| 108 | }; |
| 109 | |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 110 | struct msi_desc; |
Grant Likely | 08a543a | 2011-07-26 03:19:06 -0600 | [diff] [blame] | 111 | struct irq_domain; |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 112 | |
Ingo Molnar | 8fee5c3 | 2006-06-29 02:24:45 -0700 | [diff] [blame] | 113 | /** |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 114 | * struct irq_data - per irq and irq chip data passed down to chip functions |
| 115 | * @irq: interrupt number |
Grant Likely | 08a543a | 2011-07-26 03:19:06 -0600 | [diff] [blame] | 116 | * @hwirq: hardware interrupt number, local to the interrupt domain |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 117 | * @node: node index useful for balancing |
Randy Dunlap | 30398bf | 2011-03-18 09:33:56 -0700 | [diff] [blame] | 118 | * @state_use_accessors: status information for irq chip functions. |
Thomas Gleixner | 91c4991 | 2011-02-03 20:48:29 +0100 | [diff] [blame] | 119 | * Use accessor functions to deal with it |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 120 | * @chip: low level interrupt hardware access |
Grant Likely | 08a543a | 2011-07-26 03:19:06 -0600 | [diff] [blame] | 121 | * @domain: Interrupt translation domain; responsible for mapping |
| 122 | * between hwirq number and linux irq number. |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 123 | * @handler_data: per-IRQ data for the irq_chip methods |
| 124 | * @chip_data: platform-specific per-chip private data for the chip |
| 125 | * methods, to allow shared chip implementations |
| 126 | * @msi_desc: MSI descriptor |
| 127 | * @affinity: IRQ affinity on SMP |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 128 | * |
| 129 | * The fields here need to overlay the ones in irq_desc until we |
| 130 | * cleaned up the direct references and switched everything over to |
| 131 | * irq_data. |
| 132 | */ |
| 133 | struct irq_data { |
| 134 | unsigned int irq; |
Grant Likely | 08a543a | 2011-07-26 03:19:06 -0600 | [diff] [blame] | 135 | unsigned long hwirq; |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 136 | unsigned int node; |
Thomas Gleixner | 91c4991 | 2011-02-03 20:48:29 +0100 | [diff] [blame] | 137 | unsigned int state_use_accessors; |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 138 | struct irq_chip *chip; |
Grant Likely | 08a543a | 2011-07-26 03:19:06 -0600 | [diff] [blame] | 139 | struct irq_domain *domain; |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 140 | void *handler_data; |
| 141 | void *chip_data; |
| 142 | struct msi_desc *msi_desc; |
| 143 | #ifdef CONFIG_SMP |
| 144 | cpumask_var_t affinity; |
| 145 | #endif |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 146 | }; |
| 147 | |
Thomas Gleixner | f230b6d | 2011-02-05 15:20:04 +0100 | [diff] [blame] | 148 | /* |
| 149 | * Bit masks for irq_data.state |
| 150 | * |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 151 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
Thomas Gleixner | f230b6d | 2011-02-05 15:20:04 +0100 | [diff] [blame] | 152 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 153 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
| 154 | * IRQD_PER_CPU - Interrupt is per cpu |
Thomas Gleixner | 2bdd105 | 2011-02-08 17:22:00 +0100 | [diff] [blame] | 155 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 156 | * IRQD_LEVEL - Interrupt is level triggered |
Thomas Gleixner | 7f94226 | 2011-02-10 19:46:26 +0100 | [diff] [blame] | 157 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
| 158 | * from suspend |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 159 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
| 160 | * context |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 161 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
| 162 | * IRQD_IRQ_MASKED - Masked state of the interrupt |
| 163 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt |
Thomas Gleixner | f230b6d | 2011-02-05 15:20:04 +0100 | [diff] [blame] | 164 | */ |
| 165 | enum { |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 166 | IRQD_TRIGGER_MASK = 0xf, |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 167 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
| 168 | IRQD_NO_BALANCING = (1 << 10), |
| 169 | IRQD_PER_CPU = (1 << 11), |
Thomas Gleixner | 2bdd105 | 2011-02-08 17:22:00 +0100 | [diff] [blame] | 170 | IRQD_AFFINITY_SET = (1 << 12), |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 171 | IRQD_LEVEL = (1 << 13), |
Thomas Gleixner | 7f94226 | 2011-02-10 19:46:26 +0100 | [diff] [blame] | 172 | IRQD_WAKEUP_STATE = (1 << 14), |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 173 | IRQD_MOVE_PCNTXT = (1 << 15), |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 174 | IRQD_IRQ_DISABLED = (1 << 16), |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 175 | IRQD_IRQ_MASKED = (1 << 17), |
| 176 | IRQD_IRQ_INPROGRESS = (1 << 18), |
Thomas Gleixner | f230b6d | 2011-02-05 15:20:04 +0100 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
| 180 | { |
| 181 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; |
| 182 | } |
| 183 | |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 184 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
| 185 | { |
| 186 | return d->state_use_accessors & IRQD_PER_CPU; |
| 187 | } |
| 188 | |
| 189 | static inline bool irqd_can_balance(struct irq_data *d) |
| 190 | { |
| 191 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
| 192 | } |
| 193 | |
Thomas Gleixner | 2bdd105 | 2011-02-08 17:22:00 +0100 | [diff] [blame] | 194 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
| 195 | { |
| 196 | return d->state_use_accessors & IRQD_AFFINITY_SET; |
| 197 | } |
| 198 | |
Thomas Gleixner | ee38c04 | 2011-03-28 17:11:13 +0200 | [diff] [blame] | 199 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
| 200 | { |
| 201 | d->state_use_accessors |= IRQD_AFFINITY_SET; |
| 202 | } |
| 203 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 204 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
| 205 | { |
| 206 | return d->state_use_accessors & IRQD_TRIGGER_MASK; |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * Must only be called inside irq_chip.irq_set_type() functions. |
| 211 | */ |
| 212 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) |
| 213 | { |
| 214 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; |
| 215 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; |
| 216 | } |
| 217 | |
| 218 | static inline bool irqd_is_level_type(struct irq_data *d) |
| 219 | { |
| 220 | return d->state_use_accessors & IRQD_LEVEL; |
| 221 | } |
| 222 | |
Thomas Gleixner | 7f94226 | 2011-02-10 19:46:26 +0100 | [diff] [blame] | 223 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
| 224 | { |
| 225 | return d->state_use_accessors & IRQD_WAKEUP_STATE; |
| 226 | } |
| 227 | |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 228 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
| 229 | { |
| 230 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; |
| 231 | } |
| 232 | |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 233 | static inline bool irqd_irq_disabled(struct irq_data *d) |
| 234 | { |
| 235 | return d->state_use_accessors & IRQD_IRQ_DISABLED; |
| 236 | } |
| 237 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 238 | static inline bool irqd_irq_masked(struct irq_data *d) |
| 239 | { |
| 240 | return d->state_use_accessors & IRQD_IRQ_MASKED; |
| 241 | } |
| 242 | |
| 243 | static inline bool irqd_irq_inprogress(struct irq_data *d) |
| 244 | { |
| 245 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; |
| 246 | } |
| 247 | |
Thomas Gleixner | 9cff60d | 2011-03-28 16:41:14 +0200 | [diff] [blame] | 248 | /* |
| 249 | * Functions for chained handlers which can be enabled/disabled by the |
| 250 | * standard disable_irq/enable_irq calls. Must be called with |
| 251 | * irq_desc->lock held. |
| 252 | */ |
| 253 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) |
| 254 | { |
| 255 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; |
| 256 | } |
| 257 | |
| 258 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) |
| 259 | { |
| 260 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; |
| 261 | } |
| 262 | |
Thomas Gleixner | ff7dcd4 | 2010-09-27 12:44:25 +0000 | [diff] [blame] | 263 | /** |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 264 | * struct irq_chip - hardware interrupt chip descriptor |
Ingo Molnar | 8fee5c3 | 2006-06-29 02:24:45 -0700 | [diff] [blame] | 265 | * |
| 266 | * @name: name for /proc/interrupts |
Thomas Gleixner | f882265 | 2010-09-27 12:44:32 +0000 | [diff] [blame] | 267 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
| 268 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) |
| 269 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) |
| 270 | * @irq_disable: disable the interrupt |
| 271 | * @irq_ack: start of a new interrupt |
| 272 | * @irq_mask: mask an interrupt source |
| 273 | * @irq_mask_ack: ack and mask an interrupt source |
| 274 | * @irq_unmask: unmask an interrupt source |
| 275 | * @irq_eoi: end of interrupt |
| 276 | * @irq_set_affinity: set the CPU affinity on SMP machines |
| 277 | * @irq_retrigger: resend an IRQ to the CPU |
| 278 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ |
| 279 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ |
| 280 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips |
| 281 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 282 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
| 283 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU |
Thomas Gleixner | cfefd21 | 2011-04-15 22:36:08 +0200 | [diff] [blame] | 284 | * @irq_suspend: function called from core code on suspend once per chip |
| 285 | * @irq_resume: function called from core code on resume once per chip |
| 286 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
Thomas Gleixner | ab7798f | 2011-03-25 16:48:50 +0100 | [diff] [blame] | 287 | * @irq_print_chip: optional to print special chip info in show_interrupts |
Thomas Gleixner | 2bff17a | 2011-02-10 13:08:38 +0100 | [diff] [blame] | 288 | * @flags: chip specific flags |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 289 | * |
Ingo Molnar | 8fee5c3 | 2006-06-29 02:24:45 -0700 | [diff] [blame] | 290 | * @release: release function solely used by UML |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | */ |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 292 | struct irq_chip { |
| 293 | const char *name; |
Thomas Gleixner | f882265 | 2010-09-27 12:44:32 +0000 | [diff] [blame] | 294 | unsigned int (*irq_startup)(struct irq_data *data); |
| 295 | void (*irq_shutdown)(struct irq_data *data); |
| 296 | void (*irq_enable)(struct irq_data *data); |
| 297 | void (*irq_disable)(struct irq_data *data); |
| 298 | |
| 299 | void (*irq_ack)(struct irq_data *data); |
| 300 | void (*irq_mask)(struct irq_data *data); |
| 301 | void (*irq_mask_ack)(struct irq_data *data); |
| 302 | void (*irq_unmask)(struct irq_data *data); |
| 303 | void (*irq_eoi)(struct irq_data *data); |
| 304 | |
| 305 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); |
| 306 | int (*irq_retrigger)(struct irq_data *data); |
| 307 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); |
| 308 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); |
| 309 | |
| 310 | void (*irq_bus_lock)(struct irq_data *data); |
| 311 | void (*irq_bus_sync_unlock)(struct irq_data *data); |
| 312 | |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 313 | void (*irq_cpu_online)(struct irq_data *data); |
| 314 | void (*irq_cpu_offline)(struct irq_data *data); |
| 315 | |
Thomas Gleixner | cfefd21 | 2011-04-15 22:36:08 +0200 | [diff] [blame] | 316 | void (*irq_suspend)(struct irq_data *data); |
| 317 | void (*irq_resume)(struct irq_data *data); |
| 318 | void (*irq_pm_shutdown)(struct irq_data *data); |
| 319 | |
Thomas Gleixner | ab7798f | 2011-03-25 16:48:50 +0100 | [diff] [blame] | 320 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
| 321 | |
Thomas Gleixner | 2bff17a | 2011-02-10 13:08:38 +0100 | [diff] [blame] | 322 | unsigned long flags; |
| 323 | |
Paolo 'Blaisorblade' Giarrusso | b77d6ad | 2005-06-21 17:16:24 -0700 | [diff] [blame] | 324 | /* Currently used only by UML, might disappear one day.*/ |
| 325 | #ifdef CONFIG_IRQ_RELEASE_METHOD |
Ingo Molnar | 71d218b | 2006-06-29 02:24:41 -0700 | [diff] [blame] | 326 | void (*release)(unsigned int irq, void *dev_id); |
Paolo 'Blaisorblade' Giarrusso | b77d6ad | 2005-06-21 17:16:24 -0700 | [diff] [blame] | 327 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | }; |
| 329 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 330 | /* |
| 331 | * irq_chip specific flags |
| 332 | * |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 333 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
| 334 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled |
Thomas Gleixner | d209a69 | 2011-03-11 21:22:14 +0100 | [diff] [blame] | 335 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 336 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
| 337 | * when irq enabled |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 338 | */ |
| 339 | enum { |
| 340 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 341 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
Thomas Gleixner | d209a69 | 2011-03-11 21:22:14 +0100 | [diff] [blame] | 342 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 343 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 344 | }; |
| 345 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 346 | /* This include will go away once we isolated irq_desc usage to core code */ |
| 347 | #include <linux/irqdesc.h> |
Thomas Gleixner | c6b7674 | 2008-10-15 14:31:29 +0200 | [diff] [blame] | 348 | |
Ingo Molnar | 34ffdb7 | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 349 | /* |
Ingo Molnar | 34ffdb7 | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 350 | * Pick up the arch-dependent methods: |
| 351 | */ |
| 352 | #include <asm/hw_irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | |
Thomas Gleixner | b683de2 | 2010-09-27 20:55:03 +0200 | [diff] [blame] | 354 | #ifndef NR_IRQS_LEGACY |
| 355 | # define NR_IRQS_LEGACY 0 |
| 356 | #endif |
| 357 | |
Thomas Gleixner | 1318a48 | 2010-09-27 21:01:37 +0200 | [diff] [blame] | 358 | #ifndef ARCH_IRQ_INIT_FLAGS |
| 359 | # define ARCH_IRQ_INIT_FLAGS 0 |
| 360 | #endif |
| 361 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 362 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
Thomas Gleixner | 1318a48 | 2010-09-27 21:01:37 +0200 | [diff] [blame] | 363 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 364 | struct irqaction; |
Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 365 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
Magnus Damm | cbf94f0 | 2009-03-12 21:05:51 +0900 | [diff] [blame] | 366 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 368 | extern void irq_cpu_online(void); |
| 369 | extern void irq_cpu_offline(void); |
David Daney | c2d0c55 | 2011-03-25 12:38:50 -0700 | [diff] [blame] | 370 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 371 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | #ifdef CONFIG_GENERIC_HARDIRQS |
Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 373 | |
Thomas Gleixner | 3a3856d | 2010-10-04 13:47:12 +0200 | [diff] [blame] | 374 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 375 | void irq_move_irq(struct irq_data *data); |
| 376 | void irq_move_masked_irq(struct irq_data *data); |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 377 | #else |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 378 | static inline void irq_move_irq(struct irq_data *data) { } |
| 379 | static inline void irq_move_masked_irq(struct irq_data *data) { } |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 380 | #endif |
Ashok Raj | 54d5d42 | 2005-09-06 15:16:15 -0700 | [diff] [blame] | 381 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | extern int no_irq_affinity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | |
Ingo Molnar | 2e60bbb | 2006-06-29 02:24:39 -0700 | [diff] [blame] | 384 | /* |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 385 | * Built-in IRQ handlers for various IRQ types, |
Krzysztof Halasa | bebd04c | 2009-11-15 18:57:24 +0100 | [diff] [blame] | 386 | * callable via desc->handle_irq() |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 387 | */ |
Harvey Harrison | ec70158 | 2008-02-08 04:19:55 -0800 | [diff] [blame] | 388 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
| 389 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); |
| 390 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 391 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
Harvey Harrison | ec70158 | 2008-02-08 04:19:55 -0800 | [diff] [blame] | 392 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
| 393 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); |
| 394 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
Mark Brown | 31b47cf | 2009-08-24 20:28:04 +0100 | [diff] [blame] | 395 | extern void handle_nested_irq(unsigned int irq); |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 396 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 397 | /* Handling of unhandled and spurious interrupts: */ |
Ingo Molnar | 34ffdb7 | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 398 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
Thomas Gleixner | bedd30d | 2008-09-30 23:14:27 +0200 | [diff] [blame] | 399 | irqreturn_t action_ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | |
Thomas Gleixner | a4633ad | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 401 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 402 | /* Enable/disable irq debugging output: */ |
| 403 | extern int noirqdebug_setup(char *str); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 405 | /* Checks whether the interrupt can be requested by request_irq(): */ |
| 406 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); |
| 407 | |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 408 | /* Dummy irq-chip implementations: */ |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 409 | extern struct irq_chip no_irq_chip; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 410 | extern struct irq_chip dummy_irq_chip; |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 411 | |
| 412 | extern void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 413 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 414 | irq_flow_handler_t handle, const char *name); |
| 415 | |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 416 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
| 417 | irq_flow_handler_t handle) |
| 418 | { |
| 419 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); |
| 420 | } |
| 421 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 422 | extern void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 423 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 424 | const char *name); |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 425 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 426 | static inline void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 427 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 428 | { |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 429 | __irq_set_handler(irq, handle, 0, NULL); |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | /* |
| 433 | * Set a highlevel chained flow handler for a given IRQ. |
| 434 | * (a chained handler is automatically enabled and set to |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 435 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 436 | */ |
| 437 | static inline void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 438 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 439 | { |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 440 | __irq_set_handler(irq, handle, 1, NULL); |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 441 | } |
| 442 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 443 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
| 444 | |
| 445 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) |
| 446 | { |
| 447 | irq_modify_status(irq, 0, set); |
| 448 | } |
| 449 | |
| 450 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) |
| 451 | { |
| 452 | irq_modify_status(irq, clr, 0); |
| 453 | } |
| 454 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 455 | static inline void irq_set_noprobe(unsigned int irq) |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 456 | { |
| 457 | irq_modify_status(irq, 0, IRQ_NOPROBE); |
| 458 | } |
| 459 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 460 | static inline void irq_set_probe(unsigned int irq) |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 461 | { |
| 462 | irq_modify_status(irq, IRQ_NOPROBE, 0); |
| 463 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 464 | |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 465 | static inline void irq_set_nothread(unsigned int irq) |
| 466 | { |
| 467 | irq_modify_status(irq, 0, IRQ_NOTHREAD); |
| 468 | } |
| 469 | |
| 470 | static inline void irq_set_thread(unsigned int irq) |
| 471 | { |
| 472 | irq_modify_status(irq, IRQ_NOTHREAD, 0); |
| 473 | } |
| 474 | |
Thomas Gleixner | 6f91a52 | 2011-02-14 13:33:16 +0100 | [diff] [blame] | 475 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
| 476 | { |
| 477 | if (nest) |
| 478 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); |
| 479 | else |
| 480 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); |
| 481 | } |
| 482 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 483 | /* Handle dynamic irq creation and destruction */ |
Yinghai Lu | d047f53 | 2009-04-27 18:02:23 -0700 | [diff] [blame] | 484 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 485 | extern int create_irq(void); |
| 486 | extern void destroy_irq(unsigned int irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 487 | |
Thomas Gleixner | b7b2933 | 2010-09-29 18:46:55 +0200 | [diff] [blame] | 488 | /* |
| 489 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and |
| 490 | * irq_free_desc instead. |
| 491 | */ |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 492 | extern void dynamic_irq_cleanup(unsigned int irq); |
Thomas Gleixner | b7b2933 | 2010-09-29 18:46:55 +0200 | [diff] [blame] | 493 | static inline void dynamic_irq_init(unsigned int irq) |
| 494 | { |
| 495 | dynamic_irq_cleanup(irq); |
| 496 | } |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 497 | |
| 498 | /* Set/get chip/data for an IRQ: */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 499 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
| 500 | extern int irq_set_handler_data(unsigned int irq, void *data); |
| 501 | extern int irq_set_chip_data(unsigned int irq, void *data); |
| 502 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); |
| 503 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 504 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 505 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 506 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 507 | { |
| 508 | struct irq_data *d = irq_get_irq_data(irq); |
| 509 | return d ? d->chip : NULL; |
| 510 | } |
| 511 | |
| 512 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) |
| 513 | { |
| 514 | return d->chip; |
| 515 | } |
| 516 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 517 | static inline void *irq_get_chip_data(unsigned int irq) |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 518 | { |
| 519 | struct irq_data *d = irq_get_irq_data(irq); |
| 520 | return d ? d->chip_data : NULL; |
| 521 | } |
| 522 | |
| 523 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) |
| 524 | { |
| 525 | return d->chip_data; |
| 526 | } |
| 527 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 528 | static inline void *irq_get_handler_data(unsigned int irq) |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 529 | { |
| 530 | struct irq_data *d = irq_get_irq_data(irq); |
| 531 | return d ? d->handler_data : NULL; |
| 532 | } |
| 533 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 534 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 535 | { |
| 536 | return d->handler_data; |
| 537 | } |
| 538 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 539 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 540 | { |
| 541 | struct irq_data *d = irq_get_irq_data(irq); |
| 542 | return d ? d->msi_desc : NULL; |
| 543 | } |
| 544 | |
| 545 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) |
| 546 | { |
| 547 | return d->msi_desc; |
| 548 | } |
| 549 | |
Thomas Gleixner | 1f5a5b8 | 2010-09-27 17:48:26 +0200 | [diff] [blame] | 550 | int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node); |
| 551 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
Thomas Gleixner | 06f6c33 | 2010-10-12 12:31:46 +0200 | [diff] [blame] | 552 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); |
Thomas Gleixner | 1f5a5b8 | 2010-09-27 17:48:26 +0200 | [diff] [blame] | 553 | |
| 554 | static inline int irq_alloc_desc(int node) |
| 555 | { |
| 556 | return irq_alloc_descs(-1, 0, 1, node); |
| 557 | } |
| 558 | |
| 559 | static inline int irq_alloc_desc_at(unsigned int at, int node) |
| 560 | { |
| 561 | return irq_alloc_descs(at, at, 1, node); |
| 562 | } |
| 563 | |
| 564 | static inline int irq_alloc_desc_from(unsigned int from, int node) |
| 565 | { |
| 566 | return irq_alloc_descs(-1, from, 1, node); |
| 567 | } |
| 568 | |
| 569 | static inline void irq_free_desc(unsigned int irq) |
| 570 | { |
| 571 | irq_free_descs(irq, 1); |
| 572 | } |
| 573 | |
Paul Mundt | 639bd12 | 2010-10-26 16:19:13 +0900 | [diff] [blame] | 574 | static inline int irq_reserve_irq(unsigned int irq) |
| 575 | { |
| 576 | return irq_reserve_irqs(irq, 1); |
| 577 | } |
| 578 | |
Thomas Gleixner | 7d82806 | 2011-04-03 11:42:53 +0200 | [diff] [blame] | 579 | #ifndef irq_reg_writel |
| 580 | # define irq_reg_writel(val, addr) writel(val, addr) |
| 581 | #endif |
| 582 | #ifndef irq_reg_readl |
| 583 | # define irq_reg_readl(addr) readl(addr) |
| 584 | #endif |
| 585 | |
| 586 | /** |
| 587 | * struct irq_chip_regs - register offsets for struct irq_gci |
| 588 | * @enable: Enable register offset to reg_base |
| 589 | * @disable: Disable register offset to reg_base |
| 590 | * @mask: Mask register offset to reg_base |
| 591 | * @ack: Ack register offset to reg_base |
| 592 | * @eoi: Eoi register offset to reg_base |
| 593 | * @type: Type configuration register offset to reg_base |
| 594 | * @polarity: Polarity configuration register offset to reg_base |
| 595 | */ |
| 596 | struct irq_chip_regs { |
| 597 | unsigned long enable; |
| 598 | unsigned long disable; |
| 599 | unsigned long mask; |
| 600 | unsigned long ack; |
| 601 | unsigned long eoi; |
| 602 | unsigned long type; |
| 603 | unsigned long polarity; |
| 604 | }; |
| 605 | |
| 606 | /** |
| 607 | * struct irq_chip_type - Generic interrupt chip instance for a flow type |
| 608 | * @chip: The real interrupt chip which provides the callbacks |
| 609 | * @regs: Register offsets for this chip |
| 610 | * @handler: Flow handler associated with this chip |
| 611 | * @type: Chip can handle these flow types |
| 612 | * |
| 613 | * A irq_generic_chip can have several instances of irq_chip_type when |
| 614 | * it requires different functions and register offsets for different |
| 615 | * flow types. |
| 616 | */ |
| 617 | struct irq_chip_type { |
| 618 | struct irq_chip chip; |
| 619 | struct irq_chip_regs regs; |
| 620 | irq_flow_handler_t handler; |
| 621 | u32 type; |
| 622 | }; |
| 623 | |
| 624 | /** |
| 625 | * struct irq_chip_generic - Generic irq chip data structure |
| 626 | * @lock: Lock to protect register and cache data access |
| 627 | * @reg_base: Register base address (virtual) |
| 628 | * @irq_base: Interrupt base nr for this chip |
| 629 | * @irq_cnt: Number of interrupts handled by this chip |
| 630 | * @mask_cache: Cached mask register |
| 631 | * @type_cache: Cached type register |
| 632 | * @polarity_cache: Cached polarity register |
| 633 | * @wake_enabled: Interrupt can wakeup from suspend |
| 634 | * @wake_active: Interrupt is marked as an wakeup from suspend source |
| 635 | * @num_ct: Number of available irq_chip_type instances (usually 1) |
| 636 | * @private: Private data for non generic chip callbacks |
Thomas Gleixner | cfefd21 | 2011-04-15 22:36:08 +0200 | [diff] [blame] | 637 | * @list: List head for keeping track of instances |
Thomas Gleixner | 7d82806 | 2011-04-03 11:42:53 +0200 | [diff] [blame] | 638 | * @chip_types: Array of interrupt irq_chip_types |
| 639 | * |
| 640 | * Note, that irq_chip_generic can have multiple irq_chip_type |
| 641 | * implementations which can be associated to a particular irq line of |
| 642 | * an irq_chip_generic instance. That allows to share and protect |
| 643 | * state in an irq_chip_generic instance when we need to implement |
| 644 | * different flow mechanisms (level/edge) for it. |
| 645 | */ |
| 646 | struct irq_chip_generic { |
| 647 | raw_spinlock_t lock; |
| 648 | void __iomem *reg_base; |
| 649 | unsigned int irq_base; |
| 650 | unsigned int irq_cnt; |
| 651 | u32 mask_cache; |
| 652 | u32 type_cache; |
| 653 | u32 polarity_cache; |
| 654 | u32 wake_enabled; |
| 655 | u32 wake_active; |
| 656 | unsigned int num_ct; |
| 657 | void *private; |
Thomas Gleixner | cfefd21 | 2011-04-15 22:36:08 +0200 | [diff] [blame] | 658 | struct list_head list; |
Thomas Gleixner | 7d82806 | 2011-04-03 11:42:53 +0200 | [diff] [blame] | 659 | struct irq_chip_type chip_types[0]; |
| 660 | }; |
| 661 | |
| 662 | /** |
| 663 | * enum irq_gc_flags - Initialization flags for generic irq chips |
| 664 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg |
| 665 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for |
| 666 | * irq chips which need to call irq_set_wake() on |
| 667 | * the parent irq. Usually GPIO implementations |
| 668 | */ |
| 669 | enum irq_gc_flags { |
| 670 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, |
| 671 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, |
| 672 | }; |
| 673 | |
| 674 | /* Generic chip callback functions */ |
| 675 | void irq_gc_noop(struct irq_data *d); |
| 676 | void irq_gc_mask_disable_reg(struct irq_data *d); |
| 677 | void irq_gc_mask_set_bit(struct irq_data *d); |
| 678 | void irq_gc_mask_clr_bit(struct irq_data *d); |
| 679 | void irq_gc_unmask_enable_reg(struct irq_data *d); |
Simon Guinot | 659fb32 | 2011-07-06 12:41:31 -0400 | [diff] [blame] | 680 | void irq_gc_ack_set_bit(struct irq_data *d); |
| 681 | void irq_gc_ack_clr_bit(struct irq_data *d); |
Thomas Gleixner | 7d82806 | 2011-04-03 11:42:53 +0200 | [diff] [blame] | 682 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
| 683 | void irq_gc_eoi(struct irq_data *d); |
| 684 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); |
| 685 | |
| 686 | /* Setup functions for irq_chip_generic */ |
| 687 | struct irq_chip_generic * |
| 688 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, |
| 689 | void __iomem *reg_base, irq_flow_handler_t handler); |
| 690 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, |
| 691 | enum irq_gc_flags flags, unsigned int clr, |
| 692 | unsigned int set); |
| 693 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); |
Thomas Gleixner | cfefd21 | 2011-04-15 22:36:08 +0200 | [diff] [blame] | 694 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
| 695 | unsigned int clr, unsigned int set); |
Thomas Gleixner | 7d82806 | 2011-04-03 11:42:53 +0200 | [diff] [blame] | 696 | |
| 697 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
| 698 | { |
| 699 | return container_of(d->chip, struct irq_chip_type, chip); |
| 700 | } |
| 701 | |
| 702 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) |
| 703 | |
| 704 | #ifdef CONFIG_SMP |
| 705 | static inline void irq_gc_lock(struct irq_chip_generic *gc) |
| 706 | { |
| 707 | raw_spin_lock(&gc->lock); |
| 708 | } |
| 709 | |
| 710 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) |
| 711 | { |
| 712 | raw_spin_unlock(&gc->lock); |
| 713 | } |
| 714 | #else |
| 715 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } |
| 716 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } |
| 717 | #endif |
| 718 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 719 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | |
Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 721 | #endif /* !CONFIG_S390 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 722 | |
Ingo Molnar | 06fcb0c | 2006-06-29 02:24:40 -0700 | [diff] [blame] | 723 | #endif /* _LINUX_IRQ_H */ |