| Eric Miao | 1f017a9 | 2008-11-28 14:19:33 +0800 | [diff] [blame] | 1 | #ifndef __ASM_ARCH_REGS_AC97_H |
| 2 | #define __ASM_ARCH_REGS_AC97_H |
| 3 | |
| Eric Miao | ec971c9 | 2009-01-19 11:39:36 +0800 | [diff] [blame] | 4 | #include <mach/hardware.h> |
| 5 | |
| Eric Miao | 1f017a9 | 2008-11-28 14:19:33 +0800 | [diff] [blame] | 6 | /* |
| 7 | * AC97 Controller registers |
| 8 | */ |
| 9 | |
| 10 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ |
| 11 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 12 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 13 | |
| 14 | #define PICR __REG(0x40500004) /* PCM In Control Register */ |
| 15 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 16 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 17 | |
| 18 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ |
| 19 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 20 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 21 | |
| 22 | #define GCR __REG(0x4050000C) /* Global Control Register */ |
| 23 | #ifdef CONFIG_PXA3xx |
| 24 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ |
| 25 | #endif |
| 26 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ |
| 27 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ |
| 28 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ |
| 29 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ |
| 30 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ |
| 31 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ |
| 32 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ |
| 33 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ |
| 34 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ |
| 35 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ |
| 36 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ |
| 37 | |
| 38 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ |
| 39 | #define POSR_FIFOE (1 << 4) /* FIFO error */ |
| 40 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ |
| 41 | |
| 42 | #define PISR __REG(0x40500014) /* PCM In Status Register */ |
| 43 | #define PISR_FIFOE (1 << 4) /* FIFO error */ |
| 44 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 45 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ |
| 46 | |
| 47 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ |
| 48 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ |
| 49 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 50 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ |
| 51 | |
| 52 | #define GSR __REG(0x4050001C) /* Global Status Register */ |
| 53 | #define GSR_CDONE (1 << 19) /* Command Done */ |
| 54 | #define GSR_SDONE (1 << 18) /* Status Done */ |
| 55 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ |
| 56 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ |
| 57 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ |
| 58 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ |
| 59 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ |
| 60 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ |
| 61 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ |
| 62 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ |
| 63 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ |
| 64 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ |
| 65 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ |
| 66 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ |
| 67 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ |
| 68 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ |
| 69 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ |
| 70 | |
| 71 | #define CAR __REG(0x40500020) /* CODEC Access Register */ |
| 72 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ |
| 73 | |
| 74 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ |
| 75 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ |
| 76 | |
| 77 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ |
| 78 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ |
| 79 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 80 | |
| 81 | #define MICR __REG(0x40500108) /* Modem In Control Register */ |
| 82 | #define MICR_FEIE (1 << 3) /* FIFO Error */ |
| 83 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 84 | |
| 85 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ |
| 86 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ |
| 87 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ |
| 88 | |
| 89 | #define MISR __REG(0x40500118) /* Modem In Status Register */ |
| 90 | #define MISR_FIFOE (1 << 4) /* FIFO error */ |
| 91 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 92 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ |
| 93 | |
| 94 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ |
| 95 | |
| 96 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ |
| 97 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ |
| 98 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ |
| 99 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ |
| 100 | |
| 101 | #endif /* __ASM_ARCH_REGS_AC97_H */ |