Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*****************************************************************************/ |
| 2 | /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ |
| 3 | /* */ |
| 4 | /* Written By: Keith Mitchell, IBM Corporation */ |
| 5 | /* Jack Hammer, Adaptec, Inc. */ |
| 6 | /* David Jeffery, Adaptec, Inc. */ |
| 7 | /* */ |
| 8 | /* Copyright (C) 2000 IBM Corporation */ |
| 9 | /* Copyright (C) 2002,2003 Adaptec, Inc. */ |
| 10 | /* */ |
| 11 | /* This program is free software; you can redistribute it and/or modify */ |
| 12 | /* it under the terms of the GNU General Public License as published by */ |
| 13 | /* the Free Software Foundation; either version 2 of the License, or */ |
| 14 | /* (at your option) any later version. */ |
| 15 | /* */ |
| 16 | /* This program is distributed in the hope that it will be useful, */ |
| 17 | /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ |
| 18 | /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ |
| 19 | /* GNU General Public License for more details. */ |
| 20 | /* */ |
| 21 | /* NO WARRANTY */ |
| 22 | /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ |
| 23 | /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ |
| 24 | /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ |
| 25 | /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ |
| 26 | /* solely responsible for determining the appropriateness of using and */ |
| 27 | /* distributing the Program and assumes all risks associated with its */ |
| 28 | /* exercise of rights under this Agreement, including but not limited to */ |
| 29 | /* the risks and costs of program errors, damage to or loss of data, */ |
| 30 | /* programs or equipment, and unavailability or interruption of operations. */ |
| 31 | /* */ |
| 32 | /* DISCLAIMER OF LIABILITY */ |
| 33 | /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ |
| 34 | /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ |
| 35 | /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ |
| 36 | /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ |
| 37 | /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ |
| 38 | /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ |
| 39 | /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ |
| 40 | /* */ |
| 41 | /* You should have received a copy of the GNU General Public License */ |
| 42 | /* along with this program; if not, write to the Free Software */ |
| 43 | /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ |
| 44 | /* */ |
| 45 | /* Bugs/Comments/Suggestions about this driver should be mailed to: */ |
| 46 | /* ipslinux@adaptec.com */ |
| 47 | /* */ |
| 48 | /* For system support issues, contact your local IBM Customer support. */ |
| 49 | /* Directions to find IBM Customer Support for each country can be found at: */ |
| 50 | /* http://www.ibm.com/planetwide/ */ |
| 51 | /* */ |
| 52 | /*****************************************************************************/ |
| 53 | |
| 54 | /*****************************************************************************/ |
| 55 | /* Change Log */ |
| 56 | /* */ |
| 57 | /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ |
| 58 | /* 0.99.03 - Make interrupt routine handle all completed request on the */ |
| 59 | /* adapter not just the first one */ |
| 60 | /* - Make sure passthru commands get woken up if we run out of */ |
| 61 | /* SCBs */ |
| 62 | /* - Send all of the commands on the queue at once rather than */ |
| 63 | /* one at a time since the card will support it. */ |
| 64 | /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ |
| 65 | /* the interface to the utilities to change */ |
| 66 | /* - Fix error recovery code */ |
| 67 | /* 0.99.05 - Fix an oops when we get certain passthru commands */ |
| 68 | /* 1.00.00 - Initial Public Release */ |
| 69 | /* Functionally equivalent to 0.99.05 */ |
| 70 | /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ |
| 71 | /* - Change version to 3.60 to coincide with release numbering. */ |
| 72 | /* 3.60.01 - Remove bogus error check in passthru routine */ |
| 73 | /* 3.60.02 - Make DCDB direction based on lookup table */ |
| 74 | /* - Only allow one DCDB command to a SCSI ID at a time */ |
| 75 | /* 4.00.00 - Add support for ServeRAID 4 */ |
| 76 | /* 4.00.01 - Add support for First Failure Data Capture */ |
| 77 | /* 4.00.02 - Fix problem with PT DCDB with no buffer */ |
| 78 | /* 4.00.03 - Add alternative passthru interface */ |
| 79 | /* - Add ability to flash BIOS */ |
| 80 | /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ |
| 81 | /* 4.00.05 - Remove wish_block from init routine */ |
| 82 | /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ |
| 83 | /* 2.3.18 and later */ |
| 84 | /* - Sync with other changes from the 2.3 kernels */ |
| 85 | /* 4.00.06 - Fix timeout with initial FFDC command */ |
| 86 | /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ |
| 87 | /* 4.10.00 - Add support for ServeRAID 4M/4L */ |
| 88 | /* 4.10.13 - Fix for dynamic unload and proc file system */ |
| 89 | /* 4.20.03 - Rename version to coincide with new release schedules */ |
| 90 | /* Performance fixes */ |
| 91 | /* Fix truncation of /proc files with cat */ |
| 92 | /* Merge in changes through kernel 2.4.0test1ac21 */ |
| 93 | /* 4.20.13 - Fix some failure cases / reset code */ |
| 94 | /* - Hook into the reboot_notifier to flush the controller cache */ |
| 95 | /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ |
| 96 | /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ |
| 97 | /* - Add IPSSEND Flash Support */ |
| 98 | /* - Set Sense Data for Unknown SCSI Command */ |
| 99 | /* - Use Slot Number from NVRAM Page 5 */ |
| 100 | /* - Restore caller's DCDB Structure */ |
| 101 | /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ |
| 102 | /* 4.70.13 - Don't Send CDB's if we already know the device is not present */ |
| 103 | /* - Don't release HA Lock in ips_next() until SC taken off queue */ |
| 104 | /* - Unregister SCSI device in ips_release() */ |
| 105 | /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ |
| 106 | /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ |
| 107 | /* Code Clean-Up for 2.4.x kernel */ |
| 108 | /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ |
| 109 | /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ |
| 110 | /* - Don't Issue Internal FFDC Command if there are Active Commands */ |
| 111 | /* - Close Window for getting too many IOCTL's active */ |
| 112 | /* 4.80.00 - Make ia64 Safe */ |
| 113 | /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ |
| 114 | /* - Adjustments to Device Queue Depth */ |
| 115 | /* 4.80.14 - Take all semaphores off stack */ |
| 116 | /* - Clean Up New_IOCTL path */ |
| 117 | /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ |
| 118 | /* - 5 second delay needed after resetting an i960 adapter */ |
| 119 | /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ |
| 120 | /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ |
| 121 | /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ |
| 122 | /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ |
| 123 | /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ |
| 124 | /* 4.90.11 - Don't actually RESET unless it's physically required */ |
| 125 | /* - Remove unused compile options */ |
| 126 | /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ |
| 127 | /* - Get rid on IOCTL_NEW_COMMAND code */ |
| 128 | /* - Add Extended DCDB Commands for Tape Support in 5I */ |
| 129 | /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ |
| 130 | /* 5.10.15 - remove unused code (sem, macros, etc.) */ |
| 131 | /* 5.30.00 - use __devexit_p() */ |
| 132 | /* 6.00.00 - Add 6x Adapters and Battery Flash */ |
| 133 | /* 6.10.00 - Remove 1G Addressing Limitations */ |
| 134 | /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ |
| 135 | /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ |
Jack Hammer | c1a1546 | 2005-07-26 10:20:33 -0400 | [diff] [blame] | 136 | /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ |
| 138 | /* - Fix sort order of 7k */ |
| 139 | /* - Remove 3 unused "inline" functions */ |
Jack Hammer | c1a1546 | 2005-07-26 10:20:33 -0400 | [diff] [blame] | 140 | /* 7.12.xx - Use STATIC functions whereever possible */ |
| 141 | /* - Clean up deprecated MODULE_PARM calls */ |
Jack Hammer | a60768e | 2005-11-03 09:46:00 -0500 | [diff] [blame] | 142 | /* 7.12.05 - Remove Version Matching per IBM request */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | /*****************************************************************************/ |
| 144 | |
| 145 | /* |
| 146 | * Conditional Compilation directives for this driver: |
| 147 | * |
| 148 | * IPS_DEBUG - Turn on debugging info |
| 149 | * |
| 150 | * Parameters: |
| 151 | * |
| 152 | * debug:<number> - Set debug level to <number> |
| 153 | * NOTE: only works when IPS_DEBUG compile directive is used. |
| 154 | * 1 - Normal debug messages |
| 155 | * 2 - Verbose debug messages |
| 156 | * 11 - Method trace (non interrupt) |
| 157 | * 12 - Method trace (includes interrupt) |
| 158 | * |
| 159 | * noi2o - Don't use I2O Queues (ServeRAID 4 only) |
| 160 | * nommap - Don't use memory mapped I/O |
| 161 | * ioctlsize - Initial size of the IOCTL buffer |
| 162 | */ |
| 163 | |
| 164 | #include <asm/io.h> |
| 165 | #include <asm/byteorder.h> |
| 166 | #include <asm/page.h> |
| 167 | #include <linux/stddef.h> |
| 168 | #include <linux/version.h> |
| 169 | #include <linux/string.h> |
| 170 | #include <linux/errno.h> |
| 171 | #include <linux/kernel.h> |
| 172 | #include <linux/ioport.h> |
| 173 | #include <linux/slab.h> |
| 174 | #include <linux/delay.h> |
| 175 | #include <linux/pci.h> |
| 176 | #include <linux/proc_fs.h> |
| 177 | #include <linux/reboot.h> |
| 178 | #include <linux/interrupt.h> |
| 179 | |
| 180 | #include <linux/blkdev.h> |
| 181 | #include <linux/types.h> |
| 182 | |
| 183 | #include <scsi/sg.h> |
| 184 | |
| 185 | #include "scsi.h" |
| 186 | |
| 187 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) |
| 188 | #include "hosts.h" |
| 189 | #else |
| 190 | #include <scsi/scsi_host.h> |
| 191 | #endif |
| 192 | |
| 193 | #include "ips.h" |
| 194 | |
| 195 | #include <linux/module.h> |
| 196 | |
| 197 | #include <linux/stat.h> |
| 198 | #include <linux/config.h> |
| 199 | |
| 200 | #include <linux/spinlock.h> |
| 201 | #include <linux/init.h> |
| 202 | |
| 203 | #include <linux/smp.h> |
| 204 | |
| 205 | #ifdef MODULE |
| 206 | static char *ips = NULL; |
| 207 | module_param(ips, charp, 0); |
| 208 | #endif |
| 209 | |
| 210 | /* |
| 211 | * DRIVER_VER |
| 212 | */ |
Jack Hammer | c1a1546 | 2005-07-26 10:20:33 -0400 | [diff] [blame] | 213 | #define IPS_VERSION_HIGH "7.12" |
Jack Hammer | a60768e | 2005-11-03 09:46:00 -0500 | [diff] [blame] | 214 | #define IPS_VERSION_LOW ".05 " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | |
| 216 | #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) |
| 217 | #warning "This driver has only been tested on the x86/ia64/x86_64 platforms" |
| 218 | #endif |
| 219 | |
| 220 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) |
| 221 | #include <linux/blk.h> |
| 222 | #include "sd.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | #define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags) |
| 224 | #define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags) |
| 225 | #ifndef __devexit_p |
| 226 | #define __devexit_p(x) x |
| 227 | #endif |
| 228 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | #define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0) |
| 230 | #define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0) |
| 231 | #endif |
| 232 | |
| 233 | #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ |
| be7db05 | 2005-04-17 15:26:13 -0500 | [diff] [blame] | 234 | DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | PCI_DMA_BIDIRECTIONAL : \ |
| be7db05 | 2005-04-17 15:26:13 -0500 | [diff] [blame] | 236 | scb->scsi_cmd->sc_data_direction) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | |
| 238 | #ifdef IPS_DEBUG |
| 239 | #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); |
| 240 | #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); |
| 241 | #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); |
| 242 | #else |
| 243 | #define METHOD_TRACE(s, i) |
| 244 | #define DEBUG(i, s) |
| 245 | #define DEBUG_VAR(i, s, v...) |
| 246 | #endif |
| 247 | |
| 248 | /* |
| 249 | * Function prototypes |
| 250 | */ |
Christoph Hellwig | d0be4a7d | 2005-10-31 18:31:40 +0100 | [diff] [blame] | 251 | static int ips_detect(struct scsi_host_template *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | static int ips_release(struct Scsi_Host *); |
| 253 | static int ips_eh_abort(Scsi_Cmnd *); |
| 254 | static int ips_eh_reset(Scsi_Cmnd *); |
| 255 | static int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *)); |
| 256 | static const char *ips_info(struct Scsi_Host *); |
| 257 | static irqreturn_t do_ipsintr(int, void *, struct pt_regs *); |
| 258 | static int ips_hainit(ips_ha_t *); |
| 259 | static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); |
| 260 | static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); |
| 261 | static int ips_send_cmd(ips_ha_t *, ips_scb_t *); |
| 262 | static int ips_online(ips_ha_t *, ips_scb_t *); |
| 263 | static int ips_inquiry(ips_ha_t *, ips_scb_t *); |
| 264 | static int ips_rdcap(ips_ha_t *, ips_scb_t *); |
| 265 | static int ips_msense(ips_ha_t *, ips_scb_t *); |
| 266 | static int ips_reqsen(ips_ha_t *, ips_scb_t *); |
| 267 | static int ips_deallocatescbs(ips_ha_t *, int); |
| 268 | static int ips_allocatescbs(ips_ha_t *); |
| 269 | static int ips_reset_copperhead(ips_ha_t *); |
| 270 | static int ips_reset_copperhead_memio(ips_ha_t *); |
| 271 | static int ips_reset_morpheus(ips_ha_t *); |
| 272 | static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); |
| 273 | static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); |
| 274 | static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); |
| 275 | static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); |
| 276 | static int ips_isintr_copperhead(ips_ha_t *); |
| 277 | static int ips_isintr_copperhead_memio(ips_ha_t *); |
| 278 | static int ips_isintr_morpheus(ips_ha_t *); |
| 279 | static int ips_wait(ips_ha_t *, int, int); |
| 280 | static int ips_write_driver_status(ips_ha_t *, int); |
| 281 | static int ips_read_adapter_status(ips_ha_t *, int); |
| 282 | static int ips_read_subsystem_parameters(ips_ha_t *, int); |
| 283 | static int ips_read_config(ips_ha_t *, int); |
| 284 | static int ips_clear_adapter(ips_ha_t *, int); |
| 285 | static int ips_readwrite_page5(ips_ha_t *, int, int); |
| 286 | static int ips_init_copperhead(ips_ha_t *); |
| 287 | static int ips_init_copperhead_memio(ips_ha_t *); |
| 288 | static int ips_init_morpheus(ips_ha_t *); |
| 289 | static int ips_isinit_copperhead(ips_ha_t *); |
| 290 | static int ips_isinit_copperhead_memio(ips_ha_t *); |
| 291 | static int ips_isinit_morpheus(ips_ha_t *); |
| 292 | static int ips_erase_bios(ips_ha_t *); |
| 293 | static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); |
| 294 | static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); |
| 295 | static int ips_erase_bios_memio(ips_ha_t *); |
| 296 | static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); |
| 297 | static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); |
| 298 | static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
| 299 | static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
| 300 | static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
| 301 | static void ips_free_flash_copperhead(ips_ha_t * ha); |
| 302 | static void ips_get_bios_version(ips_ha_t *, int); |
| 303 | static void ips_identify_controller(ips_ha_t *); |
| 304 | static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); |
| 305 | static void ips_enable_int_copperhead(ips_ha_t *); |
| 306 | static void ips_enable_int_copperhead_memio(ips_ha_t *); |
| 307 | static void ips_enable_int_morpheus(ips_ha_t *); |
| 308 | static int ips_intr_copperhead(ips_ha_t *); |
| 309 | static int ips_intr_morpheus(ips_ha_t *); |
| 310 | static void ips_next(ips_ha_t *, int); |
| 311 | static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); |
| 312 | static void ipsintr_done(ips_ha_t *, struct ips_scb *); |
| 313 | static void ips_done(ips_ha_t *, ips_scb_t *); |
| 314 | static void ips_free(ips_ha_t *); |
| 315 | static void ips_init_scb(ips_ha_t *, ips_scb_t *); |
| 316 | static void ips_freescb(ips_ha_t *, ips_scb_t *); |
| 317 | static void ips_setup_funclist(ips_ha_t *); |
| 318 | static void ips_statinit(ips_ha_t *); |
| 319 | static void ips_statinit_memio(ips_ha_t *); |
| 320 | static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t); |
| 321 | static void ips_ffdc_reset(ips_ha_t *, int); |
| 322 | static void ips_ffdc_time(ips_ha_t *); |
| 323 | static uint32_t ips_statupd_copperhead(ips_ha_t *); |
| 324 | static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); |
| 325 | static uint32_t ips_statupd_morpheus(ips_ha_t *); |
| 326 | static ips_scb_t *ips_getscb(ips_ha_t *); |
| 327 | static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); |
| 328 | static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *); |
| 329 | static void ips_putq_copp_tail(ips_copp_queue_t *, |
| 330 | ips_copp_wait_item_t *); |
| 331 | static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); |
| 332 | static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); |
| 333 | static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *); |
| 334 | static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *); |
| 335 | static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, |
| 336 | ips_copp_wait_item_t *); |
| 337 | static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); |
| 338 | |
| 339 | static int ips_is_passthru(Scsi_Cmnd *); |
| 340 | static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int); |
| 341 | static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
| 342 | static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); |
| 343 | static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, |
| 344 | unsigned int count); |
| 345 | static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count); |
| 346 | |
| 347 | static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int); |
| 348 | static int ips_host_info(ips_ha_t *, char *, off_t, int); |
| 349 | static void copy_mem_info(IPS_INFOSTR *, char *, int); |
| 350 | static int copy_info(IPS_INFOSTR *, char *, ...); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | static int ips_abort_init(ips_ha_t * ha, int index); |
| 352 | static int ips_init_phase2(int index); |
| 353 | |
| 354 | static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); |
| 355 | static int ips_register_scsi(int index); |
| 356 | |
Jack Hammer | ee807c2 | 2005-08-29 10:44:34 -0400 | [diff] [blame] | 357 | static int ips_poll_for_flush_complete(ips_ha_t * ha); |
| 358 | static void ips_flush_and_reset(ips_ha_t *ha); |
| 359 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | /* |
| 361 | * global variables |
| 362 | */ |
| 363 | static const char ips_name[] = "ips"; |
| 364 | static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ |
| 365 | static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ |
| 366 | static unsigned int ips_next_controller; |
| 367 | static unsigned int ips_num_controllers; |
| 368 | static unsigned int ips_released_controllers; |
| 369 | static int ips_hotplug; |
| 370 | static int ips_cmd_timeout = 60; |
| 371 | static int ips_reset_timeout = 60 * 5; |
| 372 | static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ |
| 373 | static int ips_force_i2o = 1; /* Always use I2O command delivery */ |
| 374 | static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ |
| 375 | static int ips_cd_boot; /* Booting from Manager CD */ |
| 376 | static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ |
| 377 | static dma_addr_t ips_flashbusaddr; |
| 378 | static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ |
| 379 | static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ |
Christoph Hellwig | d0be4a7d | 2005-10-31 18:31:40 +0100 | [diff] [blame] | 380 | static struct scsi_host_template ips_driver_template = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | .detect = ips_detect, |
| 382 | .release = ips_release, |
| 383 | .info = ips_info, |
| 384 | .queuecommand = ips_queue, |
| 385 | .eh_abort_handler = ips_eh_abort, |
| 386 | .eh_host_reset_handler = ips_eh_reset, |
| 387 | .proc_name = "ips", |
| 388 | #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) |
| 389 | .proc_info = ips_proc_info, |
| 390 | .slave_configure = ips_slave_configure, |
| 391 | #else |
| 392 | .proc_info = ips_proc24_info, |
| 393 | .select_queue_depths = ips_select_queue_depth, |
| 394 | #endif |
| 395 | .bios_param = ips_biosparam, |
| 396 | .this_id = -1, |
| 397 | .sg_tablesize = IPS_MAX_SG, |
| 398 | .cmd_per_lun = 3, |
| 399 | .use_clustering = ENABLE_CLUSTERING, |
| 400 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) |
| 401 | .use_new_eh_code = 1, |
| 402 | #endif |
| 403 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) |
| 404 | .highmem_io = 1, |
| 405 | #endif |
| 406 | }; |
| 407 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | |
| 409 | /* This table describes all ServeRAID Adapters */ |
| 410 | static struct pci_device_id ips_pci_table[] = { |
| 411 | { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
| 412 | { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
| 413 | { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
| 414 | { 0, } |
| 415 | }; |
| 416 | |
| 417 | MODULE_DEVICE_TABLE( pci, ips_pci_table ); |
| 418 | |
| 419 | static char ips_hot_plug_name[] = "ips"; |
| 420 | |
| 421 | static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); |
| 422 | static void __devexit ips_remove_device(struct pci_dev *pci_dev); |
| 423 | |
| 424 | static struct pci_driver ips_pci_driver = { |
| 425 | .name = ips_hot_plug_name, |
| 426 | .id_table = ips_pci_table, |
| 427 | .probe = ips_insert_device, |
| 428 | .remove = __devexit_p(ips_remove_device), |
| 429 | }; |
| 430 | |
| 431 | |
| 432 | /* |
| 433 | * Necessary forward function protoypes |
| 434 | */ |
| 435 | static int ips_halt(struct notifier_block *nb, ulong event, void *buf); |
| 436 | |
| 437 | #define MAX_ADAPTER_NAME 15 |
| 438 | |
| 439 | static char ips_adapter_name[][30] = { |
| 440 | "ServeRAID", |
| 441 | "ServeRAID II", |
| 442 | "ServeRAID on motherboard", |
| 443 | "ServeRAID on motherboard", |
| 444 | "ServeRAID 3H", |
| 445 | "ServeRAID 3L", |
| 446 | "ServeRAID 4H", |
| 447 | "ServeRAID 4M", |
| 448 | "ServeRAID 4L", |
| 449 | "ServeRAID 4Mx", |
| 450 | "ServeRAID 4Lx", |
| 451 | "ServeRAID 5i", |
| 452 | "ServeRAID 5i", |
| 453 | "ServeRAID 6M", |
| 454 | "ServeRAID 6i", |
| 455 | "ServeRAID 7t", |
| 456 | "ServeRAID 7k", |
| 457 | "ServeRAID 7M" |
| 458 | }; |
| 459 | |
| 460 | static struct notifier_block ips_notifier = { |
| 461 | ips_halt, NULL, 0 |
| 462 | }; |
| 463 | |
| 464 | /* |
| 465 | * Direction table |
| 466 | */ |
| 467 | static char ips_command_direction[] = { |
| 468 | IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, |
| 469 | IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, |
| 470 | IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 471 | IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, |
| 472 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, |
| 473 | IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, |
| 474 | IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, |
| 475 | IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, |
| 476 | IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, |
| 477 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, |
| 478 | IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, |
| 479 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, |
| 480 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, |
| 481 | IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, |
| 482 | IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, |
| 483 | IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, |
| 484 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 485 | IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 486 | IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 487 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 488 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 489 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 490 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 491 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 492 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 493 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 494 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 495 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 496 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 497 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 498 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 499 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 500 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 501 | IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, |
| 502 | IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, |
| 503 | IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, |
| 504 | IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, |
| 505 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 506 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 507 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 508 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 509 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 510 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 511 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 512 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 513 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 514 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, |
| 515 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 516 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 517 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
| 518 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK |
| 519 | }; |
| 520 | |
| 521 | |
| 522 | /****************************************************************************/ |
| 523 | /* */ |
| 524 | /* Routine Name: ips_setup */ |
| 525 | /* */ |
| 526 | /* Routine Description: */ |
| 527 | /* */ |
| 528 | /* setup parameters to the driver */ |
| 529 | /* */ |
| 530 | /****************************************************************************/ |
| 531 | static int |
| 532 | ips_setup(char *ips_str) |
| 533 | { |
| 534 | |
| 535 | int i; |
| 536 | char *key; |
| 537 | char *value; |
| 538 | IPS_OPTION options[] = { |
| 539 | {"noi2o", &ips_force_i2o, 0}, |
| 540 | {"nommap", &ips_force_memio, 0}, |
| 541 | {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE}, |
| 542 | {"cdboot", &ips_cd_boot, 0}, |
| 543 | {"maxcmds", &MaxLiteCmds, 32}, |
| 544 | }; |
| 545 | |
| 546 | /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ |
| 547 | /* Search for value */ |
| 548 | while ((key = strsep(&ips_str, ",."))) { |
| 549 | if (!*key) |
| 550 | continue; |
| 551 | value = strchr(key, ':'); |
| 552 | if (value) |
| 553 | *value++ = '\0'; |
| 554 | /* |
| 555 | * We now have key/value pairs. |
| 556 | * Update the variables |
| 557 | */ |
| 558 | for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) { |
| 559 | if (strnicmp |
| 560 | (key, options[i].option_name, |
| 561 | strlen(options[i].option_name)) == 0) { |
| 562 | if (value) |
| 563 | *options[i].option_flag = |
| 564 | simple_strtoul(value, NULL, 0); |
| 565 | else |
| 566 | *options[i].option_flag = |
| 567 | options[i].option_value; |
| 568 | break; |
| 569 | } |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | return (1); |
| 574 | } |
| 575 | |
| 576 | __setup("ips=", ips_setup); |
| 577 | |
| 578 | /****************************************************************************/ |
| 579 | /* */ |
| 580 | /* Routine Name: ips_detect */ |
| 581 | /* */ |
| 582 | /* Routine Description: */ |
| 583 | /* */ |
| 584 | /* Detect and initialize the driver */ |
| 585 | /* */ |
| 586 | /* NOTE: this routine is called under the io_request_lock spinlock */ |
| 587 | /* */ |
| 588 | /****************************************************************************/ |
| 589 | static int |
Christoph Hellwig | d0be4a7d | 2005-10-31 18:31:40 +0100 | [diff] [blame] | 590 | ips_detect(struct scsi_host_template * SHT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | { |
| 592 | int i; |
| 593 | |
| 594 | METHOD_TRACE("ips_detect", 1); |
| 595 | |
| 596 | #ifdef MODULE |
| 597 | if (ips) |
| 598 | ips_setup(ips); |
| 599 | #endif |
| 600 | |
| 601 | for (i = 0; i < ips_num_controllers; i++) { |
| 602 | if (ips_register_scsi(i)) |
| 603 | ips_free(ips_ha[i]); |
| 604 | ips_released_controllers++; |
| 605 | } |
| 606 | ips_hotplug = 1; |
| 607 | return (ips_num_controllers); |
| 608 | } |
| 609 | |
| 610 | /****************************************************************************/ |
| 611 | /* configure the function pointers to use the functions that will work */ |
| 612 | /* with the found version of the adapter */ |
| 613 | /****************************************************************************/ |
| 614 | static void |
| 615 | ips_setup_funclist(ips_ha_t * ha) |
| 616 | { |
| 617 | |
| 618 | /* |
| 619 | * Setup Functions |
| 620 | */ |
| 621 | if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { |
| 622 | /* morpheus / marco / sebring */ |
| 623 | ha->func.isintr = ips_isintr_morpheus; |
| 624 | ha->func.isinit = ips_isinit_morpheus; |
| 625 | ha->func.issue = ips_issue_i2o_memio; |
| 626 | ha->func.init = ips_init_morpheus; |
| 627 | ha->func.statupd = ips_statupd_morpheus; |
| 628 | ha->func.reset = ips_reset_morpheus; |
| 629 | ha->func.intr = ips_intr_morpheus; |
| 630 | ha->func.enableint = ips_enable_int_morpheus; |
| 631 | } else if (IPS_USE_MEMIO(ha)) { |
| 632 | /* copperhead w/MEMIO */ |
| 633 | ha->func.isintr = ips_isintr_copperhead_memio; |
| 634 | ha->func.isinit = ips_isinit_copperhead_memio; |
| 635 | ha->func.init = ips_init_copperhead_memio; |
| 636 | ha->func.statupd = ips_statupd_copperhead_memio; |
| 637 | ha->func.statinit = ips_statinit_memio; |
| 638 | ha->func.reset = ips_reset_copperhead_memio; |
| 639 | ha->func.intr = ips_intr_copperhead; |
| 640 | ha->func.erasebios = ips_erase_bios_memio; |
| 641 | ha->func.programbios = ips_program_bios_memio; |
| 642 | ha->func.verifybios = ips_verify_bios_memio; |
| 643 | ha->func.enableint = ips_enable_int_copperhead_memio; |
| 644 | if (IPS_USE_I2O_DELIVER(ha)) |
| 645 | ha->func.issue = ips_issue_i2o_memio; |
| 646 | else |
| 647 | ha->func.issue = ips_issue_copperhead_memio; |
| 648 | } else { |
| 649 | /* copperhead */ |
| 650 | ha->func.isintr = ips_isintr_copperhead; |
| 651 | ha->func.isinit = ips_isinit_copperhead; |
| 652 | ha->func.init = ips_init_copperhead; |
| 653 | ha->func.statupd = ips_statupd_copperhead; |
| 654 | ha->func.statinit = ips_statinit; |
| 655 | ha->func.reset = ips_reset_copperhead; |
| 656 | ha->func.intr = ips_intr_copperhead; |
| 657 | ha->func.erasebios = ips_erase_bios; |
| 658 | ha->func.programbios = ips_program_bios; |
| 659 | ha->func.verifybios = ips_verify_bios; |
| 660 | ha->func.enableint = ips_enable_int_copperhead; |
| 661 | |
| 662 | if (IPS_USE_I2O_DELIVER(ha)) |
| 663 | ha->func.issue = ips_issue_i2o; |
| 664 | else |
| 665 | ha->func.issue = ips_issue_copperhead; |
| 666 | } |
| 667 | } |
| 668 | |
| 669 | /****************************************************************************/ |
| 670 | /* */ |
| 671 | /* Routine Name: ips_release */ |
| 672 | /* */ |
| 673 | /* Routine Description: */ |
| 674 | /* */ |
| 675 | /* Remove a driver */ |
| 676 | /* */ |
| 677 | /****************************************************************************/ |
| 678 | static int |
| 679 | ips_release(struct Scsi_Host *sh) |
| 680 | { |
| 681 | ips_scb_t *scb; |
| 682 | ips_ha_t *ha; |
| 683 | int i; |
| 684 | |
| 685 | METHOD_TRACE("ips_release", 1); |
| 686 | |
| 687 | for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; |
| 688 | |
| 689 | if (i == IPS_MAX_ADAPTERS) { |
| 690 | printk(KERN_WARNING |
| 691 | "(%s) release, invalid Scsi_Host pointer.\n", ips_name); |
| 692 | BUG(); |
| 693 | return (FALSE); |
| 694 | } |
| 695 | |
| 696 | ha = IPS_HA(sh); |
| 697 | |
| 698 | if (!ha) |
| 699 | return (FALSE); |
| 700 | |
| 701 | /* flush the cache on the controller */ |
| 702 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 703 | |
| 704 | ips_init_scb(ha, scb); |
| 705 | |
| 706 | scb->timeout = ips_cmd_timeout; |
| 707 | scb->cdb[0] = IPS_CMD_FLUSH; |
| 708 | |
| 709 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
| 710 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
| 711 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
| 712 | scb->cmd.flush_cache.reserved = 0; |
| 713 | scb->cmd.flush_cache.reserved2 = 0; |
| 714 | scb->cmd.flush_cache.reserved3 = 0; |
| 715 | scb->cmd.flush_cache.reserved4 = 0; |
| 716 | |
| 717 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); |
| 718 | |
| 719 | /* send command */ |
| 720 | if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) |
| 721 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n"); |
| 722 | |
| 723 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n"); |
| 724 | |
| 725 | ips_sh[i] = NULL; |
| 726 | ips_ha[i] = NULL; |
| 727 | |
| 728 | /* free extra memory */ |
| 729 | ips_free(ha); |
| 730 | |
| 731 | /* Free I/O Region */ |
| 732 | if (ha->io_addr) |
| 733 | release_region(ha->io_addr, ha->io_len); |
| 734 | |
| 735 | /* free IRQ */ |
| 736 | free_irq(ha->irq, ha); |
| 737 | |
| 738 | IPS_REMOVE_HOST(sh); |
| 739 | scsi_host_put(sh); |
| 740 | |
| 741 | ips_released_controllers++; |
| 742 | |
| 743 | return (FALSE); |
| 744 | } |
| 745 | |
| 746 | /****************************************************************************/ |
| 747 | /* */ |
| 748 | /* Routine Name: ips_halt */ |
| 749 | /* */ |
| 750 | /* Routine Description: */ |
| 751 | /* */ |
| 752 | /* Perform cleanup when the system reboots */ |
| 753 | /* */ |
| 754 | /****************************************************************************/ |
| 755 | static int |
| 756 | ips_halt(struct notifier_block *nb, ulong event, void *buf) |
| 757 | { |
| 758 | ips_scb_t *scb; |
| 759 | ips_ha_t *ha; |
| 760 | int i; |
| 761 | |
| 762 | if ((event != SYS_RESTART) && (event != SYS_HALT) && |
| 763 | (event != SYS_POWER_OFF)) |
| 764 | return (NOTIFY_DONE); |
| 765 | |
| 766 | for (i = 0; i < ips_next_controller; i++) { |
| 767 | ha = (ips_ha_t *) ips_ha[i]; |
| 768 | |
| 769 | if (!ha) |
| 770 | continue; |
| 771 | |
| 772 | if (!ha->active) |
| 773 | continue; |
| 774 | |
| 775 | /* flush the cache on the controller */ |
| 776 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 777 | |
| 778 | ips_init_scb(ha, scb); |
| 779 | |
| 780 | scb->timeout = ips_cmd_timeout; |
| 781 | scb->cdb[0] = IPS_CMD_FLUSH; |
| 782 | |
| 783 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
| 784 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
| 785 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
| 786 | scb->cmd.flush_cache.reserved = 0; |
| 787 | scb->cmd.flush_cache.reserved2 = 0; |
| 788 | scb->cmd.flush_cache.reserved3 = 0; |
| 789 | scb->cmd.flush_cache.reserved4 = 0; |
| 790 | |
| 791 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); |
| 792 | |
| 793 | /* send command */ |
| 794 | if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == |
| 795 | IPS_FAILURE) |
| 796 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 797 | "Incomplete Flush.\n"); |
| 798 | else |
| 799 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 800 | "Flushing Complete.\n"); |
| 801 | } |
| 802 | |
| 803 | return (NOTIFY_OK); |
| 804 | } |
| 805 | |
| 806 | /****************************************************************************/ |
| 807 | /* */ |
| 808 | /* Routine Name: ips_eh_abort */ |
| 809 | /* */ |
| 810 | /* Routine Description: */ |
| 811 | /* */ |
| 812 | /* Abort a command (using the new error code stuff) */ |
| 813 | /* Note: this routine is called under the io_request_lock */ |
| 814 | /****************************************************************************/ |
| 815 | int |
| 816 | ips_eh_abort(Scsi_Cmnd * SC) |
| 817 | { |
| 818 | ips_ha_t *ha; |
| 819 | ips_copp_wait_item_t *item; |
| 820 | int ret; |
Jeff Garzik | 8fa728a | 2005-05-28 07:54:40 -0400 | [diff] [blame] | 821 | unsigned long cpu_flags; |
| 822 | struct Scsi_Host *host; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | |
| 824 | METHOD_TRACE("ips_eh_abort", 1); |
| 825 | |
| 826 | if (!SC) |
| 827 | return (FAILED); |
| 828 | |
Jeff Garzik | 8fa728a | 2005-05-28 07:54:40 -0400 | [diff] [blame] | 829 | host = SC->device->host; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | ha = (ips_ha_t *) SC->device->host->hostdata; |
| 831 | |
| 832 | if (!ha) |
| 833 | return (FAILED); |
| 834 | |
| 835 | if (!ha->active) |
| 836 | return (FAILED); |
| 837 | |
Jeff Garzik | 8fa728a | 2005-05-28 07:54:40 -0400 | [diff] [blame] | 838 | IPS_LOCK_SAVE(host->host_lock, cpu_flags); |
| 839 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 840 | /* See if the command is on the copp queue */ |
| 841 | item = ha->copp_waitlist.head; |
| 842 | while ((item) && (item->scsi_cmd != SC)) |
| 843 | item = item->next; |
| 844 | |
| 845 | if (item) { |
| 846 | /* Found it */ |
| 847 | ips_removeq_copp(&ha->copp_waitlist, item); |
| 848 | ret = (SUCCESS); |
| 849 | |
| 850 | /* See if the command is on the wait queue */ |
| 851 | } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { |
| 852 | /* command not sent yet */ |
| 853 | ret = (SUCCESS); |
| 854 | } else { |
| 855 | /* command must have already been sent */ |
| 856 | ret = (FAILED); |
| 857 | } |
Jeff Garzik | 8fa728a | 2005-05-28 07:54:40 -0400 | [diff] [blame] | 858 | |
| 859 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 860 | return ret; |
| 861 | } |
| 862 | |
| 863 | /****************************************************************************/ |
| 864 | /* */ |
| 865 | /* Routine Name: ips_eh_reset */ |
| 866 | /* */ |
| 867 | /* Routine Description: */ |
| 868 | /* */ |
| 869 | /* Reset the controller (with new eh error code) */ |
| 870 | /* */ |
| 871 | /* NOTE: this routine is called under the io_request_lock spinlock */ |
| 872 | /* */ |
| 873 | /****************************************************************************/ |
| 874 | static int |
Jeff Garzik | df0ae24 | 2005-05-28 07:57:14 -0400 | [diff] [blame] | 875 | __ips_eh_reset(Scsi_Cmnd * SC) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 876 | { |
| 877 | int ret; |
| 878 | int i; |
| 879 | ips_ha_t *ha; |
| 880 | ips_scb_t *scb; |
| 881 | ips_copp_wait_item_t *item; |
| 882 | |
| 883 | METHOD_TRACE("ips_eh_reset", 1); |
| 884 | |
| 885 | #ifdef NO_IPS_RESET |
| 886 | return (FAILED); |
| 887 | #else |
| 888 | |
| 889 | if (!SC) { |
| 890 | DEBUG(1, "Reset called with NULL scsi command"); |
| 891 | |
| 892 | return (FAILED); |
| 893 | } |
| 894 | |
| 895 | ha = (ips_ha_t *) SC->device->host->hostdata; |
| 896 | |
| 897 | if (!ha) { |
| 898 | DEBUG(1, "Reset called with NULL ha struct"); |
| 899 | |
| 900 | return (FAILED); |
| 901 | } |
| 902 | |
| 903 | if (!ha->active) |
| 904 | return (FAILED); |
| 905 | |
| 906 | /* See if the command is on the copp queue */ |
| 907 | item = ha->copp_waitlist.head; |
| 908 | while ((item) && (item->scsi_cmd != SC)) |
| 909 | item = item->next; |
| 910 | |
| 911 | if (item) { |
| 912 | /* Found it */ |
| 913 | ips_removeq_copp(&ha->copp_waitlist, item); |
| 914 | return (SUCCESS); |
| 915 | } |
| 916 | |
| 917 | /* See if the command is on the wait queue */ |
| 918 | if (ips_removeq_wait(&ha->scb_waitlist, SC)) { |
| 919 | /* command not sent yet */ |
| 920 | return (SUCCESS); |
| 921 | } |
| 922 | |
| 923 | /* An explanation for the casual observer: */ |
| 924 | /* Part of the function of a RAID controller is automatic error */ |
| 925 | /* detection and recovery. As such, the only problem that physically */ |
| 926 | /* resetting an adapter will ever fix is when, for some reason, */ |
| 927 | /* the driver is not successfully communicating with the adapter. */ |
| 928 | /* Therefore, we will attempt to flush this adapter. If that succeeds, */ |
| 929 | /* then there's no real purpose in a physical reset. This will complete */ |
| 930 | /* much faster and avoids any problems that might be caused by a */ |
| 931 | /* physical reset ( such as having to fail all the outstanding I/O's ). */ |
| 932 | |
| 933 | if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ |
| 934 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 935 | |
| 936 | ips_init_scb(ha, scb); |
| 937 | |
| 938 | scb->timeout = ips_cmd_timeout; |
| 939 | scb->cdb[0] = IPS_CMD_FLUSH; |
| 940 | |
| 941 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
| 942 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
| 943 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
| 944 | scb->cmd.flush_cache.reserved = 0; |
| 945 | scb->cmd.flush_cache.reserved2 = 0; |
| 946 | scb->cmd.flush_cache.reserved3 = 0; |
| 947 | scb->cmd.flush_cache.reserved4 = 0; |
| 948 | |
| 949 | /* Attempt the flush command */ |
| 950 | ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); |
| 951 | if (ret == IPS_SUCCESS) { |
| 952 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
| 953 | "Reset Request - Flushed Cache\n"); |
| 954 | return (SUCCESS); |
| 955 | } |
| 956 | } |
| 957 | |
| 958 | /* Either we can't communicate with the adapter or it's an IOCTL request */ |
| 959 | /* from a utility. A physical reset is needed at this point. */ |
| 960 | |
| 961 | ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ |
| 962 | |
| 963 | /* |
| 964 | * command must have already been sent |
| 965 | * reset the controller |
| 966 | */ |
| 967 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n"); |
| 968 | ret = (*ha->func.reset) (ha); |
| 969 | |
| 970 | if (!ret) { |
| 971 | Scsi_Cmnd *scsi_cmd; |
| 972 | |
| 973 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
| 974 | "Controller reset failed - controller now offline.\n"); |
| 975 | |
| 976 | /* Now fail all of the active commands */ |
| 977 | DEBUG_VAR(1, "(%s%d) Failing active commands", |
| 978 | ips_name, ha->host_num); |
| 979 | |
| 980 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
| 981 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 982 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 983 | ips_freescb(ha, scb); |
| 984 | } |
| 985 | |
| 986 | /* Now fail all of the pending commands */ |
| 987 | DEBUG_VAR(1, "(%s%d) Failing pending commands", |
| 988 | ips_name, ha->host_num); |
| 989 | |
| 990 | while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { |
| 991 | scsi_cmd->result = DID_ERROR; |
| 992 | scsi_cmd->scsi_done(scsi_cmd); |
| 993 | } |
| 994 | |
| 995 | ha->active = FALSE; |
| 996 | return (FAILED); |
| 997 | } |
| 998 | |
| 999 | if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { |
| 1000 | Scsi_Cmnd *scsi_cmd; |
| 1001 | |
| 1002 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
| 1003 | "Controller reset failed - controller now offline.\n"); |
| 1004 | |
| 1005 | /* Now fail all of the active commands */ |
| 1006 | DEBUG_VAR(1, "(%s%d) Failing active commands", |
| 1007 | ips_name, ha->host_num); |
| 1008 | |
| 1009 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
| 1010 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 1011 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 1012 | ips_freescb(ha, scb); |
| 1013 | } |
| 1014 | |
| 1015 | /* Now fail all of the pending commands */ |
| 1016 | DEBUG_VAR(1, "(%s%d) Failing pending commands", |
| 1017 | ips_name, ha->host_num); |
| 1018 | |
| 1019 | while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { |
| 1020 | scsi_cmd->result = DID_ERROR << 16; |
| 1021 | scsi_cmd->scsi_done(scsi_cmd); |
| 1022 | } |
| 1023 | |
| 1024 | ha->active = FALSE; |
| 1025 | return (FAILED); |
| 1026 | } |
| 1027 | |
| 1028 | /* FFDC */ |
| 1029 | if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { |
| 1030 | struct timeval tv; |
| 1031 | |
| 1032 | do_gettimeofday(&tv); |
| 1033 | ha->last_ffdc = tv.tv_sec; |
| 1034 | ha->reset_count++; |
| 1035 | ips_ffdc_reset(ha, IPS_INTR_IORL); |
| 1036 | } |
| 1037 | |
| 1038 | /* Now fail all of the active commands */ |
| 1039 | DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num); |
| 1040 | |
| 1041 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
| 1042 | scb->scsi_cmd->result = |
| 1043 | (DID_RESET << 16) | (SUGGEST_RETRY << 24); |
| 1044 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 1045 | ips_freescb(ha, scb); |
| 1046 | } |
| 1047 | |
| 1048 | /* Reset DCDB active command bits */ |
| 1049 | for (i = 1; i < ha->nbus; i++) |
| 1050 | ha->dcdb_active[i - 1] = 0; |
| 1051 | |
| 1052 | /* Reset the number of active IOCTLs */ |
| 1053 | ha->num_ioctl = 0; |
| 1054 | |
| 1055 | ips_next(ha, IPS_INTR_IORL); |
| 1056 | |
| 1057 | return (SUCCESS); |
| 1058 | #endif /* NO_IPS_RESET */ |
| 1059 | |
| 1060 | } |
| 1061 | |
Jeff Garzik | df0ae24 | 2005-05-28 07:57:14 -0400 | [diff] [blame] | 1062 | static int |
| 1063 | ips_eh_reset(Scsi_Cmnd * SC) |
| 1064 | { |
| 1065 | int rc; |
| 1066 | |
| 1067 | spin_lock_irq(SC->device->host->host_lock); |
| 1068 | rc = __ips_eh_reset(SC); |
| 1069 | spin_unlock_irq(SC->device->host->host_lock); |
| 1070 | |
| 1071 | return rc; |
| 1072 | } |
| 1073 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1074 | /****************************************************************************/ |
| 1075 | /* */ |
| 1076 | /* Routine Name: ips_queue */ |
| 1077 | /* */ |
| 1078 | /* Routine Description: */ |
| 1079 | /* */ |
| 1080 | /* Send a command to the controller */ |
| 1081 | /* */ |
| 1082 | /* NOTE: */ |
| 1083 | /* Linux obtains io_request_lock before calling this function */ |
| 1084 | /* */ |
| 1085 | /****************************************************************************/ |
| 1086 | static int |
| 1087 | ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *)) |
| 1088 | { |
| 1089 | ips_ha_t *ha; |
| 1090 | ips_passthru_t *pt; |
| 1091 | |
| 1092 | METHOD_TRACE("ips_queue", 1); |
| 1093 | |
| 1094 | ha = (ips_ha_t *) SC->device->host->hostdata; |
| 1095 | |
| 1096 | if (!ha) |
| 1097 | return (1); |
| 1098 | |
| 1099 | if (!ha->active) |
| 1100 | return (DID_ERROR); |
| 1101 | |
| 1102 | if (ips_is_passthru(SC)) { |
| 1103 | if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { |
| 1104 | SC->result = DID_BUS_BUSY << 16; |
| 1105 | done(SC); |
| 1106 | |
| 1107 | return (0); |
| 1108 | } |
| 1109 | } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { |
| 1110 | SC->result = DID_BUS_BUSY << 16; |
| 1111 | done(SC); |
| 1112 | |
| 1113 | return (0); |
| 1114 | } |
| 1115 | |
| 1116 | SC->scsi_done = done; |
| 1117 | |
| 1118 | DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)", |
| 1119 | ips_name, |
| 1120 | ha->host_num, |
| 1121 | SC->cmnd[0], |
| 1122 | SC->device->channel, SC->device->id, SC->device->lun); |
| 1123 | |
| 1124 | /* Check for command to initiator IDs */ |
Jeff Garzik | 422c0d6 | 2005-10-24 18:05:09 -0400 | [diff] [blame] | 1125 | if ((scmd_channel(SC) > 0) |
| 1126 | && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | SC->result = DID_NO_CONNECT << 16; |
| 1128 | done(SC); |
| 1129 | |
| 1130 | return (0); |
| 1131 | } |
| 1132 | |
| 1133 | if (ips_is_passthru(SC)) { |
| 1134 | |
| 1135 | ips_copp_wait_item_t *scratch; |
| 1136 | |
| 1137 | /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ |
| 1138 | /* There can never be any system activity ( network or disk ), but check */ |
| 1139 | /* anyway just as a good practice. */ |
| 1140 | pt = (ips_passthru_t *) SC->request_buffer; |
| 1141 | if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && |
| 1142 | (pt->CoppCP.cmd.reset.adapter_flag == 1)) { |
| 1143 | if (ha->scb_activelist.count != 0) { |
| 1144 | SC->result = DID_BUS_BUSY << 16; |
| 1145 | done(SC); |
| 1146 | return (0); |
| 1147 | } |
| 1148 | ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ |
| 1149 | ips_eh_reset(SC); |
| 1150 | SC->result = DID_OK << 16; |
| 1151 | SC->scsi_done(SC); |
| 1152 | return (0); |
| 1153 | } |
| 1154 | |
| 1155 | /* allocate space for the scribble */ |
| 1156 | scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC); |
| 1157 | |
| 1158 | if (!scratch) { |
| 1159 | SC->result = DID_ERROR << 16; |
| 1160 | done(SC); |
| 1161 | |
| 1162 | return (0); |
| 1163 | } |
| 1164 | |
| 1165 | scratch->scsi_cmd = SC; |
| 1166 | scratch->next = NULL; |
| 1167 | |
| 1168 | ips_putq_copp_tail(&ha->copp_waitlist, scratch); |
| 1169 | } else { |
| 1170 | ips_putq_wait_tail(&ha->scb_waitlist, SC); |
| 1171 | } |
| 1172 | |
| 1173 | ips_next(ha, IPS_INTR_IORL); |
| 1174 | |
| 1175 | return (0); |
| 1176 | } |
| 1177 | |
| 1178 | /****************************************************************************/ |
| 1179 | /* */ |
| 1180 | /* Routine Name: ips_biosparam */ |
| 1181 | /* */ |
| 1182 | /* Routine Description: */ |
| 1183 | /* */ |
| 1184 | /* Set bios geometry for the controller */ |
| 1185 | /* */ |
| 1186 | /****************************************************************************/ |
| 1187 | static int |
| 1188 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) |
| 1189 | ips_biosparam(Disk * disk, kdev_t dev, int geom[]) |
| 1190 | { |
| 1191 | ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata; |
| 1192 | unsigned long capacity = disk->capacity; |
| 1193 | #else |
| 1194 | ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, |
| 1195 | sector_t capacity, int geom[]) |
| 1196 | { |
| 1197 | ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; |
| 1198 | #endif |
| 1199 | int heads; |
| 1200 | int sectors; |
| 1201 | int cylinders; |
| 1202 | |
| 1203 | METHOD_TRACE("ips_biosparam", 1); |
| 1204 | |
| 1205 | if (!ha) |
| 1206 | /* ?!?! host adater info invalid */ |
| 1207 | return (0); |
| 1208 | |
| 1209 | if (!ha->active) |
| 1210 | return (0); |
| 1211 | |
| 1212 | if (!ips_read_adapter_status(ha, IPS_INTR_ON)) |
| 1213 | /* ?!?! Enquiry command failed */ |
| 1214 | return (0); |
| 1215 | |
| 1216 | if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { |
| 1217 | heads = IPS_NORM_HEADS; |
| 1218 | sectors = IPS_NORM_SECTORS; |
| 1219 | } else { |
| 1220 | heads = IPS_COMP_HEADS; |
| 1221 | sectors = IPS_COMP_SECTORS; |
| 1222 | } |
| 1223 | |
| 1224 | cylinders = (unsigned long) capacity / (heads * sectors); |
| 1225 | |
| 1226 | DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d", |
| 1227 | heads, sectors, cylinders); |
| 1228 | |
| 1229 | geom[0] = heads; |
| 1230 | geom[1] = sectors; |
| 1231 | geom[2] = cylinders; |
| 1232 | |
| 1233 | return (0); |
| 1234 | } |
| 1235 | |
| 1236 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) |
| 1237 | |
| 1238 | /* ips_proc24_info is a wrapper around ips_proc_info * |
| 1239 | * for compatibility with the 2.4 scsi parameters */ |
| 1240 | static int |
| 1241 | ips_proc24_info(char *buffer, char **start, off_t offset, int length, |
| 1242 | int hostno, int func) |
| 1243 | { |
| 1244 | int i; |
| 1245 | |
| 1246 | for (i = 0; i < ips_next_controller; i++) { |
| 1247 | if (ips_sh[i] && ips_sh[i]->host_no == hostno) { |
| 1248 | return ips_proc_info(ips_sh[i], buffer, start, |
| 1249 | offset, length, func); |
| 1250 | } |
| 1251 | } |
| 1252 | return -EINVAL; |
| 1253 | } |
| 1254 | |
| 1255 | /****************************************************************************/ |
| 1256 | /* */ |
| 1257 | /* Routine Name: ips_select_queue_depth */ |
| 1258 | /* */ |
| 1259 | /* Routine Description: */ |
| 1260 | /* */ |
| 1261 | /* Select queue depths for the devices on the contoller */ |
| 1262 | /* */ |
| 1263 | /****************************************************************************/ |
| 1264 | static void |
Christoph Hellwig | f64a181 | 2005-10-31 18:32:08 +0100 | [diff] [blame] | 1265 | ips_select_queue_depth(struct Scsi_Host *host, struct scsi_device * scsi_devs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | { |
Christoph Hellwig | f64a181 | 2005-10-31 18:32:08 +0100 | [diff] [blame] | 1267 | struct scsi_device *device; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | ips_ha_t *ha; |
| 1269 | int count = 0; |
| 1270 | int min; |
| 1271 | |
| 1272 | ha = IPS_HA(host); |
| 1273 | min = ha->max_cmds / 4; |
| 1274 | |
| 1275 | for (device = scsi_devs; device; device = device->next) { |
| 1276 | if (device->host == host) { |
| 1277 | if ((device->channel == 0) && (device->type == 0)) |
| 1278 | count++; |
| 1279 | } |
| 1280 | } |
| 1281 | |
| 1282 | for (device = scsi_devs; device; device = device->next) { |
| 1283 | if (device->host == host) { |
| 1284 | if ((device->channel == 0) && (device->type == 0)) { |
| 1285 | device->queue_depth = |
| 1286 | (ha->max_cmds - 1) / count; |
| 1287 | if (device->queue_depth < min) |
| 1288 | device->queue_depth = min; |
| 1289 | } else { |
| 1290 | device->queue_depth = 2; |
| 1291 | } |
| 1292 | |
| 1293 | if (device->queue_depth < 2) |
| 1294 | device->queue_depth = 2; |
| 1295 | } |
| 1296 | } |
| 1297 | } |
| 1298 | |
| 1299 | #else |
| 1300 | /****************************************************************************/ |
| 1301 | /* */ |
| 1302 | /* Routine Name: ips_slave_configure */ |
| 1303 | /* */ |
| 1304 | /* Routine Description: */ |
| 1305 | /* */ |
| 1306 | /* Set queue depths on devices once scan is complete */ |
| 1307 | /* */ |
| 1308 | /****************************************************************************/ |
| 1309 | static int |
Christoph Hellwig | f64a181 | 2005-10-31 18:32:08 +0100 | [diff] [blame] | 1310 | ips_slave_configure(struct scsi_device * SDptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1311 | { |
| 1312 | ips_ha_t *ha; |
| 1313 | int min; |
| 1314 | |
| 1315 | ha = IPS_HA(SDptr->host); |
| 1316 | if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { |
| 1317 | min = ha->max_cmds / 2; |
| 1318 | if (ha->enq->ucLogDriveCount <= 2) |
| 1319 | min = ha->max_cmds - 1; |
| 1320 | scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min); |
| 1321 | } |
Jack Hammer | 560c26c | 2006-01-13 10:06:50 -0500 | [diff] [blame] | 1322 | |
| 1323 | SDptr->skip_ms_page_8 = 1; |
| 1324 | SDptr->skip_ms_page_3f = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | return 0; |
| 1326 | } |
| 1327 | #endif |
| 1328 | |
| 1329 | /****************************************************************************/ |
| 1330 | /* */ |
| 1331 | /* Routine Name: do_ipsintr */ |
| 1332 | /* */ |
| 1333 | /* Routine Description: */ |
| 1334 | /* */ |
| 1335 | /* Wrapper for the interrupt handler */ |
| 1336 | /* */ |
| 1337 | /****************************************************************************/ |
| 1338 | static irqreturn_t |
| 1339 | do_ipsintr(int irq, void *dev_id, struct pt_regs * regs) |
| 1340 | { |
| 1341 | ips_ha_t *ha; |
| 1342 | unsigned long cpu_flags; |
| 1343 | struct Scsi_Host *host; |
| 1344 | int irqstatus; |
| 1345 | |
| 1346 | METHOD_TRACE("do_ipsintr", 2); |
| 1347 | |
| 1348 | ha = (ips_ha_t *) dev_id; |
| 1349 | if (!ha) |
| 1350 | return IRQ_NONE; |
| 1351 | host = ips_sh[ha->host_num]; |
| 1352 | /* interrupt during initialization */ |
| 1353 | if (!host) { |
| 1354 | (*ha->func.intr) (ha); |
| 1355 | return IRQ_HANDLED; |
| 1356 | } |
| 1357 | |
| 1358 | IPS_LOCK_SAVE(host->host_lock, cpu_flags); |
| 1359 | |
| 1360 | if (!ha->active) { |
| 1361 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); |
| 1362 | return IRQ_HANDLED; |
| 1363 | } |
| 1364 | |
| 1365 | irqstatus = (*ha->func.intr) (ha); |
| 1366 | |
| 1367 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); |
| 1368 | |
| 1369 | /* start the next command */ |
| 1370 | ips_next(ha, IPS_INTR_ON); |
| 1371 | return IRQ_RETVAL(irqstatus); |
| 1372 | } |
| 1373 | |
| 1374 | /****************************************************************************/ |
| 1375 | /* */ |
| 1376 | /* Routine Name: ips_intr_copperhead */ |
| 1377 | /* */ |
| 1378 | /* Routine Description: */ |
| 1379 | /* */ |
| 1380 | /* Polling interrupt handler */ |
| 1381 | /* */ |
| 1382 | /* ASSUMES interrupts are disabled */ |
| 1383 | /* */ |
| 1384 | /****************************************************************************/ |
| 1385 | int |
| 1386 | ips_intr_copperhead(ips_ha_t * ha) |
| 1387 | { |
| 1388 | ips_stat_t *sp; |
| 1389 | ips_scb_t *scb; |
| 1390 | IPS_STATUS cstatus; |
| 1391 | int intrstatus; |
| 1392 | |
| 1393 | METHOD_TRACE("ips_intr", 2); |
| 1394 | |
| 1395 | if (!ha) |
| 1396 | return 0; |
| 1397 | |
| 1398 | if (!ha->active) |
| 1399 | return 0; |
| 1400 | |
| 1401 | intrstatus = (*ha->func.isintr) (ha); |
| 1402 | |
| 1403 | if (!intrstatus) { |
| 1404 | /* |
| 1405 | * Unexpected/Shared interrupt |
| 1406 | */ |
| 1407 | |
| 1408 | return 0; |
| 1409 | } |
| 1410 | |
| 1411 | while (TRUE) { |
| 1412 | sp = &ha->sp; |
| 1413 | |
| 1414 | intrstatus = (*ha->func.isintr) (ha); |
| 1415 | |
| 1416 | if (!intrstatus) |
| 1417 | break; |
| 1418 | else |
| 1419 | cstatus.value = (*ha->func.statupd) (ha); |
| 1420 | |
| 1421 | if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { |
| 1422 | /* Spurious Interupt ? */ |
| 1423 | continue; |
| 1424 | } |
| 1425 | |
| 1426 | ips_chkstatus(ha, &cstatus); |
| 1427 | scb = (ips_scb_t *) sp->scb_addr; |
| 1428 | |
| 1429 | /* |
| 1430 | * use the callback function to finish things up |
| 1431 | * NOTE: interrupts are OFF for this |
| 1432 | */ |
| 1433 | (*scb->callback) (ha, scb); |
| 1434 | } /* end while */ |
| 1435 | return 1; |
| 1436 | } |
| 1437 | |
| 1438 | /****************************************************************************/ |
| 1439 | /* */ |
| 1440 | /* Routine Name: ips_intr_morpheus */ |
| 1441 | /* */ |
| 1442 | /* Routine Description: */ |
| 1443 | /* */ |
| 1444 | /* Polling interrupt handler */ |
| 1445 | /* */ |
| 1446 | /* ASSUMES interrupts are disabled */ |
| 1447 | /* */ |
| 1448 | /****************************************************************************/ |
| 1449 | int |
| 1450 | ips_intr_morpheus(ips_ha_t * ha) |
| 1451 | { |
| 1452 | ips_stat_t *sp; |
| 1453 | ips_scb_t *scb; |
| 1454 | IPS_STATUS cstatus; |
| 1455 | int intrstatus; |
| 1456 | |
| 1457 | METHOD_TRACE("ips_intr_morpheus", 2); |
| 1458 | |
| 1459 | if (!ha) |
| 1460 | return 0; |
| 1461 | |
| 1462 | if (!ha->active) |
| 1463 | return 0; |
| 1464 | |
| 1465 | intrstatus = (*ha->func.isintr) (ha); |
| 1466 | |
| 1467 | if (!intrstatus) { |
| 1468 | /* |
| 1469 | * Unexpected/Shared interrupt |
| 1470 | */ |
| 1471 | |
| 1472 | return 0; |
| 1473 | } |
| 1474 | |
| 1475 | while (TRUE) { |
| 1476 | sp = &ha->sp; |
| 1477 | |
| 1478 | intrstatus = (*ha->func.isintr) (ha); |
| 1479 | |
| 1480 | if (!intrstatus) |
| 1481 | break; |
| 1482 | else |
| 1483 | cstatus.value = (*ha->func.statupd) (ha); |
| 1484 | |
| 1485 | if (cstatus.value == 0xffffffff) |
| 1486 | /* No more to process */ |
| 1487 | break; |
| 1488 | |
| 1489 | if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { |
| 1490 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 1491 | "Spurious interrupt; no ccb.\n"); |
| 1492 | |
| 1493 | continue; |
| 1494 | } |
| 1495 | |
| 1496 | ips_chkstatus(ha, &cstatus); |
| 1497 | scb = (ips_scb_t *) sp->scb_addr; |
| 1498 | |
| 1499 | /* |
| 1500 | * use the callback function to finish things up |
| 1501 | * NOTE: interrupts are OFF for this |
| 1502 | */ |
| 1503 | (*scb->callback) (ha, scb); |
| 1504 | } /* end while */ |
| 1505 | return 1; |
| 1506 | } |
| 1507 | |
| 1508 | /****************************************************************************/ |
| 1509 | /* */ |
| 1510 | /* Routine Name: ips_info */ |
| 1511 | /* */ |
| 1512 | /* Routine Description: */ |
| 1513 | /* */ |
| 1514 | /* Return info about the driver */ |
| 1515 | /* */ |
| 1516 | /****************************************************************************/ |
| 1517 | static const char * |
| 1518 | ips_info(struct Scsi_Host *SH) |
| 1519 | { |
| 1520 | static char buffer[256]; |
| 1521 | char *bp; |
| 1522 | ips_ha_t *ha; |
| 1523 | |
| 1524 | METHOD_TRACE("ips_info", 1); |
| 1525 | |
| 1526 | ha = IPS_HA(SH); |
| 1527 | |
| 1528 | if (!ha) |
| 1529 | return (NULL); |
| 1530 | |
| 1531 | bp = &buffer[0]; |
| 1532 | memset(bp, 0, sizeof (buffer)); |
| 1533 | |
| 1534 | sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ", |
| 1535 | IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); |
| 1536 | |
| 1537 | if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { |
| 1538 | strcat(bp, " <"); |
| 1539 | strcat(bp, ips_adapter_name[ha->ad_type - 1]); |
| 1540 | strcat(bp, ">"); |
| 1541 | } |
| 1542 | |
| 1543 | return (bp); |
| 1544 | } |
| 1545 | |
| 1546 | /****************************************************************************/ |
| 1547 | /* */ |
| 1548 | /* Routine Name: ips_proc_info */ |
| 1549 | /* */ |
| 1550 | /* Routine Description: */ |
| 1551 | /* */ |
| 1552 | /* The passthru interface for the driver */ |
| 1553 | /* */ |
| 1554 | /****************************************************************************/ |
| 1555 | static int |
| 1556 | ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset, |
| 1557 | int length, int func) |
| 1558 | { |
| 1559 | int i; |
| 1560 | int ret; |
| 1561 | ips_ha_t *ha = NULL; |
| 1562 | |
| 1563 | METHOD_TRACE("ips_proc_info", 1); |
| 1564 | |
| 1565 | /* Find our host structure */ |
| 1566 | for (i = 0; i < ips_next_controller; i++) { |
| 1567 | if (ips_sh[i]) { |
| 1568 | if (ips_sh[i] == host) { |
| 1569 | ha = (ips_ha_t *) ips_sh[i]->hostdata; |
| 1570 | break; |
| 1571 | } |
| 1572 | } |
| 1573 | } |
| 1574 | |
| 1575 | if (!ha) |
| 1576 | return (-EINVAL); |
| 1577 | |
| 1578 | if (func) { |
| 1579 | /* write */ |
| 1580 | return (0); |
| 1581 | } else { |
| 1582 | /* read */ |
| 1583 | if (start) |
| 1584 | *start = buffer; |
| 1585 | |
| 1586 | ret = ips_host_info(ha, buffer, offset, length); |
| 1587 | |
| 1588 | return (ret); |
| 1589 | } |
| 1590 | } |
| 1591 | |
| 1592 | /*--------------------------------------------------------------------------*/ |
| 1593 | /* Helper Functions */ |
| 1594 | /*--------------------------------------------------------------------------*/ |
| 1595 | |
| 1596 | /****************************************************************************/ |
| 1597 | /* */ |
| 1598 | /* Routine Name: ips_is_passthru */ |
| 1599 | /* */ |
| 1600 | /* Routine Description: */ |
| 1601 | /* */ |
| 1602 | /* Determine if the specified SCSI command is really a passthru command */ |
| 1603 | /* */ |
| 1604 | /****************************************************************************/ |
| 1605 | static int |
| 1606 | ips_is_passthru(Scsi_Cmnd * SC) |
| 1607 | { |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 1608 | unsigned long flags; |
| 1609 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1610 | METHOD_TRACE("ips_is_passthru", 1); |
| 1611 | |
| 1612 | if (!SC) |
| 1613 | return (0); |
| 1614 | |
| 1615 | if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && |
| 1616 | (SC->device->channel == 0) && |
| 1617 | (SC->device->id == IPS_ADAPTER_ID) && |
| 1618 | (SC->device->lun == 0) && SC->request_buffer) { |
| 1619 | if ((!SC->use_sg) && SC->request_bufflen && |
| 1620 | (((char *) SC->request_buffer)[0] == 'C') && |
| 1621 | (((char *) SC->request_buffer)[1] == 'O') && |
| 1622 | (((char *) SC->request_buffer)[2] == 'P') && |
| 1623 | (((char *) SC->request_buffer)[3] == 'P')) |
| 1624 | return 1; |
| 1625 | else if (SC->use_sg) { |
| 1626 | struct scatterlist *sg = SC->request_buffer; |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 1627 | char *buffer; |
| 1628 | |
| 1629 | /* kmap_atomic() ensures addressability of the user buffer.*/ |
| 1630 | /* local_irq_save() protects the KM_IRQ0 address slot. */ |
| 1631 | local_irq_save(flags); |
| 1632 | buffer = kmap_atomic(sg->page, KM_IRQ0) + sg->offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1633 | if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 1634 | buffer[2] == 'P' && buffer[3] == 'P') { |
| 1635 | kunmap_atomic(buffer - sg->offset, KM_IRQ0); |
| 1636 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | return 1; |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 1638 | } |
| 1639 | kunmap_atomic(buffer - sg->offset, KM_IRQ0); |
| 1640 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | } |
| 1642 | } |
| 1643 | return 0; |
| 1644 | } |
| 1645 | |
| 1646 | /****************************************************************************/ |
| 1647 | /* */ |
| 1648 | /* Routine Name: ips_alloc_passthru_buffer */ |
| 1649 | /* */ |
| 1650 | /* Routine Description: */ |
| 1651 | /* allocate a buffer large enough for the ioctl data if the ioctl buffer */ |
| 1652 | /* is too small or doesn't exist */ |
| 1653 | /****************************************************************************/ |
| 1654 | static int |
| 1655 | ips_alloc_passthru_buffer(ips_ha_t * ha, int length) |
| 1656 | { |
| 1657 | void *bigger_buf; |
| 1658 | dma_addr_t dma_busaddr; |
| 1659 | |
| 1660 | if (ha->ioctl_data && length <= ha->ioctl_len) |
| 1661 | return 0; |
| 1662 | /* there is no buffer or it's not big enough, allocate a new one */ |
| 1663 | bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr); |
| 1664 | if (bigger_buf) { |
| 1665 | /* free the old memory */ |
| 1666 | pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data, |
| 1667 | ha->ioctl_busaddr); |
| 1668 | /* use the new memory */ |
| 1669 | ha->ioctl_data = (char *) bigger_buf; |
| 1670 | ha->ioctl_len = length; |
| 1671 | ha->ioctl_busaddr = dma_busaddr; |
| 1672 | } else { |
| 1673 | return -1; |
| 1674 | } |
| 1675 | return 0; |
| 1676 | } |
| 1677 | |
| 1678 | /****************************************************************************/ |
| 1679 | /* */ |
| 1680 | /* Routine Name: ips_make_passthru */ |
| 1681 | /* */ |
| 1682 | /* Routine Description: */ |
| 1683 | /* */ |
| 1684 | /* Make a passthru command out of the info in the Scsi block */ |
| 1685 | /* */ |
| 1686 | /****************************************************************************/ |
| 1687 | static int |
| 1688 | ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr) |
| 1689 | { |
| 1690 | ips_passthru_t *pt; |
| 1691 | int length = 0; |
| 1692 | int ret; |
| 1693 | |
| 1694 | METHOD_TRACE("ips_make_passthru", 1); |
| 1695 | |
| 1696 | if (!SC->use_sg) { |
| 1697 | length = SC->request_bufflen; |
| 1698 | } else { |
| 1699 | struct scatterlist *sg = SC->request_buffer; |
| 1700 | int i; |
| 1701 | for (i = 0; i < SC->use_sg; i++) |
| 1702 | length += sg[i].length; |
| 1703 | } |
| 1704 | if (length < sizeof (ips_passthru_t)) { |
| 1705 | /* wrong size */ |
| 1706 | DEBUG_VAR(1, "(%s%d) Passthru structure wrong size", |
| 1707 | ips_name, ha->host_num); |
| 1708 | return (IPS_FAILURE); |
| 1709 | } |
| 1710 | if (ips_alloc_passthru_buffer(ha, length)) { |
| 1711 | /* allocation failure! If ha->ioctl_data exists, use it to return |
| 1712 | some error codes. Return a failed command to the scsi layer. */ |
| 1713 | if (ha->ioctl_data) { |
| 1714 | pt = (ips_passthru_t *) ha->ioctl_data; |
| 1715 | ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t)); |
| 1716 | pt->BasicStatus = 0x0B; |
| 1717 | pt->ExtendedStatus = 0x00; |
| 1718 | ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t)); |
| 1719 | } |
| 1720 | return IPS_FAILURE; |
| 1721 | } |
| 1722 | ha->ioctl_datasize = length; |
| 1723 | |
| 1724 | ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize); |
| 1725 | pt = (ips_passthru_t *) ha->ioctl_data; |
| 1726 | |
| 1727 | /* |
| 1728 | * Some notes about the passthru interface used |
| 1729 | * |
| 1730 | * IF the scsi op_code == 0x0d then we assume |
| 1731 | * that the data came along with/goes with the |
| 1732 | * packet we received from the sg driver. In this |
| 1733 | * case the CmdBSize field of the pt structure is |
| 1734 | * used for the size of the buffer. |
| 1735 | */ |
| 1736 | |
| 1737 | switch (pt->CoppCmd) { |
| 1738 | case IPS_NUMCTRLS: |
| 1739 | memcpy(ha->ioctl_data + sizeof (ips_passthru_t), |
| 1740 | &ips_num_controllers, sizeof (int)); |
| 1741 | ips_scmd_buf_write(SC, ha->ioctl_data, |
| 1742 | sizeof (ips_passthru_t) + sizeof (int)); |
| 1743 | SC->result = DID_OK << 16; |
| 1744 | |
| 1745 | return (IPS_SUCCESS_IMM); |
| 1746 | |
| 1747 | case IPS_COPPUSRCMD: |
| 1748 | case IPS_COPPIOCCMD: |
| 1749 | if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { |
| 1750 | if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { |
| 1751 | /* wrong size */ |
| 1752 | DEBUG_VAR(1, |
| 1753 | "(%s%d) Passthru structure wrong size", |
| 1754 | ips_name, ha->host_num); |
| 1755 | |
| 1756 | return (IPS_FAILURE); |
| 1757 | } |
| 1758 | |
| 1759 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD && |
| 1760 | pt->CoppCP.cmd.flashfw.op_code == |
| 1761 | IPS_CMD_RW_BIOSFW) { |
| 1762 | ret = ips_flash_copperhead(ha, pt, scb); |
| 1763 | ips_scmd_buf_write(SC, ha->ioctl_data, |
| 1764 | sizeof (ips_passthru_t)); |
| 1765 | return ret; |
| 1766 | } |
| 1767 | if (ips_usrcmd(ha, pt, scb)) |
| 1768 | return (IPS_SUCCESS); |
| 1769 | else |
| 1770 | return (IPS_FAILURE); |
| 1771 | } |
| 1772 | |
| 1773 | break; |
| 1774 | |
| 1775 | } /* end switch */ |
| 1776 | |
| 1777 | return (IPS_FAILURE); |
| 1778 | } |
| 1779 | |
| 1780 | /****************************************************************************/ |
| 1781 | /* Routine Name: ips_flash_copperhead */ |
| 1782 | /* Routine Description: */ |
| 1783 | /* Flash the BIOS/FW on a Copperhead style controller */ |
| 1784 | /****************************************************************************/ |
| 1785 | static int |
| 1786 | ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
| 1787 | { |
| 1788 | int datasize; |
| 1789 | |
| 1790 | /* Trombone is the only copperhead that can do packet flash, but only |
| 1791 | * for firmware. No one said it had to make sence. */ |
| 1792 | if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { |
| 1793 | if (ips_usrcmd(ha, pt, scb)) |
| 1794 | return IPS_SUCCESS; |
| 1795 | else |
| 1796 | return IPS_FAILURE; |
| 1797 | } |
| 1798 | pt->BasicStatus = 0x0B; |
| 1799 | pt->ExtendedStatus = 0; |
| 1800 | scb->scsi_cmd->result = DID_OK << 16; |
| 1801 | /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ |
| 1802 | /* avoid allocating a huge buffer per adapter ( which can fail ). */ |
| 1803 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
| 1804 | pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { |
| 1805 | pt->BasicStatus = 0; |
| 1806 | return ips_flash_bios(ha, pt, scb); |
| 1807 | } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { |
| 1808 | if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){ |
| 1809 | ha->flash_data = ips_FlashData; |
| 1810 | ha->flash_busaddr = ips_flashbusaddr; |
| 1811 | ha->flash_len = PAGE_SIZE << 7; |
| 1812 | ha->flash_datasize = 0; |
| 1813 | } else if (!ha->flash_data) { |
| 1814 | datasize = pt->CoppCP.cmd.flashfw.total_packets * |
| 1815 | pt->CoppCP.cmd.flashfw.count; |
| 1816 | ha->flash_data = pci_alloc_consistent(ha->pcidev, |
| 1817 | datasize, |
| 1818 | &ha->flash_busaddr); |
| 1819 | if (!ha->flash_data){ |
| 1820 | printk(KERN_WARNING "Unable to allocate a flash buffer\n"); |
| 1821 | return IPS_FAILURE; |
| 1822 | } |
| 1823 | ha->flash_datasize = 0; |
| 1824 | ha->flash_len = datasize; |
| 1825 | } else |
| 1826 | return IPS_FAILURE; |
| 1827 | } else { |
| 1828 | if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > |
| 1829 | ha->flash_len) { |
| 1830 | ips_free_flash_copperhead(ha); |
| 1831 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 1832 | "failed size sanity check\n"); |
| 1833 | return IPS_FAILURE; |
| 1834 | } |
| 1835 | } |
| 1836 | if (!ha->flash_data) |
| 1837 | return IPS_FAILURE; |
| 1838 | pt->BasicStatus = 0; |
| 1839 | memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, |
| 1840 | pt->CoppCP.cmd.flashfw.count); |
| 1841 | ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; |
| 1842 | if (pt->CoppCP.cmd.flashfw.packet_num == |
| 1843 | pt->CoppCP.cmd.flashfw.total_packets - 1) { |
| 1844 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) |
| 1845 | return ips_flash_bios(ha, pt, scb); |
| 1846 | else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) |
| 1847 | return ips_flash_firmware(ha, pt, scb); |
| 1848 | } |
| 1849 | return IPS_SUCCESS_IMM; |
| 1850 | } |
| 1851 | |
| 1852 | /****************************************************************************/ |
| 1853 | /* Routine Name: ips_flash_bios */ |
| 1854 | /* Routine Description: */ |
| 1855 | /* flashes the bios of a copperhead adapter */ |
| 1856 | /****************************************************************************/ |
| 1857 | static int |
| 1858 | ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
| 1859 | { |
| 1860 | |
| 1861 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
| 1862 | pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { |
| 1863 | if ((!ha->func.programbios) || (!ha->func.erasebios) || |
| 1864 | (!ha->func.verifybios)) |
| 1865 | goto error; |
| 1866 | if ((*ha->func.erasebios) (ha)) { |
| 1867 | DEBUG_VAR(1, |
| 1868 | "(%s%d) flash bios failed - unable to erase flash", |
| 1869 | ips_name, ha->host_num); |
| 1870 | goto error; |
| 1871 | } else |
| 1872 | if ((*ha->func.programbios) (ha, |
| 1873 | ha->flash_data + |
| 1874 | IPS_BIOS_HEADER, |
| 1875 | ha->flash_datasize - |
| 1876 | IPS_BIOS_HEADER, 0)) { |
| 1877 | DEBUG_VAR(1, |
| 1878 | "(%s%d) flash bios failed - unable to flash", |
| 1879 | ips_name, ha->host_num); |
| 1880 | goto error; |
| 1881 | } else |
| 1882 | if ((*ha->func.verifybios) (ha, |
| 1883 | ha->flash_data + |
| 1884 | IPS_BIOS_HEADER, |
| 1885 | ha->flash_datasize - |
| 1886 | IPS_BIOS_HEADER, 0)) { |
| 1887 | DEBUG_VAR(1, |
| 1888 | "(%s%d) flash bios failed - unable to verify flash", |
| 1889 | ips_name, ha->host_num); |
| 1890 | goto error; |
| 1891 | } |
| 1892 | ips_free_flash_copperhead(ha); |
| 1893 | return IPS_SUCCESS_IMM; |
| 1894 | } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
| 1895 | pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { |
| 1896 | if (!ha->func.erasebios) |
| 1897 | goto error; |
| 1898 | if ((*ha->func.erasebios) (ha)) { |
| 1899 | DEBUG_VAR(1, |
| 1900 | "(%s%d) flash bios failed - unable to erase flash", |
| 1901 | ips_name, ha->host_num); |
| 1902 | goto error; |
| 1903 | } |
| 1904 | return IPS_SUCCESS_IMM; |
| 1905 | } |
| 1906 | error: |
| 1907 | pt->BasicStatus = 0x0B; |
| 1908 | pt->ExtendedStatus = 0x00; |
| 1909 | ips_free_flash_copperhead(ha); |
| 1910 | return IPS_FAILURE; |
| 1911 | } |
| 1912 | |
| 1913 | /****************************************************************************/ |
| 1914 | /* */ |
| 1915 | /* Routine Name: ips_fill_scb_sg_single */ |
| 1916 | /* */ |
| 1917 | /* Routine Description: */ |
| 1918 | /* Fill in a single scb sg_list element from an address */ |
| 1919 | /* return a -1 if a breakup occurred */ |
| 1920 | /****************************************************************************/ |
| 1921 | static int |
| 1922 | ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, |
| 1923 | ips_scb_t * scb, int indx, unsigned int e_len) |
| 1924 | { |
| 1925 | |
| 1926 | int ret_val = 0; |
| 1927 | |
| 1928 | if ((scb->data_len + e_len) > ha->max_xfer) { |
| 1929 | e_len = ha->max_xfer - scb->data_len; |
| 1930 | scb->breakup = indx; |
| 1931 | ++scb->sg_break; |
| 1932 | ret_val = -1; |
| 1933 | } else { |
| 1934 | scb->breakup = 0; |
| 1935 | scb->sg_break = 0; |
| 1936 | } |
| 1937 | if (IPS_USE_ENH_SGLIST(ha)) { |
| 1938 | scb->sg_list.enh_list[indx].address_lo = |
| 1939 | cpu_to_le32(pci_dma_lo32(busaddr)); |
| 1940 | scb->sg_list.enh_list[indx].address_hi = |
| 1941 | cpu_to_le32(pci_dma_hi32(busaddr)); |
| 1942 | scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); |
| 1943 | } else { |
| 1944 | scb->sg_list.std_list[indx].address = |
| 1945 | cpu_to_le32(pci_dma_lo32(busaddr)); |
| 1946 | scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); |
| 1947 | } |
| 1948 | |
| 1949 | ++scb->sg_len; |
| 1950 | scb->data_len += e_len; |
| 1951 | return ret_val; |
| 1952 | } |
| 1953 | |
| 1954 | /****************************************************************************/ |
| 1955 | /* Routine Name: ips_flash_firmware */ |
| 1956 | /* Routine Description: */ |
| 1957 | /* flashes the firmware of a copperhead adapter */ |
| 1958 | /****************************************************************************/ |
| 1959 | static int |
| 1960 | ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
| 1961 | { |
| 1962 | IPS_SG_LIST sg_list; |
| 1963 | uint32_t cmd_busaddr; |
| 1964 | |
| 1965 | if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && |
| 1966 | pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { |
| 1967 | memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); |
| 1968 | pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; |
| 1969 | pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); |
| 1970 | } else { |
| 1971 | pt->BasicStatus = 0x0B; |
| 1972 | pt->ExtendedStatus = 0x00; |
| 1973 | ips_free_flash_copperhead(ha); |
| 1974 | return IPS_FAILURE; |
| 1975 | } |
| 1976 | /* Save the S/G list pointer so it doesn't get clobbered */ |
| 1977 | sg_list.list = scb->sg_list.list; |
| 1978 | cmd_busaddr = scb->scb_busaddr; |
| 1979 | /* copy in the CP */ |
| 1980 | memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); |
| 1981 | /* FIX stuff that might be wrong */ |
| 1982 | scb->sg_list.list = sg_list.list; |
| 1983 | scb->scb_busaddr = cmd_busaddr; |
| 1984 | scb->bus = scb->scsi_cmd->device->channel; |
| 1985 | scb->target_id = scb->scsi_cmd->device->id; |
| 1986 | scb->lun = scb->scsi_cmd->device->lun; |
| 1987 | scb->sg_len = 0; |
| 1988 | scb->data_len = 0; |
| 1989 | scb->flags = 0; |
| 1990 | scb->op_code = 0; |
| 1991 | scb->callback = ipsintr_done; |
| 1992 | scb->timeout = ips_cmd_timeout; |
| 1993 | |
| 1994 | scb->data_len = ha->flash_datasize; |
| 1995 | scb->data_busaddr = |
| 1996 | pci_map_single(ha->pcidev, ha->flash_data, scb->data_len, |
| 1997 | IPS_DMA_DIR(scb)); |
| 1998 | scb->flags |= IPS_SCB_MAP_SINGLE; |
| 1999 | scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); |
| 2000 | scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); |
| 2001 | if (pt->TimeOut) |
| 2002 | scb->timeout = pt->TimeOut; |
| 2003 | scb->scsi_cmd->result = DID_OK << 16; |
| 2004 | return IPS_SUCCESS; |
| 2005 | } |
| 2006 | |
| 2007 | /****************************************************************************/ |
| 2008 | /* Routine Name: ips_free_flash_copperhead */ |
| 2009 | /* Routine Description: */ |
| 2010 | /* release the memory resources used to hold the flash image */ |
| 2011 | /****************************************************************************/ |
| 2012 | static void |
| 2013 | ips_free_flash_copperhead(ips_ha_t * ha) |
| 2014 | { |
| 2015 | if (ha->flash_data == ips_FlashData) |
| 2016 | test_and_clear_bit(0, &ips_FlashDataInUse); |
| 2017 | else if (ha->flash_data) |
| 2018 | pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data, |
| 2019 | ha->flash_busaddr); |
| 2020 | ha->flash_data = NULL; |
| 2021 | } |
| 2022 | |
| 2023 | /****************************************************************************/ |
| 2024 | /* */ |
| 2025 | /* Routine Name: ips_usrcmd */ |
| 2026 | /* */ |
| 2027 | /* Routine Description: */ |
| 2028 | /* */ |
| 2029 | /* Process a user command and make it ready to send */ |
| 2030 | /* */ |
| 2031 | /****************************************************************************/ |
| 2032 | static int |
| 2033 | ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
| 2034 | { |
| 2035 | IPS_SG_LIST sg_list; |
| 2036 | uint32_t cmd_busaddr; |
| 2037 | |
| 2038 | METHOD_TRACE("ips_usrcmd", 1); |
| 2039 | |
| 2040 | if ((!scb) || (!pt) || (!ha)) |
| 2041 | return (0); |
| 2042 | |
| 2043 | /* Save the S/G list pointer so it doesn't get clobbered */ |
| 2044 | sg_list.list = scb->sg_list.list; |
| 2045 | cmd_busaddr = scb->scb_busaddr; |
| 2046 | /* copy in the CP */ |
| 2047 | memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); |
| 2048 | memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); |
| 2049 | |
| 2050 | /* FIX stuff that might be wrong */ |
| 2051 | scb->sg_list.list = sg_list.list; |
| 2052 | scb->scb_busaddr = cmd_busaddr; |
| 2053 | scb->bus = scb->scsi_cmd->device->channel; |
| 2054 | scb->target_id = scb->scsi_cmd->device->id; |
| 2055 | scb->lun = scb->scsi_cmd->device->lun; |
| 2056 | scb->sg_len = 0; |
| 2057 | scb->data_len = 0; |
| 2058 | scb->flags = 0; |
| 2059 | scb->op_code = 0; |
| 2060 | scb->callback = ipsintr_done; |
| 2061 | scb->timeout = ips_cmd_timeout; |
| 2062 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 2063 | |
| 2064 | /* we don't support DCDB/READ/WRITE Scatter Gather */ |
| 2065 | if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || |
| 2066 | (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || |
| 2067 | (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) |
| 2068 | return (0); |
| 2069 | |
| 2070 | if (pt->CmdBSize) { |
| 2071 | scb->data_len = pt->CmdBSize; |
| 2072 | scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); |
| 2073 | } else { |
| 2074 | scb->data_busaddr = 0L; |
| 2075 | } |
| 2076 | |
| 2077 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) |
| 2078 | scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + |
| 2079 | (unsigned long) &scb-> |
| 2080 | dcdb - |
| 2081 | (unsigned long) scb); |
| 2082 | |
| 2083 | if (pt->CmdBSize) { |
| 2084 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) |
| 2085 | scb->dcdb.buffer_pointer = |
| 2086 | cpu_to_le32(scb->data_busaddr); |
| 2087 | else |
| 2088 | scb->cmd.basic_io.sg_addr = |
| 2089 | cpu_to_le32(scb->data_busaddr); |
| 2090 | } |
| 2091 | |
| 2092 | /* set timeouts */ |
| 2093 | if (pt->TimeOut) { |
| 2094 | scb->timeout = pt->TimeOut; |
| 2095 | |
| 2096 | if (pt->TimeOut <= 10) |
| 2097 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; |
| 2098 | else if (pt->TimeOut <= 60) |
| 2099 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; |
| 2100 | else |
| 2101 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; |
| 2102 | } |
| 2103 | |
| 2104 | /* assume success */ |
| 2105 | scb->scsi_cmd->result = DID_OK << 16; |
| 2106 | |
| 2107 | /* success */ |
| 2108 | return (1); |
| 2109 | } |
| 2110 | |
| 2111 | /****************************************************************************/ |
| 2112 | /* */ |
| 2113 | /* Routine Name: ips_cleanup_passthru */ |
| 2114 | /* */ |
| 2115 | /* Routine Description: */ |
| 2116 | /* */ |
| 2117 | /* Cleanup after a passthru command */ |
| 2118 | /* */ |
| 2119 | /****************************************************************************/ |
| 2120 | static void |
| 2121 | ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) |
| 2122 | { |
| 2123 | ips_passthru_t *pt; |
| 2124 | |
| 2125 | METHOD_TRACE("ips_cleanup_passthru", 1); |
| 2126 | |
| 2127 | if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) { |
| 2128 | DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru", |
| 2129 | ips_name, ha->host_num); |
| 2130 | |
| 2131 | return; |
| 2132 | } |
| 2133 | pt = (ips_passthru_t *) ha->ioctl_data; |
| 2134 | |
| 2135 | /* Copy data back to the user */ |
| 2136 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ |
| 2137 | memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); |
| 2138 | |
| 2139 | pt->BasicStatus = scb->basic_status; |
| 2140 | pt->ExtendedStatus = scb->extended_status; |
| 2141 | pt->AdapterType = ha->ad_type; |
| 2142 | |
| 2143 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD && |
| 2144 | (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || |
| 2145 | scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) |
| 2146 | ips_free_flash_copperhead(ha); |
| 2147 | |
| 2148 | ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize); |
| 2149 | } |
| 2150 | |
| 2151 | /****************************************************************************/ |
| 2152 | /* */ |
| 2153 | /* Routine Name: ips_host_info */ |
| 2154 | /* */ |
| 2155 | /* Routine Description: */ |
| 2156 | /* */ |
| 2157 | /* The passthru interface for the driver */ |
| 2158 | /* */ |
| 2159 | /****************************************************************************/ |
| 2160 | static int |
| 2161 | ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len) |
| 2162 | { |
| 2163 | IPS_INFOSTR info; |
| 2164 | |
| 2165 | METHOD_TRACE("ips_host_info", 1); |
| 2166 | |
| 2167 | info.buffer = ptr; |
| 2168 | info.length = len; |
| 2169 | info.offset = offset; |
| 2170 | info.pos = 0; |
| 2171 | info.localpos = 0; |
| 2172 | |
| 2173 | copy_info(&info, "\nIBM ServeRAID General Information:\n\n"); |
| 2174 | |
| 2175 | if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && |
| 2176 | (le16_to_cpu(ha->nvram->adapter_type) != 0)) |
| 2177 | copy_info(&info, "\tController Type : %s\n", |
| 2178 | ips_adapter_name[ha->ad_type - 1]); |
| 2179 | else |
| 2180 | copy_info(&info, |
| 2181 | "\tController Type : Unknown\n"); |
| 2182 | |
| 2183 | if (ha->io_addr) |
| 2184 | copy_info(&info, |
| 2185 | "\tIO region : 0x%lx (%d bytes)\n", |
| 2186 | ha->io_addr, ha->io_len); |
| 2187 | |
| 2188 | if (ha->mem_addr) { |
| 2189 | copy_info(&info, |
| 2190 | "\tMemory region : 0x%lx (%d bytes)\n", |
| 2191 | ha->mem_addr, ha->mem_len); |
| 2192 | copy_info(&info, |
| 2193 | "\tShared memory address : 0x%lx\n", |
| 2194 | ha->mem_ptr); |
| 2195 | } |
| 2196 | |
| 2197 | copy_info(&info, "\tIRQ number : %d\n", ha->irq); |
| 2198 | |
| 2199 | /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ |
| 2200 | /* That keeps everything happy for "text" operations on the proc file. */ |
| 2201 | |
| 2202 | if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { |
| 2203 | if (ha->nvram->bios_low[3] == 0) { |
| 2204 | copy_info(&info, |
| 2205 | "\tBIOS Version : %c%c%c%c%c%c%c\n", |
| 2206 | ha->nvram->bios_high[0], ha->nvram->bios_high[1], |
| 2207 | ha->nvram->bios_high[2], ha->nvram->bios_high[3], |
| 2208 | ha->nvram->bios_low[0], ha->nvram->bios_low[1], |
| 2209 | ha->nvram->bios_low[2]); |
| 2210 | |
| 2211 | } else { |
| 2212 | copy_info(&info, |
| 2213 | "\tBIOS Version : %c%c%c%c%c%c%c%c\n", |
| 2214 | ha->nvram->bios_high[0], ha->nvram->bios_high[1], |
| 2215 | ha->nvram->bios_high[2], ha->nvram->bios_high[3], |
| 2216 | ha->nvram->bios_low[0], ha->nvram->bios_low[1], |
| 2217 | ha->nvram->bios_low[2], ha->nvram->bios_low[3]); |
| 2218 | } |
| 2219 | |
| 2220 | } |
| 2221 | |
| 2222 | if (ha->enq->CodeBlkVersion[7] == 0) { |
| 2223 | copy_info(&info, |
| 2224 | "\tFirmware Version : %c%c%c%c%c%c%c\n", |
| 2225 | ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], |
| 2226 | ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], |
| 2227 | ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], |
| 2228 | ha->enq->CodeBlkVersion[6]); |
| 2229 | } else { |
| 2230 | copy_info(&info, |
| 2231 | "\tFirmware Version : %c%c%c%c%c%c%c%c\n", |
| 2232 | ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], |
| 2233 | ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], |
| 2234 | ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], |
| 2235 | ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); |
| 2236 | } |
| 2237 | |
| 2238 | if (ha->enq->BootBlkVersion[7] == 0) { |
| 2239 | copy_info(&info, |
| 2240 | "\tBoot Block Version : %c%c%c%c%c%c%c\n", |
| 2241 | ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], |
| 2242 | ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], |
| 2243 | ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], |
| 2244 | ha->enq->BootBlkVersion[6]); |
| 2245 | } else { |
| 2246 | copy_info(&info, |
| 2247 | "\tBoot Block Version : %c%c%c%c%c%c%c%c\n", |
| 2248 | ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], |
| 2249 | ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], |
| 2250 | ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], |
| 2251 | ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); |
| 2252 | } |
| 2253 | |
| 2254 | copy_info(&info, "\tDriver Version : %s%s\n", |
| 2255 | IPS_VERSION_HIGH, IPS_VERSION_LOW); |
| 2256 | |
| 2257 | copy_info(&info, "\tDriver Build : %d\n", |
| 2258 | IPS_BUILD_IDENT); |
| 2259 | |
| 2260 | copy_info(&info, "\tMax Physical Devices : %d\n", |
| 2261 | ha->enq->ucMaxPhysicalDevices); |
| 2262 | copy_info(&info, "\tMax Active Commands : %d\n", |
| 2263 | ha->max_cmds); |
| 2264 | copy_info(&info, "\tCurrent Queued Commands : %d\n", |
| 2265 | ha->scb_waitlist.count); |
| 2266 | copy_info(&info, "\tCurrent Active Commands : %d\n", |
| 2267 | ha->scb_activelist.count - ha->num_ioctl); |
| 2268 | copy_info(&info, "\tCurrent Queued PT Commands : %d\n", |
| 2269 | ha->copp_waitlist.count); |
| 2270 | copy_info(&info, "\tCurrent Active PT Commands : %d\n", |
| 2271 | ha->num_ioctl); |
| 2272 | |
| 2273 | copy_info(&info, "\n"); |
| 2274 | |
| 2275 | return (info.localpos); |
| 2276 | } |
| 2277 | |
| 2278 | /****************************************************************************/ |
| 2279 | /* */ |
| 2280 | /* Routine Name: copy_mem_info */ |
| 2281 | /* */ |
| 2282 | /* Routine Description: */ |
| 2283 | /* */ |
| 2284 | /* Copy data into an IPS_INFOSTR structure */ |
| 2285 | /* */ |
| 2286 | /****************************************************************************/ |
| 2287 | static void |
| 2288 | copy_mem_info(IPS_INFOSTR * info, char *data, int len) |
| 2289 | { |
| 2290 | METHOD_TRACE("copy_mem_info", 1); |
| 2291 | |
| 2292 | if (info->pos + len < info->offset) { |
| 2293 | info->pos += len; |
| 2294 | return; |
| 2295 | } |
| 2296 | |
| 2297 | if (info->pos < info->offset) { |
| 2298 | data += (info->offset - info->pos); |
| 2299 | len -= (info->offset - info->pos); |
| 2300 | info->pos += (info->offset - info->pos); |
| 2301 | } |
| 2302 | |
| 2303 | if (info->localpos + len > info->length) |
| 2304 | len = info->length - info->localpos; |
| 2305 | |
| 2306 | if (len > 0) { |
| 2307 | memcpy(info->buffer + info->localpos, data, len); |
| 2308 | info->pos += len; |
| 2309 | info->localpos += len; |
| 2310 | } |
| 2311 | } |
| 2312 | |
| 2313 | /****************************************************************************/ |
| 2314 | /* */ |
| 2315 | /* Routine Name: copy_info */ |
| 2316 | /* */ |
| 2317 | /* Routine Description: */ |
| 2318 | /* */ |
| 2319 | /* printf style wrapper for an info structure */ |
| 2320 | /* */ |
| 2321 | /****************************************************************************/ |
| 2322 | static int |
| 2323 | copy_info(IPS_INFOSTR * info, char *fmt, ...) |
| 2324 | { |
| 2325 | va_list args; |
| 2326 | char buf[128]; |
| 2327 | int len; |
| 2328 | |
| 2329 | METHOD_TRACE("copy_info", 1); |
| 2330 | |
| 2331 | va_start(args, fmt); |
| 2332 | len = vsprintf(buf, fmt, args); |
| 2333 | va_end(args); |
| 2334 | |
| 2335 | copy_mem_info(info, buf, len); |
| 2336 | |
| 2337 | return (len); |
| 2338 | } |
| 2339 | |
| 2340 | /****************************************************************************/ |
| 2341 | /* */ |
| 2342 | /* Routine Name: ips_identify_controller */ |
| 2343 | /* */ |
| 2344 | /* Routine Description: */ |
| 2345 | /* */ |
| 2346 | /* Identify this controller */ |
| 2347 | /* */ |
| 2348 | /****************************************************************************/ |
| 2349 | static void |
| 2350 | ips_identify_controller(ips_ha_t * ha) |
| 2351 | { |
| 2352 | METHOD_TRACE("ips_identify_controller", 1); |
| 2353 | |
| 2354 | switch (ha->device_id) { |
| 2355 | case IPS_DEVICEID_COPPERHEAD: |
| 2356 | if (ha->revision_id <= IPS_REVID_SERVERAID) { |
| 2357 | ha->ad_type = IPS_ADTYPE_SERVERAID; |
| 2358 | } else if (ha->revision_id == IPS_REVID_SERVERAID2) { |
| 2359 | ha->ad_type = IPS_ADTYPE_SERVERAID2; |
| 2360 | } else if (ha->revision_id == IPS_REVID_NAVAJO) { |
| 2361 | ha->ad_type = IPS_ADTYPE_NAVAJO; |
| 2362 | } else if ((ha->revision_id == IPS_REVID_SERVERAID2) |
| 2363 | && (ha->slot_num == 0)) { |
| 2364 | ha->ad_type = IPS_ADTYPE_KIOWA; |
| 2365 | } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) && |
| 2366 | (ha->revision_id <= IPS_REVID_CLARINETP3)) { |
| 2367 | if (ha->enq->ucMaxPhysicalDevices == 15) |
| 2368 | ha->ad_type = IPS_ADTYPE_SERVERAID3L; |
| 2369 | else |
| 2370 | ha->ad_type = IPS_ADTYPE_SERVERAID3; |
| 2371 | } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) && |
| 2372 | (ha->revision_id <= IPS_REVID_TROMBONE64)) { |
| 2373 | ha->ad_type = IPS_ADTYPE_SERVERAID4H; |
| 2374 | } |
| 2375 | break; |
| 2376 | |
| 2377 | case IPS_DEVICEID_MORPHEUS: |
| 2378 | switch (ha->subdevice_id) { |
| 2379 | case IPS_SUBDEVICEID_4L: |
| 2380 | ha->ad_type = IPS_ADTYPE_SERVERAID4L; |
| 2381 | break; |
| 2382 | |
| 2383 | case IPS_SUBDEVICEID_4M: |
| 2384 | ha->ad_type = IPS_ADTYPE_SERVERAID4M; |
| 2385 | break; |
| 2386 | |
| 2387 | case IPS_SUBDEVICEID_4MX: |
| 2388 | ha->ad_type = IPS_ADTYPE_SERVERAID4MX; |
| 2389 | break; |
| 2390 | |
| 2391 | case IPS_SUBDEVICEID_4LX: |
| 2392 | ha->ad_type = IPS_ADTYPE_SERVERAID4LX; |
| 2393 | break; |
| 2394 | |
| 2395 | case IPS_SUBDEVICEID_5I2: |
| 2396 | ha->ad_type = IPS_ADTYPE_SERVERAID5I2; |
| 2397 | break; |
| 2398 | |
| 2399 | case IPS_SUBDEVICEID_5I1: |
| 2400 | ha->ad_type = IPS_ADTYPE_SERVERAID5I1; |
| 2401 | break; |
| 2402 | } |
| 2403 | |
| 2404 | break; |
| 2405 | |
| 2406 | case IPS_DEVICEID_MARCO: |
| 2407 | switch (ha->subdevice_id) { |
| 2408 | case IPS_SUBDEVICEID_6M: |
| 2409 | ha->ad_type = IPS_ADTYPE_SERVERAID6M; |
| 2410 | break; |
| 2411 | case IPS_SUBDEVICEID_6I: |
| 2412 | ha->ad_type = IPS_ADTYPE_SERVERAID6I; |
| 2413 | break; |
| 2414 | case IPS_SUBDEVICEID_7k: |
| 2415 | ha->ad_type = IPS_ADTYPE_SERVERAID7k; |
| 2416 | break; |
| 2417 | case IPS_SUBDEVICEID_7M: |
| 2418 | ha->ad_type = IPS_ADTYPE_SERVERAID7M; |
| 2419 | break; |
| 2420 | } |
| 2421 | break; |
| 2422 | } |
| 2423 | } |
| 2424 | |
| 2425 | /****************************************************************************/ |
| 2426 | /* */ |
| 2427 | /* Routine Name: ips_get_bios_version */ |
| 2428 | /* */ |
| 2429 | /* Routine Description: */ |
| 2430 | /* */ |
| 2431 | /* Get the BIOS revision number */ |
| 2432 | /* */ |
| 2433 | /****************************************************************************/ |
| 2434 | static void |
| 2435 | ips_get_bios_version(ips_ha_t * ha, int intr) |
| 2436 | { |
| 2437 | ips_scb_t *scb; |
| 2438 | int ret; |
| 2439 | uint8_t major; |
| 2440 | uint8_t minor; |
| 2441 | uint8_t subminor; |
| 2442 | uint8_t *buffer; |
| 2443 | char hexDigits[] = |
| 2444 | { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', |
| 2445 | 'D', 'E', 'F' }; |
| 2446 | |
| 2447 | METHOD_TRACE("ips_get_bios_version", 1); |
| 2448 | |
| 2449 | major = 0; |
| 2450 | minor = 0; |
| 2451 | |
| 2452 | strncpy(ha->bios_version, " ?", 8); |
| 2453 | |
| 2454 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD) { |
| 2455 | if (IPS_USE_MEMIO(ha)) { |
| 2456 | /* Memory Mapped I/O */ |
| 2457 | |
| 2458 | /* test 1st byte */ |
| 2459 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 2460 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2461 | udelay(25); /* 25 us */ |
| 2462 | |
| 2463 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
| 2464 | return; |
| 2465 | |
| 2466 | writel(1, ha->mem_ptr + IPS_REG_FLAP); |
| 2467 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2468 | udelay(25); /* 25 us */ |
| 2469 | |
| 2470 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
| 2471 | return; |
| 2472 | |
| 2473 | /* Get Major version */ |
| 2474 | writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); |
| 2475 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2476 | udelay(25); /* 25 us */ |
| 2477 | |
| 2478 | major = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 2479 | |
| 2480 | /* Get Minor version */ |
| 2481 | writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); |
| 2482 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2483 | udelay(25); /* 25 us */ |
| 2484 | minor = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 2485 | |
| 2486 | /* Get SubMinor version */ |
| 2487 | writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); |
| 2488 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2489 | udelay(25); /* 25 us */ |
| 2490 | subminor = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 2491 | |
| 2492 | } else { |
| 2493 | /* Programmed I/O */ |
| 2494 | |
| 2495 | /* test 1st byte */ |
| 2496 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 2497 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2498 | udelay(25); /* 25 us */ |
| 2499 | |
| 2500 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) |
| 2501 | return; |
| 2502 | |
| 2503 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); |
| 2504 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2505 | udelay(25); /* 25 us */ |
| 2506 | |
| 2507 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) |
| 2508 | return; |
| 2509 | |
| 2510 | /* Get Major version */ |
| 2511 | outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP); |
| 2512 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2513 | udelay(25); /* 25 us */ |
| 2514 | |
| 2515 | major = inb(ha->io_addr + IPS_REG_FLDP); |
| 2516 | |
| 2517 | /* Get Minor version */ |
| 2518 | outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP); |
| 2519 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2520 | udelay(25); /* 25 us */ |
| 2521 | |
| 2522 | minor = inb(ha->io_addr + IPS_REG_FLDP); |
| 2523 | |
| 2524 | /* Get SubMinor version */ |
| 2525 | outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP); |
| 2526 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 2527 | udelay(25); /* 25 us */ |
| 2528 | |
| 2529 | subminor = inb(ha->io_addr + IPS_REG_FLDP); |
| 2530 | |
| 2531 | } |
| 2532 | } else { |
| 2533 | /* Morpheus Family - Send Command to the card */ |
| 2534 | |
| 2535 | buffer = ha->ioctl_data; |
| 2536 | |
| 2537 | memset(buffer, 0, 0x1000); |
| 2538 | |
| 2539 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 2540 | |
| 2541 | ips_init_scb(ha, scb); |
| 2542 | |
| 2543 | scb->timeout = ips_cmd_timeout; |
| 2544 | scb->cdb[0] = IPS_CMD_RW_BIOSFW; |
| 2545 | |
| 2546 | scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; |
| 2547 | scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); |
| 2548 | scb->cmd.flashfw.type = 1; |
| 2549 | scb->cmd.flashfw.direction = 0; |
| 2550 | scb->cmd.flashfw.count = cpu_to_le32(0x800); |
| 2551 | scb->cmd.flashfw.total_packets = 1; |
| 2552 | scb->cmd.flashfw.packet_num = 0; |
| 2553 | scb->data_len = 0x1000; |
| 2554 | scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; |
| 2555 | |
| 2556 | /* issue the command */ |
| 2557 | if (((ret = |
| 2558 | ips_send_wait(ha, scb, ips_cmd_timeout, |
| 2559 | intr)) == IPS_FAILURE) |
| 2560 | || (ret == IPS_SUCCESS_IMM) |
| 2561 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
| 2562 | /* Error occurred */ |
| 2563 | |
| 2564 | return; |
| 2565 | } |
| 2566 | |
| 2567 | if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { |
| 2568 | major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ |
| 2569 | minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ |
| 2570 | subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ |
| 2571 | } else { |
| 2572 | return; |
| 2573 | } |
| 2574 | } |
| 2575 | |
| 2576 | ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4]; |
| 2577 | ha->bios_version[1] = '.'; |
| 2578 | ha->bios_version[2] = hexDigits[major & 0x0F]; |
| 2579 | ha->bios_version[3] = hexDigits[subminor]; |
| 2580 | ha->bios_version[4] = '.'; |
| 2581 | ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4]; |
| 2582 | ha->bios_version[6] = hexDigits[minor & 0x0F]; |
| 2583 | ha->bios_version[7] = 0; |
| 2584 | } |
| 2585 | |
| 2586 | /****************************************************************************/ |
| 2587 | /* */ |
| 2588 | /* Routine Name: ips_hainit */ |
| 2589 | /* */ |
| 2590 | /* Routine Description: */ |
| 2591 | /* */ |
| 2592 | /* Initialize the controller */ |
| 2593 | /* */ |
| 2594 | /* NOTE: Assumes to be called from with a lock */ |
| 2595 | /* */ |
| 2596 | /****************************************************************************/ |
| 2597 | static int |
| 2598 | ips_hainit(ips_ha_t * ha) |
| 2599 | { |
| 2600 | int i; |
| 2601 | struct timeval tv; |
| 2602 | |
| 2603 | METHOD_TRACE("ips_hainit", 1); |
| 2604 | |
| 2605 | if (!ha) |
| 2606 | return (0); |
| 2607 | |
| 2608 | if (ha->func.statinit) |
| 2609 | (*ha->func.statinit) (ha); |
| 2610 | |
| 2611 | if (ha->func.enableint) |
| 2612 | (*ha->func.enableint) (ha); |
| 2613 | |
| 2614 | /* Send FFDC */ |
| 2615 | ha->reset_count = 1; |
| 2616 | do_gettimeofday(&tv); |
| 2617 | ha->last_ffdc = tv.tv_sec; |
| 2618 | ips_ffdc_reset(ha, IPS_INTR_IORL); |
| 2619 | |
| 2620 | if (!ips_read_config(ha, IPS_INTR_IORL)) { |
| 2621 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 2622 | "unable to read config from controller.\n"); |
| 2623 | |
| 2624 | return (0); |
| 2625 | } |
| 2626 | /* end if */ |
| 2627 | if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { |
| 2628 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 2629 | "unable to read controller status.\n"); |
| 2630 | |
| 2631 | return (0); |
| 2632 | } |
| 2633 | |
| 2634 | /* Identify this controller */ |
| 2635 | ips_identify_controller(ha); |
| 2636 | |
| 2637 | if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { |
| 2638 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 2639 | "unable to read subsystem parameters.\n"); |
| 2640 | |
| 2641 | return (0); |
| 2642 | } |
| 2643 | |
| 2644 | /* write nvram user page 5 */ |
| 2645 | if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { |
| 2646 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 2647 | "unable to write driver info to controller.\n"); |
| 2648 | |
| 2649 | return (0); |
| 2650 | } |
| 2651 | |
| 2652 | /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ |
| 2653 | if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) |
| 2654 | ips_clear_adapter(ha, IPS_INTR_IORL); |
| 2655 | |
| 2656 | /* set limits on SID, LUN, BUS */ |
| 2657 | ha->ntargets = IPS_MAX_TARGETS + 1; |
| 2658 | ha->nlun = 1; |
| 2659 | ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; |
| 2660 | |
| 2661 | switch (ha->conf->logical_drive[0].ucStripeSize) { |
| 2662 | case 4: |
| 2663 | ha->max_xfer = 0x10000; |
| 2664 | break; |
| 2665 | |
| 2666 | case 5: |
| 2667 | ha->max_xfer = 0x20000; |
| 2668 | break; |
| 2669 | |
| 2670 | case 6: |
| 2671 | ha->max_xfer = 0x40000; |
| 2672 | break; |
| 2673 | |
| 2674 | case 7: |
| 2675 | default: |
| 2676 | ha->max_xfer = 0x80000; |
| 2677 | break; |
| 2678 | } |
| 2679 | |
| 2680 | /* setup max concurrent commands */ |
| 2681 | if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { |
| 2682 | /* Use the new method */ |
| 2683 | ha->max_cmds = ha->enq->ucConcurrentCmdCount; |
| 2684 | } else { |
| 2685 | /* use the old method */ |
| 2686 | switch (ha->conf->logical_drive[0].ucStripeSize) { |
| 2687 | case 4: |
| 2688 | ha->max_cmds = 32; |
| 2689 | break; |
| 2690 | |
| 2691 | case 5: |
| 2692 | ha->max_cmds = 16; |
| 2693 | break; |
| 2694 | |
| 2695 | case 6: |
| 2696 | ha->max_cmds = 8; |
| 2697 | break; |
| 2698 | |
| 2699 | case 7: |
| 2700 | default: |
| 2701 | ha->max_cmds = 4; |
| 2702 | break; |
| 2703 | } |
| 2704 | } |
| 2705 | |
| 2706 | /* Limit the Active Commands on a Lite Adapter */ |
| 2707 | if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || |
| 2708 | (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || |
| 2709 | (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { |
| 2710 | if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) |
| 2711 | ha->max_cmds = MaxLiteCmds; |
| 2712 | } |
| 2713 | |
| 2714 | /* set controller IDs */ |
| 2715 | ha->ha_id[0] = IPS_ADAPTER_ID; |
| 2716 | for (i = 1; i < ha->nbus; i++) { |
| 2717 | ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; |
| 2718 | ha->dcdb_active[i - 1] = 0; |
| 2719 | } |
| 2720 | |
| 2721 | return (1); |
| 2722 | } |
| 2723 | |
| 2724 | /****************************************************************************/ |
| 2725 | /* */ |
| 2726 | /* Routine Name: ips_next */ |
| 2727 | /* */ |
| 2728 | /* Routine Description: */ |
| 2729 | /* */ |
| 2730 | /* Take the next command off the queue and send it to the controller */ |
| 2731 | /* */ |
| 2732 | /****************************************************************************/ |
| 2733 | static void |
| 2734 | ips_next(ips_ha_t * ha, int intr) |
| 2735 | { |
| 2736 | ips_scb_t *scb; |
| 2737 | Scsi_Cmnd *SC; |
| 2738 | Scsi_Cmnd *p; |
| 2739 | Scsi_Cmnd *q; |
| 2740 | ips_copp_wait_item_t *item; |
| 2741 | int ret; |
| 2742 | unsigned long cpu_flags = 0; |
| 2743 | struct Scsi_Host *host; |
| 2744 | METHOD_TRACE("ips_next", 1); |
| 2745 | |
| 2746 | if (!ha) |
| 2747 | return; |
| 2748 | host = ips_sh[ha->host_num]; |
| 2749 | /* |
| 2750 | * Block access to the queue function so |
| 2751 | * this command won't time out |
| 2752 | */ |
| 2753 | if (intr == IPS_INTR_ON) |
| 2754 | IPS_LOCK_SAVE(host->host_lock, cpu_flags); |
| 2755 | |
| 2756 | if ((ha->subsys->param[3] & 0x300000) |
| 2757 | && (ha->scb_activelist.count == 0)) { |
| 2758 | struct timeval tv; |
| 2759 | |
| 2760 | do_gettimeofday(&tv); |
| 2761 | |
| 2762 | if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) { |
| 2763 | ha->last_ffdc = tv.tv_sec; |
| 2764 | ips_ffdc_time(ha); |
| 2765 | } |
| 2766 | } |
| 2767 | |
| 2768 | /* |
| 2769 | * Send passthru commands |
| 2770 | * These have priority over normal I/O |
| 2771 | * but shouldn't affect performance too much |
| 2772 | * since we limit the number that can be active |
| 2773 | * on the card at any one time |
| 2774 | */ |
| 2775 | while ((ha->num_ioctl < IPS_MAX_IOCTL) && |
| 2776 | (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { |
| 2777 | |
| 2778 | item = ips_removeq_copp_head(&ha->copp_waitlist); |
| 2779 | ha->num_ioctl++; |
| 2780 | if (intr == IPS_INTR_ON) |
| 2781 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); |
| 2782 | scb->scsi_cmd = item->scsi_cmd; |
| 2783 | kfree(item); |
| 2784 | |
| 2785 | ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr); |
| 2786 | |
| 2787 | if (intr == IPS_INTR_ON) |
| 2788 | IPS_LOCK_SAVE(host->host_lock, cpu_flags); |
| 2789 | switch (ret) { |
| 2790 | case IPS_FAILURE: |
| 2791 | if (scb->scsi_cmd) { |
| 2792 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 2793 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 2794 | } |
| 2795 | |
| 2796 | ips_freescb(ha, scb); |
| 2797 | break; |
| 2798 | case IPS_SUCCESS_IMM: |
| 2799 | if (scb->scsi_cmd) { |
| 2800 | scb->scsi_cmd->result = DID_OK << 16; |
| 2801 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 2802 | } |
| 2803 | |
| 2804 | ips_freescb(ha, scb); |
| 2805 | break; |
| 2806 | default: |
| 2807 | break; |
| 2808 | } /* end case */ |
| 2809 | |
| 2810 | if (ret != IPS_SUCCESS) { |
| 2811 | ha->num_ioctl--; |
| 2812 | continue; |
| 2813 | } |
| 2814 | |
| 2815 | ret = ips_send_cmd(ha, scb); |
| 2816 | |
| 2817 | if (ret == IPS_SUCCESS) |
| 2818 | ips_putq_scb_head(&ha->scb_activelist, scb); |
| 2819 | else |
| 2820 | ha->num_ioctl--; |
| 2821 | |
| 2822 | switch (ret) { |
| 2823 | case IPS_FAILURE: |
| 2824 | if (scb->scsi_cmd) { |
| 2825 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 2826 | } |
| 2827 | |
| 2828 | ips_freescb(ha, scb); |
| 2829 | break; |
| 2830 | case IPS_SUCCESS_IMM: |
| 2831 | ips_freescb(ha, scb); |
| 2832 | break; |
| 2833 | default: |
| 2834 | break; |
| 2835 | } /* end case */ |
| 2836 | |
| 2837 | } |
| 2838 | |
| 2839 | /* |
| 2840 | * Send "Normal" I/O commands |
| 2841 | */ |
| 2842 | |
| 2843 | p = ha->scb_waitlist.head; |
| 2844 | while ((p) && (scb = ips_getscb(ha))) { |
Jeff Garzik | 422c0d6 | 2005-10-24 18:05:09 -0400 | [diff] [blame] | 2845 | if ((scmd_channel(p) > 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2846 | && (ha-> |
Jeff Garzik | 422c0d6 | 2005-10-24 18:05:09 -0400 | [diff] [blame] | 2847 | dcdb_active[scmd_channel(p) - |
| 2848 | 1] & (1 << scmd_id(p)))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2849 | ips_freescb(ha, scb); |
| 2850 | p = (Scsi_Cmnd *) p->host_scribble; |
| 2851 | continue; |
| 2852 | } |
| 2853 | |
| 2854 | q = p; |
| 2855 | SC = ips_removeq_wait(&ha->scb_waitlist, q); |
| 2856 | |
| 2857 | if (intr == IPS_INTR_ON) |
| 2858 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */ |
| 2859 | |
| 2860 | SC->result = DID_OK; |
| 2861 | SC->host_scribble = NULL; |
| 2862 | |
| 2863 | memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer)); |
| 2864 | |
| 2865 | scb->target_id = SC->device->id; |
| 2866 | scb->lun = SC->device->lun; |
| 2867 | scb->bus = SC->device->channel; |
| 2868 | scb->scsi_cmd = SC; |
| 2869 | scb->breakup = 0; |
| 2870 | scb->data_len = 0; |
| 2871 | scb->callback = ipsintr_done; |
| 2872 | scb->timeout = ips_cmd_timeout; |
| 2873 | memset(&scb->cmd, 0, 16); |
| 2874 | |
| 2875 | /* copy in the CDB */ |
| 2876 | memcpy(scb->cdb, SC->cmnd, SC->cmd_len); |
| 2877 | |
| 2878 | /* Now handle the data buffer */ |
| 2879 | if (SC->use_sg) { |
| 2880 | struct scatterlist *sg; |
| 2881 | int i; |
| 2882 | |
| 2883 | sg = SC->request_buffer; |
| 2884 | scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg, |
| be7db05 | 2005-04-17 15:26:13 -0500 | [diff] [blame] | 2885 | SC->sc_data_direction); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2886 | scb->flags |= IPS_SCB_MAP_SG; |
| 2887 | for (i = 0; i < scb->sg_count; i++) { |
| 2888 | if (ips_fill_scb_sg_single |
| 2889 | (ha, sg_dma_address(&sg[i]), scb, i, |
| 2890 | sg_dma_len(&sg[i])) < 0) |
| 2891 | break; |
| 2892 | } |
| 2893 | scb->dcdb.transfer_length = scb->data_len; |
| 2894 | } else { |
| 2895 | if (SC->request_bufflen) { |
| 2896 | scb->data_busaddr = |
| 2897 | pci_map_single(ha->pcidev, |
| 2898 | SC->request_buffer, |
| 2899 | SC->request_bufflen, |
| be7db05 | 2005-04-17 15:26:13 -0500 | [diff] [blame] | 2900 | SC->sc_data_direction); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2901 | scb->flags |= IPS_SCB_MAP_SINGLE; |
| 2902 | ips_fill_scb_sg_single(ha, scb->data_busaddr, |
| 2903 | scb, 0, |
| 2904 | SC->request_bufflen); |
| 2905 | scb->dcdb.transfer_length = scb->data_len; |
| 2906 | } else { |
| 2907 | scb->data_busaddr = 0L; |
| 2908 | scb->sg_len = 0; |
| 2909 | scb->data_len = 0; |
| 2910 | scb->dcdb.transfer_length = 0; |
| 2911 | } |
| 2912 | |
| 2913 | } |
| 2914 | |
| 2915 | scb->dcdb.cmd_attribute = |
| 2916 | ips_command_direction[scb->scsi_cmd->cmnd[0]]; |
| 2917 | |
| 2918 | /* Allow a WRITE BUFFER Command to Have no Data */ |
| 2919 | /* This is Used by Tape Flash Utilites */ |
| 2920 | if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0)) |
| 2921 | scb->dcdb.cmd_attribute = 0; |
| 2922 | |
| 2923 | if (!(scb->dcdb.cmd_attribute & 0x3)) |
| 2924 | scb->dcdb.transfer_length = 0; |
| 2925 | |
| 2926 | if (scb->data_len >= IPS_MAX_XFER) { |
| 2927 | scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; |
| 2928 | scb->dcdb.transfer_length = 0; |
| 2929 | } |
| 2930 | if (intr == IPS_INTR_ON) |
| 2931 | IPS_LOCK_SAVE(host->host_lock, cpu_flags); |
| 2932 | |
| 2933 | ret = ips_send_cmd(ha, scb); |
| 2934 | |
| 2935 | switch (ret) { |
| 2936 | case IPS_SUCCESS: |
| 2937 | ips_putq_scb_head(&ha->scb_activelist, scb); |
| 2938 | break; |
| 2939 | case IPS_FAILURE: |
| 2940 | if (scb->scsi_cmd) { |
| 2941 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 2942 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 2943 | } |
| 2944 | |
| 2945 | if (scb->bus) |
| 2946 | ha->dcdb_active[scb->bus - 1] &= |
| 2947 | ~(1 << scb->target_id); |
| 2948 | |
| 2949 | ips_freescb(ha, scb); |
| 2950 | break; |
| 2951 | case IPS_SUCCESS_IMM: |
| 2952 | if (scb->scsi_cmd) |
| 2953 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 2954 | |
| 2955 | if (scb->bus) |
| 2956 | ha->dcdb_active[scb->bus - 1] &= |
| 2957 | ~(1 << scb->target_id); |
| 2958 | |
| 2959 | ips_freescb(ha, scb); |
| 2960 | break; |
| 2961 | default: |
| 2962 | break; |
| 2963 | } /* end case */ |
| 2964 | |
| 2965 | p = (Scsi_Cmnd *) p->host_scribble; |
| 2966 | |
| 2967 | } /* end while */ |
| 2968 | |
| 2969 | if (intr == IPS_INTR_ON) |
| 2970 | IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); |
| 2971 | } |
| 2972 | |
| 2973 | /****************************************************************************/ |
| 2974 | /* */ |
| 2975 | /* Routine Name: ips_putq_scb_head */ |
| 2976 | /* */ |
| 2977 | /* Routine Description: */ |
| 2978 | /* */ |
| 2979 | /* Add an item to the head of the queue */ |
| 2980 | /* */ |
| 2981 | /* ASSUMED to be called from within the HA lock */ |
| 2982 | /* */ |
| 2983 | /****************************************************************************/ |
| 2984 | static void |
| 2985 | ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) |
| 2986 | { |
| 2987 | METHOD_TRACE("ips_putq_scb_head", 1); |
| 2988 | |
| 2989 | if (!item) |
| 2990 | return; |
| 2991 | |
| 2992 | item->q_next = queue->head; |
| 2993 | queue->head = item; |
| 2994 | |
| 2995 | if (!queue->tail) |
| 2996 | queue->tail = item; |
| 2997 | |
| 2998 | queue->count++; |
| 2999 | } |
| 3000 | |
| 3001 | /****************************************************************************/ |
| 3002 | /* */ |
| 3003 | /* Routine Name: ips_removeq_scb_head */ |
| 3004 | /* */ |
| 3005 | /* Routine Description: */ |
| 3006 | /* */ |
| 3007 | /* Remove the head of the queue */ |
| 3008 | /* */ |
| 3009 | /* ASSUMED to be called from within the HA lock */ |
| 3010 | /* */ |
| 3011 | /****************************************************************************/ |
| 3012 | static ips_scb_t * |
| 3013 | ips_removeq_scb_head(ips_scb_queue_t * queue) |
| 3014 | { |
| 3015 | ips_scb_t *item; |
| 3016 | |
| 3017 | METHOD_TRACE("ips_removeq_scb_head", 1); |
| 3018 | |
| 3019 | item = queue->head; |
| 3020 | |
| 3021 | if (!item) { |
| 3022 | return (NULL); |
| 3023 | } |
| 3024 | |
| 3025 | queue->head = item->q_next; |
| 3026 | item->q_next = NULL; |
| 3027 | |
| 3028 | if (queue->tail == item) |
| 3029 | queue->tail = NULL; |
| 3030 | |
| 3031 | queue->count--; |
| 3032 | |
| 3033 | return (item); |
| 3034 | } |
| 3035 | |
| 3036 | /****************************************************************************/ |
| 3037 | /* */ |
| 3038 | /* Routine Name: ips_removeq_scb */ |
| 3039 | /* */ |
| 3040 | /* Routine Description: */ |
| 3041 | /* */ |
| 3042 | /* Remove an item from a queue */ |
| 3043 | /* */ |
| 3044 | /* ASSUMED to be called from within the HA lock */ |
| 3045 | /* */ |
| 3046 | /****************************************************************************/ |
| 3047 | static ips_scb_t * |
| 3048 | ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) |
| 3049 | { |
| 3050 | ips_scb_t *p; |
| 3051 | |
| 3052 | METHOD_TRACE("ips_removeq_scb", 1); |
| 3053 | |
| 3054 | if (!item) |
| 3055 | return (NULL); |
| 3056 | |
| 3057 | if (item == queue->head) { |
| 3058 | return (ips_removeq_scb_head(queue)); |
| 3059 | } |
| 3060 | |
| 3061 | p = queue->head; |
| 3062 | |
| 3063 | while ((p) && (item != p->q_next)) |
| 3064 | p = p->q_next; |
| 3065 | |
| 3066 | if (p) { |
| 3067 | /* found a match */ |
| 3068 | p->q_next = item->q_next; |
| 3069 | |
| 3070 | if (!item->q_next) |
| 3071 | queue->tail = p; |
| 3072 | |
| 3073 | item->q_next = NULL; |
| 3074 | queue->count--; |
| 3075 | |
| 3076 | return (item); |
| 3077 | } |
| 3078 | |
| 3079 | return (NULL); |
| 3080 | } |
| 3081 | |
| 3082 | /****************************************************************************/ |
| 3083 | /* */ |
| 3084 | /* Routine Name: ips_putq_wait_tail */ |
| 3085 | /* */ |
| 3086 | /* Routine Description: */ |
| 3087 | /* */ |
| 3088 | /* Add an item to the tail of the queue */ |
| 3089 | /* */ |
| 3090 | /* ASSUMED to be called from within the HA lock */ |
| 3091 | /* */ |
| 3092 | /****************************************************************************/ |
| 3093 | static void |
| 3094 | ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item) |
| 3095 | { |
| 3096 | METHOD_TRACE("ips_putq_wait_tail", 1); |
| 3097 | |
| 3098 | if (!item) |
| 3099 | return; |
| 3100 | |
| 3101 | item->host_scribble = NULL; |
| 3102 | |
| 3103 | if (queue->tail) |
| 3104 | queue->tail->host_scribble = (char *) item; |
| 3105 | |
| 3106 | queue->tail = item; |
| 3107 | |
| 3108 | if (!queue->head) |
| 3109 | queue->head = item; |
| 3110 | |
| 3111 | queue->count++; |
| 3112 | } |
| 3113 | |
| 3114 | /****************************************************************************/ |
| 3115 | /* */ |
| 3116 | /* Routine Name: ips_removeq_wait_head */ |
| 3117 | /* */ |
| 3118 | /* Routine Description: */ |
| 3119 | /* */ |
| 3120 | /* Remove the head of the queue */ |
| 3121 | /* */ |
| 3122 | /* ASSUMED to be called from within the HA lock */ |
| 3123 | /* */ |
| 3124 | /****************************************************************************/ |
| 3125 | static Scsi_Cmnd * |
| 3126 | ips_removeq_wait_head(ips_wait_queue_t * queue) |
| 3127 | { |
| 3128 | Scsi_Cmnd *item; |
| 3129 | |
| 3130 | METHOD_TRACE("ips_removeq_wait_head", 1); |
| 3131 | |
| 3132 | item = queue->head; |
| 3133 | |
| 3134 | if (!item) { |
| 3135 | return (NULL); |
| 3136 | } |
| 3137 | |
| 3138 | queue->head = (Scsi_Cmnd *) item->host_scribble; |
| 3139 | item->host_scribble = NULL; |
| 3140 | |
| 3141 | if (queue->tail == item) |
| 3142 | queue->tail = NULL; |
| 3143 | |
| 3144 | queue->count--; |
| 3145 | |
| 3146 | return (item); |
| 3147 | } |
| 3148 | |
| 3149 | /****************************************************************************/ |
| 3150 | /* */ |
| 3151 | /* Routine Name: ips_removeq_wait */ |
| 3152 | /* */ |
| 3153 | /* Routine Description: */ |
| 3154 | /* */ |
| 3155 | /* Remove an item from a queue */ |
| 3156 | /* */ |
| 3157 | /* ASSUMED to be called from within the HA lock */ |
| 3158 | /* */ |
| 3159 | /****************************************************************************/ |
| 3160 | static Scsi_Cmnd * |
| 3161 | ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item) |
| 3162 | { |
| 3163 | Scsi_Cmnd *p; |
| 3164 | |
| 3165 | METHOD_TRACE("ips_removeq_wait", 1); |
| 3166 | |
| 3167 | if (!item) |
| 3168 | return (NULL); |
| 3169 | |
| 3170 | if (item == queue->head) { |
| 3171 | return (ips_removeq_wait_head(queue)); |
| 3172 | } |
| 3173 | |
| 3174 | p = queue->head; |
| 3175 | |
| 3176 | while ((p) && (item != (Scsi_Cmnd *) p->host_scribble)) |
| 3177 | p = (Scsi_Cmnd *) p->host_scribble; |
| 3178 | |
| 3179 | if (p) { |
| 3180 | /* found a match */ |
| 3181 | p->host_scribble = item->host_scribble; |
| 3182 | |
| 3183 | if (!item->host_scribble) |
| 3184 | queue->tail = p; |
| 3185 | |
| 3186 | item->host_scribble = NULL; |
| 3187 | queue->count--; |
| 3188 | |
| 3189 | return (item); |
| 3190 | } |
| 3191 | |
| 3192 | return (NULL); |
| 3193 | } |
| 3194 | |
| 3195 | /****************************************************************************/ |
| 3196 | /* */ |
| 3197 | /* Routine Name: ips_putq_copp_tail */ |
| 3198 | /* */ |
| 3199 | /* Routine Description: */ |
| 3200 | /* */ |
| 3201 | /* Add an item to the tail of the queue */ |
| 3202 | /* */ |
| 3203 | /* ASSUMED to be called from within the HA lock */ |
| 3204 | /* */ |
| 3205 | /****************************************************************************/ |
| 3206 | static void |
| 3207 | ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) |
| 3208 | { |
| 3209 | METHOD_TRACE("ips_putq_copp_tail", 1); |
| 3210 | |
| 3211 | if (!item) |
| 3212 | return; |
| 3213 | |
| 3214 | item->next = NULL; |
| 3215 | |
| 3216 | if (queue->tail) |
| 3217 | queue->tail->next = item; |
| 3218 | |
| 3219 | queue->tail = item; |
| 3220 | |
| 3221 | if (!queue->head) |
| 3222 | queue->head = item; |
| 3223 | |
| 3224 | queue->count++; |
| 3225 | } |
| 3226 | |
| 3227 | /****************************************************************************/ |
| 3228 | /* */ |
| 3229 | /* Routine Name: ips_removeq_copp_head */ |
| 3230 | /* */ |
| 3231 | /* Routine Description: */ |
| 3232 | /* */ |
| 3233 | /* Remove the head of the queue */ |
| 3234 | /* */ |
| 3235 | /* ASSUMED to be called from within the HA lock */ |
| 3236 | /* */ |
| 3237 | /****************************************************************************/ |
| 3238 | static ips_copp_wait_item_t * |
| 3239 | ips_removeq_copp_head(ips_copp_queue_t * queue) |
| 3240 | { |
| 3241 | ips_copp_wait_item_t *item; |
| 3242 | |
| 3243 | METHOD_TRACE("ips_removeq_copp_head", 1); |
| 3244 | |
| 3245 | item = queue->head; |
| 3246 | |
| 3247 | if (!item) { |
| 3248 | return (NULL); |
| 3249 | } |
| 3250 | |
| 3251 | queue->head = item->next; |
| 3252 | item->next = NULL; |
| 3253 | |
| 3254 | if (queue->tail == item) |
| 3255 | queue->tail = NULL; |
| 3256 | |
| 3257 | queue->count--; |
| 3258 | |
| 3259 | return (item); |
| 3260 | } |
| 3261 | |
| 3262 | /****************************************************************************/ |
| 3263 | /* */ |
| 3264 | /* Routine Name: ips_removeq_copp */ |
| 3265 | /* */ |
| 3266 | /* Routine Description: */ |
| 3267 | /* */ |
| 3268 | /* Remove an item from a queue */ |
| 3269 | /* */ |
| 3270 | /* ASSUMED to be called from within the HA lock */ |
| 3271 | /* */ |
| 3272 | /****************************************************************************/ |
| 3273 | static ips_copp_wait_item_t * |
| 3274 | ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) |
| 3275 | { |
| 3276 | ips_copp_wait_item_t *p; |
| 3277 | |
| 3278 | METHOD_TRACE("ips_removeq_copp", 1); |
| 3279 | |
| 3280 | if (!item) |
| 3281 | return (NULL); |
| 3282 | |
| 3283 | if (item == queue->head) { |
| 3284 | return (ips_removeq_copp_head(queue)); |
| 3285 | } |
| 3286 | |
| 3287 | p = queue->head; |
| 3288 | |
| 3289 | while ((p) && (item != p->next)) |
| 3290 | p = p->next; |
| 3291 | |
| 3292 | if (p) { |
| 3293 | /* found a match */ |
| 3294 | p->next = item->next; |
| 3295 | |
| 3296 | if (!item->next) |
| 3297 | queue->tail = p; |
| 3298 | |
| 3299 | item->next = NULL; |
| 3300 | queue->count--; |
| 3301 | |
| 3302 | return (item); |
| 3303 | } |
| 3304 | |
| 3305 | return (NULL); |
| 3306 | } |
| 3307 | |
| 3308 | /****************************************************************************/ |
| 3309 | /* */ |
| 3310 | /* Routine Name: ipsintr_blocking */ |
| 3311 | /* */ |
| 3312 | /* Routine Description: */ |
| 3313 | /* */ |
| 3314 | /* Finalize an interrupt for internal commands */ |
| 3315 | /* */ |
| 3316 | /****************************************************************************/ |
| 3317 | static void |
| 3318 | ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) |
| 3319 | { |
| 3320 | METHOD_TRACE("ipsintr_blocking", 2); |
| 3321 | |
| 3322 | ips_freescb(ha, scb); |
| 3323 | if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) { |
| 3324 | ha->waitflag = FALSE; |
| 3325 | |
| 3326 | return; |
| 3327 | } |
| 3328 | } |
| 3329 | |
| 3330 | /****************************************************************************/ |
| 3331 | /* */ |
| 3332 | /* Routine Name: ipsintr_done */ |
| 3333 | /* */ |
| 3334 | /* Routine Description: */ |
| 3335 | /* */ |
| 3336 | /* Finalize an interrupt for non-internal commands */ |
| 3337 | /* */ |
| 3338 | /****************************************************************************/ |
| 3339 | static void |
| 3340 | ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) |
| 3341 | { |
| 3342 | METHOD_TRACE("ipsintr_done", 2); |
| 3343 | |
| 3344 | if (!scb) { |
| 3345 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 3346 | "Spurious interrupt; scb NULL.\n"); |
| 3347 | |
| 3348 | return; |
| 3349 | } |
| 3350 | |
| 3351 | if (scb->scsi_cmd == NULL) { |
| 3352 | /* unexpected interrupt */ |
| 3353 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 3354 | "Spurious interrupt; scsi_cmd not set.\n"); |
| 3355 | |
| 3356 | return; |
| 3357 | } |
| 3358 | |
| 3359 | ips_done(ha, scb); |
| 3360 | } |
| 3361 | |
| 3362 | /****************************************************************************/ |
| 3363 | /* */ |
| 3364 | /* Routine Name: ips_done */ |
| 3365 | /* */ |
| 3366 | /* Routine Description: */ |
| 3367 | /* */ |
| 3368 | /* Do housekeeping on completed commands */ |
| 3369 | /* ASSUMED to be called form within the request lock */ |
| 3370 | /****************************************************************************/ |
| 3371 | static void |
| 3372 | ips_done(ips_ha_t * ha, ips_scb_t * scb) |
| 3373 | { |
| 3374 | int ret; |
| 3375 | |
| 3376 | METHOD_TRACE("ips_done", 1); |
| 3377 | |
| 3378 | if (!scb) |
| 3379 | return; |
| 3380 | |
| 3381 | if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) { |
| 3382 | ips_cleanup_passthru(ha, scb); |
| 3383 | ha->num_ioctl--; |
| 3384 | } else { |
| 3385 | /* |
| 3386 | * Check to see if this command had too much |
| 3387 | * data and had to be broke up. If so, queue |
| 3388 | * the rest of the data and continue. |
| 3389 | */ |
| 3390 | if ((scb->breakup) || (scb->sg_break)) { |
| 3391 | /* we had a data breakup */ |
| 3392 | scb->data_len = 0; |
| 3393 | |
| 3394 | if (scb->sg_count) { |
| 3395 | /* S/G request */ |
| 3396 | struct scatterlist *sg; |
| 3397 | int ips_sg_index = 0; |
| 3398 | int sg_dma_index; |
| 3399 | |
| 3400 | sg = scb->scsi_cmd->request_buffer; |
| 3401 | |
| 3402 | /* Spin forward to last dma chunk */ |
| 3403 | sg_dma_index = scb->breakup; |
| 3404 | |
| 3405 | /* Take care of possible partial on last chunk */ |
| 3406 | ips_fill_scb_sg_single(ha, |
| 3407 | sg_dma_address(&sg |
| 3408 | [sg_dma_index]), |
| 3409 | scb, ips_sg_index++, |
| 3410 | sg_dma_len(&sg |
| 3411 | [sg_dma_index])); |
| 3412 | |
| 3413 | for (; sg_dma_index < scb->sg_count; |
| 3414 | sg_dma_index++) { |
| 3415 | if (ips_fill_scb_sg_single |
| 3416 | (ha, |
| 3417 | sg_dma_address(&sg[sg_dma_index]), |
| 3418 | scb, ips_sg_index++, |
| 3419 | sg_dma_len(&sg[sg_dma_index])) < 0) |
| 3420 | break; |
| 3421 | |
| 3422 | } |
| 3423 | |
| 3424 | } else { |
| 3425 | /* Non S/G Request */ |
| 3426 | (void) ips_fill_scb_sg_single(ha, |
| 3427 | scb-> |
| 3428 | data_busaddr + |
| 3429 | (scb->sg_break * |
| 3430 | ha->max_xfer), |
| 3431 | scb, 0, |
| 3432 | scb->scsi_cmd-> |
| 3433 | request_bufflen - |
| 3434 | (scb->sg_break * |
| 3435 | ha->max_xfer)); |
| 3436 | } |
| 3437 | |
| 3438 | scb->dcdb.transfer_length = scb->data_len; |
| 3439 | scb->dcdb.cmd_attribute |= |
| 3440 | ips_command_direction[scb->scsi_cmd->cmnd[0]]; |
| 3441 | |
| 3442 | if (!(scb->dcdb.cmd_attribute & 0x3)) |
| 3443 | scb->dcdb.transfer_length = 0; |
| 3444 | |
| 3445 | if (scb->data_len >= IPS_MAX_XFER) { |
| 3446 | scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; |
| 3447 | scb->dcdb.transfer_length = 0; |
| 3448 | } |
| 3449 | |
| 3450 | ret = ips_send_cmd(ha, scb); |
| 3451 | |
| 3452 | switch (ret) { |
| 3453 | case IPS_FAILURE: |
| 3454 | if (scb->scsi_cmd) { |
| 3455 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 3456 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 3457 | } |
| 3458 | |
| 3459 | ips_freescb(ha, scb); |
| 3460 | break; |
| 3461 | case IPS_SUCCESS_IMM: |
| 3462 | if (scb->scsi_cmd) { |
| 3463 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 3464 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 3465 | } |
| 3466 | |
| 3467 | ips_freescb(ha, scb); |
| 3468 | break; |
| 3469 | default: |
| 3470 | break; |
| 3471 | } /* end case */ |
| 3472 | |
| 3473 | return; |
| 3474 | } |
| 3475 | } /* end if passthru */ |
| 3476 | |
| 3477 | if (scb->bus) { |
| 3478 | ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); |
| 3479 | } |
| 3480 | |
| 3481 | scb->scsi_cmd->scsi_done(scb->scsi_cmd); |
| 3482 | |
| 3483 | ips_freescb(ha, scb); |
| 3484 | } |
| 3485 | |
| 3486 | /****************************************************************************/ |
| 3487 | /* */ |
| 3488 | /* Routine Name: ips_map_status */ |
| 3489 | /* */ |
| 3490 | /* Routine Description: */ |
| 3491 | /* */ |
| 3492 | /* Map Controller Error codes to Linux Error Codes */ |
| 3493 | /* */ |
| 3494 | /****************************************************************************/ |
| 3495 | static int |
| 3496 | ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) |
| 3497 | { |
| 3498 | int errcode; |
| 3499 | int device_error; |
| 3500 | uint32_t transfer_len; |
| 3501 | IPS_DCDB_TABLE_TAPE *tapeDCDB; |
Jack Hammer | a5b3c86 | 2006-01-31 13:17:55 -0500 | [diff] [blame] | 3502 | IPS_SCSI_INQ_DATA inquiryData; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3503 | |
| 3504 | METHOD_TRACE("ips_map_status", 1); |
| 3505 | |
| 3506 | if (scb->bus) { |
| 3507 | DEBUG_VAR(2, |
| 3508 | "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x", |
| 3509 | ips_name, ha->host_num, |
| 3510 | scb->scsi_cmd->device->channel, |
| 3511 | scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, |
| 3512 | scb->basic_status, scb->extended_status, |
| 3513 | scb->extended_status == |
| 3514 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, |
| 3515 | scb->extended_status == |
| 3516 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, |
| 3517 | scb->extended_status == |
| 3518 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); |
| 3519 | } |
| 3520 | |
| 3521 | /* default driver error */ |
| 3522 | errcode = DID_ERROR; |
| 3523 | device_error = 0; |
| 3524 | |
| 3525 | switch (scb->basic_status & IPS_GSC_STATUS_MASK) { |
| 3526 | case IPS_CMD_TIMEOUT: |
| 3527 | errcode = DID_TIME_OUT; |
| 3528 | break; |
| 3529 | |
| 3530 | case IPS_INVAL_OPCO: |
| 3531 | case IPS_INVAL_CMD_BLK: |
| 3532 | case IPS_INVAL_PARM_BLK: |
| 3533 | case IPS_LD_ERROR: |
| 3534 | case IPS_CMD_CMPLT_WERROR: |
| 3535 | break; |
| 3536 | |
| 3537 | case IPS_PHYS_DRV_ERROR: |
| 3538 | switch (scb->extended_status) { |
| 3539 | case IPS_ERR_SEL_TO: |
| 3540 | if (scb->bus) |
| 3541 | errcode = DID_NO_CONNECT; |
| 3542 | |
| 3543 | break; |
| 3544 | |
| 3545 | case IPS_ERR_OU_RUN: |
| 3546 | if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || |
| 3547 | (scb->cmd.dcdb.op_code == |
| 3548 | IPS_CMD_EXTENDED_DCDB_SG)) { |
| 3549 | tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; |
| 3550 | transfer_len = tapeDCDB->transfer_length; |
| 3551 | } else { |
| 3552 | transfer_len = |
| 3553 | (uint32_t) scb->dcdb.transfer_length; |
| 3554 | } |
| 3555 | |
| 3556 | if ((scb->bus) && (transfer_len < scb->data_len)) { |
| 3557 | /* Underrun - set default to no error */ |
| 3558 | errcode = DID_OK; |
| 3559 | |
| 3560 | /* Restrict access to physical DASD */ |
Jack Hammer | a5b3c86 | 2006-01-31 13:17:55 -0500 | [diff] [blame] | 3561 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
| 3562 | ips_scmd_buf_read(scb->scsi_cmd, |
| 3563 | &inquiryData, sizeof (inquiryData)); |
| 3564 | if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { |
| 3565 | errcode = DID_TIME_OUT; |
| 3566 | break; |
| 3567 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3568 | } |
| 3569 | } else |
| 3570 | errcode = DID_ERROR; |
| 3571 | |
| 3572 | break; |
| 3573 | |
| 3574 | case IPS_ERR_RECOVERY: |
| 3575 | /* don't fail recovered errors */ |
| 3576 | if (scb->bus) |
| 3577 | errcode = DID_OK; |
| 3578 | |
| 3579 | break; |
| 3580 | |
| 3581 | case IPS_ERR_HOST_RESET: |
| 3582 | case IPS_ERR_DEV_RESET: |
| 3583 | errcode = DID_RESET; |
| 3584 | break; |
| 3585 | |
| 3586 | case IPS_ERR_CKCOND: |
| 3587 | if (scb->bus) { |
| 3588 | if ((scb->cmd.dcdb.op_code == |
| 3589 | IPS_CMD_EXTENDED_DCDB) |
| 3590 | || (scb->cmd.dcdb.op_code == |
| 3591 | IPS_CMD_EXTENDED_DCDB_SG)) { |
| 3592 | tapeDCDB = |
| 3593 | (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; |
| 3594 | memcpy(scb->scsi_cmd->sense_buffer, |
| 3595 | tapeDCDB->sense_info, |
| 3596 | sizeof (scb->scsi_cmd-> |
| 3597 | sense_buffer)); |
| 3598 | } else { |
| 3599 | memcpy(scb->scsi_cmd->sense_buffer, |
| 3600 | scb->dcdb.sense_info, |
| 3601 | sizeof (scb->scsi_cmd-> |
| 3602 | sense_buffer)); |
| 3603 | } |
| 3604 | device_error = 2; /* check condition */ |
| 3605 | } |
| 3606 | |
| 3607 | errcode = DID_OK; |
| 3608 | |
| 3609 | break; |
| 3610 | |
| 3611 | default: |
| 3612 | errcode = DID_ERROR; |
| 3613 | break; |
| 3614 | |
| 3615 | } /* end switch */ |
| 3616 | } /* end switch */ |
| 3617 | |
| 3618 | scb->scsi_cmd->result = device_error | (errcode << 16); |
| 3619 | |
| 3620 | return (1); |
| 3621 | } |
| 3622 | |
| 3623 | /****************************************************************************/ |
| 3624 | /* */ |
| 3625 | /* Routine Name: ips_send_wait */ |
| 3626 | /* */ |
| 3627 | /* Routine Description: */ |
| 3628 | /* */ |
| 3629 | /* Send a command to the controller and wait for it to return */ |
| 3630 | /* */ |
| 3631 | /* The FFDC Time Stamp use this function for the callback, but doesn't */ |
| 3632 | /* actually need to wait. */ |
| 3633 | /****************************************************************************/ |
| 3634 | static int |
| 3635 | ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) |
| 3636 | { |
| 3637 | int ret; |
| 3638 | |
| 3639 | METHOD_TRACE("ips_send_wait", 1); |
| 3640 | |
| 3641 | if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ |
| 3642 | ha->waitflag = TRUE; |
| 3643 | ha->cmd_in_progress = scb->cdb[0]; |
| 3644 | } |
| 3645 | scb->callback = ipsintr_blocking; |
| 3646 | ret = ips_send_cmd(ha, scb); |
| 3647 | |
| 3648 | if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) |
| 3649 | return (ret); |
| 3650 | |
| 3651 | if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ |
| 3652 | ret = ips_wait(ha, timeout, intr); |
| 3653 | |
| 3654 | return (ret); |
| 3655 | } |
| 3656 | |
| 3657 | /****************************************************************************/ |
| 3658 | /* */ |
| 3659 | /* Routine Name: ips_scmd_buf_write */ |
| 3660 | /* */ |
| 3661 | /* Routine Description: */ |
| 3662 | /* Write data to Scsi_Cmnd request_buffer at proper offsets */ |
| 3663 | /****************************************************************************/ |
| 3664 | static void |
| 3665 | ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned |
| 3666 | int count) |
| 3667 | { |
| 3668 | if (scmd->use_sg) { |
| 3669 | int i; |
| 3670 | unsigned int min_cnt, xfer_cnt; |
| 3671 | char *cdata = (char *) data; |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 3672 | unsigned char *buffer; |
| 3673 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3674 | struct scatterlist *sg = scmd->request_buffer; |
| 3675 | for (i = 0, xfer_cnt = 0; |
| 3676 | (i < scmd->use_sg) && (xfer_cnt < count); i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3677 | min_cnt = min(count - xfer_cnt, sg[i].length); |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 3678 | |
| 3679 | /* kmap_atomic() ensures addressability of the data buffer.*/ |
| 3680 | /* local_irq_save() protects the KM_IRQ0 address slot. */ |
| 3681 | local_irq_save(flags); |
| 3682 | buffer = kmap_atomic(sg[i].page, KM_IRQ0) + sg[i].offset; |
| 3683 | memcpy(buffer, &cdata[xfer_cnt], min_cnt); |
| 3684 | kunmap_atomic(buffer - sg[i].offset, KM_IRQ0); |
| 3685 | local_irq_restore(flags); |
| 3686 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3687 | xfer_cnt += min_cnt; |
| 3688 | } |
| 3689 | |
| 3690 | } else { |
| 3691 | unsigned int min_cnt = min(count, scmd->request_bufflen); |
| 3692 | memcpy(scmd->request_buffer, data, min_cnt); |
| 3693 | } |
| 3694 | } |
| 3695 | |
| 3696 | /****************************************************************************/ |
| 3697 | /* */ |
| 3698 | /* Routine Name: ips_scmd_buf_read */ |
| 3699 | /* */ |
| 3700 | /* Routine Description: */ |
| 3701 | /* Copy data from a Scsi_Cmnd to a new, linear buffer */ |
| 3702 | /****************************************************************************/ |
| 3703 | static void |
| 3704 | ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned |
| 3705 | int count) |
| 3706 | { |
| 3707 | if (scmd->use_sg) { |
| 3708 | int i; |
| 3709 | unsigned int min_cnt, xfer_cnt; |
| 3710 | char *cdata = (char *) data; |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 3711 | unsigned char *buffer; |
| 3712 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3713 | struct scatterlist *sg = scmd->request_buffer; |
| 3714 | for (i = 0, xfer_cnt = 0; |
| 3715 | (i < scmd->use_sg) && (xfer_cnt < count); i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3716 | min_cnt = min(count - xfer_cnt, sg[i].length); |
Jack Hammer | a3632fa | 2005-10-25 14:13:03 -0400 | [diff] [blame] | 3717 | |
| 3718 | /* kmap_atomic() ensures addressability of the data buffer.*/ |
| 3719 | /* local_irq_save() protects the KM_IRQ0 address slot. */ |
| 3720 | local_irq_save(flags); |
| 3721 | buffer = kmap_atomic(sg[i].page, KM_IRQ0) + sg[i].offset; |
| 3722 | memcpy(&cdata[xfer_cnt], buffer, min_cnt); |
| 3723 | kunmap_atomic(buffer - sg[i].offset, KM_IRQ0); |
| 3724 | local_irq_restore(flags); |
| 3725 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3726 | xfer_cnt += min_cnt; |
| 3727 | } |
| 3728 | |
| 3729 | } else { |
| 3730 | unsigned int min_cnt = min(count, scmd->request_bufflen); |
| 3731 | memcpy(data, scmd->request_buffer, min_cnt); |
| 3732 | } |
| 3733 | } |
| 3734 | |
| 3735 | /****************************************************************************/ |
| 3736 | /* */ |
| 3737 | /* Routine Name: ips_send_cmd */ |
| 3738 | /* */ |
| 3739 | /* Routine Description: */ |
| 3740 | /* */ |
| 3741 | /* Map SCSI commands to ServeRAID commands for logical drives */ |
| 3742 | /* */ |
| 3743 | /****************************************************************************/ |
| 3744 | static int |
| 3745 | ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) |
| 3746 | { |
| 3747 | int ret; |
| 3748 | char *sp; |
| 3749 | int device_error; |
| 3750 | IPS_DCDB_TABLE_TAPE *tapeDCDB; |
| 3751 | int TimeOut; |
| 3752 | |
| 3753 | METHOD_TRACE("ips_send_cmd", 1); |
| 3754 | |
| 3755 | ret = IPS_SUCCESS; |
| 3756 | |
| 3757 | if (!scb->scsi_cmd) { |
| 3758 | /* internal command */ |
| 3759 | |
| 3760 | if (scb->bus > 0) { |
| 3761 | /* Controller commands can't be issued */ |
| 3762 | /* to real devices -- fail them */ |
| 3763 | if ((ha->waitflag == TRUE) && |
| 3764 | (ha->cmd_in_progress == scb->cdb[0])) { |
| 3765 | ha->waitflag = FALSE; |
| 3766 | } |
| 3767 | |
| 3768 | return (1); |
| 3769 | } |
| 3770 | } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) { |
| 3771 | /* command to logical bus -- interpret */ |
| 3772 | ret = IPS_SUCCESS_IMM; |
| 3773 | |
| 3774 | switch (scb->scsi_cmd->cmnd[0]) { |
| 3775 | case ALLOW_MEDIUM_REMOVAL: |
| 3776 | case REZERO_UNIT: |
| 3777 | case ERASE: |
| 3778 | case WRITE_FILEMARKS: |
| 3779 | case SPACE: |
| 3780 | scb->scsi_cmd->result = DID_ERROR << 16; |
| 3781 | break; |
| 3782 | |
| 3783 | case START_STOP: |
| 3784 | scb->scsi_cmd->result = DID_OK << 16; |
| 3785 | |
| 3786 | case TEST_UNIT_READY: |
| 3787 | case INQUIRY: |
| 3788 | if (scb->target_id == IPS_ADAPTER_ID) { |
| 3789 | /* |
| 3790 | * Either we have a TUR |
| 3791 | * or we have a SCSI inquiry |
| 3792 | */ |
| 3793 | if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) |
| 3794 | scb->scsi_cmd->result = DID_OK << 16; |
| 3795 | |
| 3796 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
| 3797 | IPS_SCSI_INQ_DATA inquiry; |
| 3798 | |
| 3799 | memset(&inquiry, 0, |
| 3800 | sizeof (IPS_SCSI_INQ_DATA)); |
| 3801 | |
| 3802 | inquiry.DeviceType = |
| 3803 | IPS_SCSI_INQ_TYPE_PROCESSOR; |
| 3804 | inquiry.DeviceTypeQualifier = |
| 3805 | IPS_SCSI_INQ_LU_CONNECTED; |
| 3806 | inquiry.Version = IPS_SCSI_INQ_REV2; |
| 3807 | inquiry.ResponseDataFormat = |
| 3808 | IPS_SCSI_INQ_RD_REV2; |
| 3809 | inquiry.AdditionalLength = 31; |
| 3810 | inquiry.Flags[0] = |
| 3811 | IPS_SCSI_INQ_Address16; |
| 3812 | inquiry.Flags[1] = |
| 3813 | IPS_SCSI_INQ_WBus16 | |
| 3814 | IPS_SCSI_INQ_Sync; |
| 3815 | strncpy(inquiry.VendorId, "IBM ", |
| 3816 | 8); |
| 3817 | strncpy(inquiry.ProductId, |
| 3818 | "SERVERAID ", 16); |
| 3819 | strncpy(inquiry.ProductRevisionLevel, |
| 3820 | "1.00", 4); |
| 3821 | |
| 3822 | ips_scmd_buf_write(scb->scsi_cmd, |
| 3823 | &inquiry, |
| 3824 | sizeof (inquiry)); |
| 3825 | |
| 3826 | scb->scsi_cmd->result = DID_OK << 16; |
| 3827 | } |
| 3828 | } else { |
| 3829 | scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; |
| 3830 | scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); |
| 3831 | scb->cmd.logical_info.reserved = 0; |
| 3832 | scb->cmd.logical_info.reserved2 = 0; |
| 3833 | scb->data_len = sizeof (IPS_LD_INFO); |
| 3834 | scb->data_busaddr = ha->logical_drive_info_dma_addr; |
| 3835 | scb->flags = 0; |
| 3836 | scb->cmd.logical_info.buffer_addr = scb->data_busaddr; |
| 3837 | ret = IPS_SUCCESS; |
| 3838 | } |
| 3839 | |
| 3840 | break; |
| 3841 | |
| 3842 | case REQUEST_SENSE: |
| 3843 | ips_reqsen(ha, scb); |
| 3844 | scb->scsi_cmd->result = DID_OK << 16; |
| 3845 | break; |
| 3846 | |
| 3847 | case READ_6: |
| 3848 | case WRITE_6: |
| 3849 | if (!scb->sg_len) { |
| 3850 | scb->cmd.basic_io.op_code = |
| 3851 | (scb->scsi_cmd->cmnd[0] == |
| 3852 | READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; |
| 3853 | scb->cmd.basic_io.enhanced_sg = 0; |
| 3854 | scb->cmd.basic_io.sg_addr = |
| 3855 | cpu_to_le32(scb->data_busaddr); |
| 3856 | } else { |
| 3857 | scb->cmd.basic_io.op_code = |
| 3858 | (scb->scsi_cmd->cmnd[0] == |
| 3859 | READ_6) ? IPS_CMD_READ_SG : |
| 3860 | IPS_CMD_WRITE_SG; |
| 3861 | scb->cmd.basic_io.enhanced_sg = |
| 3862 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
| 3863 | scb->cmd.basic_io.sg_addr = |
| 3864 | cpu_to_le32(scb->sg_busaddr); |
| 3865 | } |
| 3866 | |
| 3867 | scb->cmd.basic_io.segment_4G = 0; |
| 3868 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 3869 | scb->cmd.basic_io.log_drv = scb->target_id; |
| 3870 | scb->cmd.basic_io.sg_count = scb->sg_len; |
| 3871 | |
| 3872 | if (scb->cmd.basic_io.lba) |
| 3873 | scb->cmd.basic_io.lba = |
| 3874 | cpu_to_le32(le32_to_cpu |
| 3875 | (scb->cmd.basic_io.lba) + |
| 3876 | le16_to_cpu(scb->cmd.basic_io. |
| 3877 | sector_count)); |
| 3878 | else |
| 3879 | scb->cmd.basic_io.lba = |
| 3880 | (((scb->scsi_cmd-> |
| 3881 | cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> |
| 3882 | cmnd[2] << 8) | |
| 3883 | (scb->scsi_cmd->cmnd[3])); |
| 3884 | |
| 3885 | scb->cmd.basic_io.sector_count = |
| 3886 | cpu_to_le16(scb->data_len / IPS_BLKSIZE); |
| 3887 | |
| 3888 | if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) |
| 3889 | scb->cmd.basic_io.sector_count = |
| 3890 | cpu_to_le16(256); |
| 3891 | |
| 3892 | ret = IPS_SUCCESS; |
| 3893 | break; |
| 3894 | |
| 3895 | case READ_10: |
| 3896 | case WRITE_10: |
| 3897 | if (!scb->sg_len) { |
| 3898 | scb->cmd.basic_io.op_code = |
| 3899 | (scb->scsi_cmd->cmnd[0] == |
| 3900 | READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; |
| 3901 | scb->cmd.basic_io.enhanced_sg = 0; |
| 3902 | scb->cmd.basic_io.sg_addr = |
| 3903 | cpu_to_le32(scb->data_busaddr); |
| 3904 | } else { |
| 3905 | scb->cmd.basic_io.op_code = |
| 3906 | (scb->scsi_cmd->cmnd[0] == |
| 3907 | READ_10) ? IPS_CMD_READ_SG : |
| 3908 | IPS_CMD_WRITE_SG; |
| 3909 | scb->cmd.basic_io.enhanced_sg = |
| 3910 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
| 3911 | scb->cmd.basic_io.sg_addr = |
| 3912 | cpu_to_le32(scb->sg_busaddr); |
| 3913 | } |
| 3914 | |
| 3915 | scb->cmd.basic_io.segment_4G = 0; |
| 3916 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 3917 | scb->cmd.basic_io.log_drv = scb->target_id; |
| 3918 | scb->cmd.basic_io.sg_count = scb->sg_len; |
| 3919 | |
| 3920 | if (scb->cmd.basic_io.lba) |
| 3921 | scb->cmd.basic_io.lba = |
| 3922 | cpu_to_le32(le32_to_cpu |
| 3923 | (scb->cmd.basic_io.lba) + |
| 3924 | le16_to_cpu(scb->cmd.basic_io. |
| 3925 | sector_count)); |
| 3926 | else |
| 3927 | scb->cmd.basic_io.lba = |
| 3928 | ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> |
| 3929 | scsi_cmd-> |
| 3930 | cmnd[3] |
| 3931 | << 16) | |
| 3932 | (scb->scsi_cmd->cmnd[4] << 8) | scb-> |
| 3933 | scsi_cmd->cmnd[5]); |
| 3934 | |
| 3935 | scb->cmd.basic_io.sector_count = |
| 3936 | cpu_to_le16(scb->data_len / IPS_BLKSIZE); |
| 3937 | |
| 3938 | if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { |
| 3939 | /* |
| 3940 | * This is a null condition |
| 3941 | * we don't have to do anything |
| 3942 | * so just return |
| 3943 | */ |
| 3944 | scb->scsi_cmd->result = DID_OK << 16; |
| 3945 | } else |
| 3946 | ret = IPS_SUCCESS; |
| 3947 | |
| 3948 | break; |
| 3949 | |
| 3950 | case RESERVE: |
| 3951 | case RELEASE: |
| 3952 | scb->scsi_cmd->result = DID_OK << 16; |
| 3953 | break; |
| 3954 | |
| 3955 | case MODE_SENSE: |
| 3956 | scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; |
| 3957 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 3958 | scb->cmd.basic_io.segment_4G = 0; |
| 3959 | scb->cmd.basic_io.enhanced_sg = 0; |
| 3960 | scb->data_len = sizeof (*ha->enq); |
| 3961 | scb->cmd.basic_io.sg_addr = ha->enq_busaddr; |
| 3962 | ret = IPS_SUCCESS; |
| 3963 | break; |
| 3964 | |
| 3965 | case READ_CAPACITY: |
| 3966 | scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; |
| 3967 | scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); |
| 3968 | scb->cmd.logical_info.reserved = 0; |
| 3969 | scb->cmd.logical_info.reserved2 = 0; |
| 3970 | scb->cmd.logical_info.reserved3 = 0; |
| 3971 | scb->data_len = sizeof (IPS_LD_INFO); |
| 3972 | scb->data_busaddr = ha->logical_drive_info_dma_addr; |
| 3973 | scb->flags = 0; |
| 3974 | scb->cmd.logical_info.buffer_addr = scb->data_busaddr; |
| 3975 | ret = IPS_SUCCESS; |
| 3976 | break; |
| 3977 | |
| 3978 | case SEND_DIAGNOSTIC: |
| 3979 | case REASSIGN_BLOCKS: |
| 3980 | case FORMAT_UNIT: |
| 3981 | case SEEK_10: |
| 3982 | case VERIFY: |
| 3983 | case READ_DEFECT_DATA: |
| 3984 | case READ_BUFFER: |
| 3985 | case WRITE_BUFFER: |
| 3986 | scb->scsi_cmd->result = DID_OK << 16; |
| 3987 | break; |
| 3988 | |
| 3989 | default: |
| 3990 | /* Set the Return Info to appear like the Command was */ |
| 3991 | /* attempted, a Check Condition occurred, and Sense */ |
| 3992 | /* Data indicating an Invalid CDB OpCode is returned. */ |
| 3993 | sp = (char *) scb->scsi_cmd->sense_buffer; |
| 3994 | memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer)); |
| 3995 | |
| 3996 | sp[0] = 0x70; /* Error Code */ |
| 3997 | sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ |
| 3998 | sp[7] = 0x0A; /* Additional Sense Length */ |
| 3999 | sp[12] = 0x20; /* ASC = Invalid OpCode */ |
| 4000 | sp[13] = 0x00; /* ASCQ */ |
| 4001 | |
| 4002 | device_error = 2; /* Indicate Check Condition */ |
| 4003 | scb->scsi_cmd->result = device_error | (DID_OK << 16); |
| 4004 | break; |
| 4005 | } /* end switch */ |
| 4006 | } |
| 4007 | /* end if */ |
| 4008 | if (ret == IPS_SUCCESS_IMM) |
| 4009 | return (ret); |
| 4010 | |
| 4011 | /* setup DCDB */ |
| 4012 | if (scb->bus > 0) { |
| 4013 | |
| 4014 | /* If we already know the Device is Not there, no need to attempt a Command */ |
| 4015 | /* This also protects an NT FailOver Controller from getting CDB's sent to it */ |
| 4016 | if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { |
| 4017 | scb->scsi_cmd->result = DID_NO_CONNECT << 16; |
| 4018 | return (IPS_SUCCESS_IMM); |
| 4019 | } |
| 4020 | |
| 4021 | ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); |
| 4022 | scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); |
| 4023 | scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + |
| 4024 | (unsigned long) &scb-> |
| 4025 | dcdb - |
| 4026 | (unsigned long) scb); |
| 4027 | scb->cmd.dcdb.reserved = 0; |
| 4028 | scb->cmd.dcdb.reserved2 = 0; |
| 4029 | scb->cmd.dcdb.reserved3 = 0; |
| 4030 | scb->cmd.dcdb.segment_4G = 0; |
| 4031 | scb->cmd.dcdb.enhanced_sg = 0; |
| 4032 | |
| 4033 | TimeOut = scb->scsi_cmd->timeout_per_command; |
| 4034 | |
| 4035 | if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ |
| 4036 | if (!scb->sg_len) { |
| 4037 | scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; |
| 4038 | } else { |
| 4039 | scb->cmd.dcdb.op_code = |
| 4040 | IPS_CMD_EXTENDED_DCDB_SG; |
| 4041 | scb->cmd.dcdb.enhanced_sg = |
| 4042 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
| 4043 | } |
| 4044 | |
| 4045 | tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ |
| 4046 | tapeDCDB->device_address = |
| 4047 | ((scb->bus - 1) << 4) | scb->target_id; |
| 4048 | tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; |
| 4049 | tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ |
| 4050 | |
| 4051 | if (TimeOut) { |
| 4052 | if (TimeOut < (10 * HZ)) |
| 4053 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ |
| 4054 | else if (TimeOut < (60 * HZ)) |
| 4055 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ |
| 4056 | else if (TimeOut < (1200 * HZ)) |
| 4057 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ |
| 4058 | } |
| 4059 | |
| 4060 | tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; |
| 4061 | tapeDCDB->reserved_for_LUN = 0; |
| 4062 | tapeDCDB->transfer_length = scb->data_len; |
| 4063 | if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) |
| 4064 | tapeDCDB->buffer_pointer = |
| 4065 | cpu_to_le32(scb->sg_busaddr); |
| 4066 | else |
| 4067 | tapeDCDB->buffer_pointer = |
| 4068 | cpu_to_le32(scb->data_busaddr); |
| 4069 | tapeDCDB->sg_count = scb->sg_len; |
| 4070 | tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); |
| 4071 | tapeDCDB->scsi_status = 0; |
| 4072 | tapeDCDB->reserved = 0; |
| 4073 | memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, |
| 4074 | scb->scsi_cmd->cmd_len); |
| 4075 | } else { |
| 4076 | if (!scb->sg_len) { |
| 4077 | scb->cmd.dcdb.op_code = IPS_CMD_DCDB; |
| 4078 | } else { |
| 4079 | scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; |
| 4080 | scb->cmd.dcdb.enhanced_sg = |
| 4081 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
| 4082 | } |
| 4083 | |
| 4084 | scb->dcdb.device_address = |
| 4085 | ((scb->bus - 1) << 4) | scb->target_id; |
| 4086 | scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; |
| 4087 | |
| 4088 | if (TimeOut) { |
| 4089 | if (TimeOut < (10 * HZ)) |
| 4090 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ |
| 4091 | else if (TimeOut < (60 * HZ)) |
| 4092 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ |
| 4093 | else if (TimeOut < (1200 * HZ)) |
| 4094 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ |
| 4095 | } |
| 4096 | |
| 4097 | scb->dcdb.transfer_length = scb->data_len; |
| 4098 | if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) |
| 4099 | scb->dcdb.transfer_length = 0; |
| 4100 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) |
| 4101 | scb->dcdb.buffer_pointer = |
| 4102 | cpu_to_le32(scb->sg_busaddr); |
| 4103 | else |
| 4104 | scb->dcdb.buffer_pointer = |
| 4105 | cpu_to_le32(scb->data_busaddr); |
| 4106 | scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; |
| 4107 | scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); |
| 4108 | scb->dcdb.sg_count = scb->sg_len; |
| 4109 | scb->dcdb.reserved = 0; |
| 4110 | memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, |
| 4111 | scb->scsi_cmd->cmd_len); |
| 4112 | scb->dcdb.scsi_status = 0; |
| 4113 | scb->dcdb.reserved2[0] = 0; |
| 4114 | scb->dcdb.reserved2[1] = 0; |
| 4115 | scb->dcdb.reserved2[2] = 0; |
| 4116 | } |
| 4117 | } |
| 4118 | |
| 4119 | return ((*ha->func.issue) (ha, scb)); |
| 4120 | } |
| 4121 | |
| 4122 | /****************************************************************************/ |
| 4123 | /* */ |
| 4124 | /* Routine Name: ips_chk_status */ |
| 4125 | /* */ |
| 4126 | /* Routine Description: */ |
| 4127 | /* */ |
| 4128 | /* Check the status of commands to logical drives */ |
| 4129 | /* Assumed to be called with the HA lock */ |
| 4130 | /****************************************************************************/ |
| 4131 | static void |
| 4132 | ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) |
| 4133 | { |
| 4134 | ips_scb_t *scb; |
| 4135 | ips_stat_t *sp; |
| 4136 | uint8_t basic_status; |
| 4137 | uint8_t ext_status; |
| 4138 | int errcode; |
Jack Hammer | a5b3c86 | 2006-01-31 13:17:55 -0500 | [diff] [blame] | 4139 | IPS_SCSI_INQ_DATA inquiryData; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4140 | |
| 4141 | METHOD_TRACE("ips_chkstatus", 1); |
| 4142 | |
| 4143 | scb = &ha->scbs[pstatus->fields.command_id]; |
| 4144 | scb->basic_status = basic_status = |
| 4145 | pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; |
| 4146 | scb->extended_status = ext_status = pstatus->fields.extended_status; |
| 4147 | |
| 4148 | sp = &ha->sp; |
| 4149 | sp->residue_len = 0; |
| 4150 | sp->scb_addr = (void *) scb; |
| 4151 | |
| 4152 | /* Remove the item from the active queue */ |
| 4153 | ips_removeq_scb(&ha->scb_activelist, scb); |
| 4154 | |
| 4155 | if (!scb->scsi_cmd) |
| 4156 | /* internal commands are handled in do_ipsintr */ |
| 4157 | return; |
| 4158 | |
| 4159 | DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)", |
| 4160 | ips_name, |
| 4161 | ha->host_num, |
| 4162 | scb->cdb[0], |
| 4163 | scb->cmd.basic_io.command_id, |
| 4164 | scb->bus, scb->target_id, scb->lun); |
| 4165 | |
| 4166 | if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) |
| 4167 | /* passthru - just returns the raw result */ |
| 4168 | return; |
| 4169 | |
| 4170 | errcode = DID_OK; |
| 4171 | |
| 4172 | if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || |
| 4173 | ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { |
| 4174 | |
| 4175 | if (scb->bus == 0) { |
| 4176 | if ((basic_status & IPS_GSC_STATUS_MASK) == |
| 4177 | IPS_CMD_RECOVERED_ERROR) { |
| 4178 | DEBUG_VAR(1, |
| 4179 | "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", |
| 4180 | ips_name, ha->host_num, |
| 4181 | scb->cmd.basic_io.op_code, |
| 4182 | basic_status, ext_status); |
| 4183 | } |
| 4184 | |
| 4185 | switch (scb->scsi_cmd->cmnd[0]) { |
| 4186 | case ALLOW_MEDIUM_REMOVAL: |
| 4187 | case REZERO_UNIT: |
| 4188 | case ERASE: |
| 4189 | case WRITE_FILEMARKS: |
| 4190 | case SPACE: |
| 4191 | errcode = DID_ERROR; |
| 4192 | break; |
| 4193 | |
| 4194 | case START_STOP: |
| 4195 | break; |
| 4196 | |
| 4197 | case TEST_UNIT_READY: |
| 4198 | if (!ips_online(ha, scb)) { |
| 4199 | errcode = DID_TIME_OUT; |
| 4200 | } |
| 4201 | break; |
| 4202 | |
| 4203 | case INQUIRY: |
| 4204 | if (ips_online(ha, scb)) { |
| 4205 | ips_inquiry(ha, scb); |
| 4206 | } else { |
| 4207 | errcode = DID_TIME_OUT; |
| 4208 | } |
| 4209 | break; |
| 4210 | |
| 4211 | case REQUEST_SENSE: |
| 4212 | ips_reqsen(ha, scb); |
| 4213 | break; |
| 4214 | |
| 4215 | case READ_6: |
| 4216 | case WRITE_6: |
| 4217 | case READ_10: |
| 4218 | case WRITE_10: |
| 4219 | case RESERVE: |
| 4220 | case RELEASE: |
| 4221 | break; |
| 4222 | |
| 4223 | case MODE_SENSE: |
| 4224 | if (!ips_online(ha, scb) |
| 4225 | || !ips_msense(ha, scb)) { |
| 4226 | errcode = DID_ERROR; |
| 4227 | } |
| 4228 | break; |
| 4229 | |
| 4230 | case READ_CAPACITY: |
| 4231 | if (ips_online(ha, scb)) |
| 4232 | ips_rdcap(ha, scb); |
| 4233 | else { |
| 4234 | errcode = DID_TIME_OUT; |
| 4235 | } |
| 4236 | break; |
| 4237 | |
| 4238 | case SEND_DIAGNOSTIC: |
| 4239 | case REASSIGN_BLOCKS: |
| 4240 | break; |
| 4241 | |
| 4242 | case FORMAT_UNIT: |
| 4243 | errcode = DID_ERROR; |
| 4244 | break; |
| 4245 | |
| 4246 | case SEEK_10: |
| 4247 | case VERIFY: |
| 4248 | case READ_DEFECT_DATA: |
| 4249 | case READ_BUFFER: |
| 4250 | case WRITE_BUFFER: |
| 4251 | break; |
| 4252 | |
| 4253 | default: |
| 4254 | errcode = DID_ERROR; |
| 4255 | } /* end switch */ |
| 4256 | |
| 4257 | scb->scsi_cmd->result = errcode << 16; |
| 4258 | } else { /* bus == 0 */ |
| 4259 | /* restrict access to physical drives */ |
Jack Hammer | a5b3c86 | 2006-01-31 13:17:55 -0500 | [diff] [blame] | 4260 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
| 4261 | ips_scmd_buf_read(scb->scsi_cmd, |
| 4262 | &inquiryData, sizeof (inquiryData)); |
| 4263 | if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) |
| 4264 | scb->scsi_cmd->result = DID_TIME_OUT << 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4265 | } |
| 4266 | } /* else */ |
| 4267 | } else { /* recovered error / success */ |
| 4268 | if (scb->bus == 0) { |
| 4269 | DEBUG_VAR(1, |
| 4270 | "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", |
| 4271 | ips_name, ha->host_num, |
| 4272 | scb->cmd.basic_io.op_code, basic_status, |
| 4273 | ext_status); |
| 4274 | } |
| 4275 | |
| 4276 | ips_map_status(ha, scb, sp); |
| 4277 | } /* else */ |
| 4278 | } |
| 4279 | |
| 4280 | /****************************************************************************/ |
| 4281 | /* */ |
| 4282 | /* Routine Name: ips_online */ |
| 4283 | /* */ |
| 4284 | /* Routine Description: */ |
| 4285 | /* */ |
| 4286 | /* Determine if a logical drive is online */ |
| 4287 | /* */ |
| 4288 | /****************************************************************************/ |
| 4289 | static int |
| 4290 | ips_online(ips_ha_t * ha, ips_scb_t * scb) |
| 4291 | { |
| 4292 | METHOD_TRACE("ips_online", 1); |
| 4293 | |
| 4294 | if (scb->target_id >= IPS_MAX_LD) |
| 4295 | return (0); |
| 4296 | |
| 4297 | if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { |
| 4298 | memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); |
| 4299 | return (0); |
| 4300 | } |
| 4301 | |
| 4302 | if (ha->logical_drive_info->drive_info[scb->target_id].state != |
| 4303 | IPS_LD_OFFLINE |
| 4304 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
| 4305 | IPS_LD_FREE |
| 4306 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
| 4307 | IPS_LD_CRS |
| 4308 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
| 4309 | IPS_LD_SYS) |
| 4310 | return (1); |
| 4311 | else |
| 4312 | return (0); |
| 4313 | } |
| 4314 | |
| 4315 | /****************************************************************************/ |
| 4316 | /* */ |
| 4317 | /* Routine Name: ips_inquiry */ |
| 4318 | /* */ |
| 4319 | /* Routine Description: */ |
| 4320 | /* */ |
| 4321 | /* Simulate an inquiry command to a logical drive */ |
| 4322 | /* */ |
| 4323 | /****************************************************************************/ |
| 4324 | static int |
| 4325 | ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) |
| 4326 | { |
| 4327 | IPS_SCSI_INQ_DATA inquiry; |
| 4328 | |
| 4329 | METHOD_TRACE("ips_inquiry", 1); |
| 4330 | |
| 4331 | memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); |
| 4332 | |
| 4333 | inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; |
| 4334 | inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; |
| 4335 | inquiry.Version = IPS_SCSI_INQ_REV2; |
| 4336 | inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; |
| 4337 | inquiry.AdditionalLength = 31; |
| 4338 | inquiry.Flags[0] = IPS_SCSI_INQ_Address16; |
| 4339 | inquiry.Flags[1] = |
| 4340 | IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; |
| 4341 | strncpy(inquiry.VendorId, "IBM ", 8); |
| 4342 | strncpy(inquiry.ProductId, "SERVERAID ", 16); |
| 4343 | strncpy(inquiry.ProductRevisionLevel, "1.00", 4); |
| 4344 | |
| 4345 | ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry)); |
| 4346 | |
| 4347 | return (1); |
| 4348 | } |
| 4349 | |
| 4350 | /****************************************************************************/ |
| 4351 | /* */ |
| 4352 | /* Routine Name: ips_rdcap */ |
| 4353 | /* */ |
| 4354 | /* Routine Description: */ |
| 4355 | /* */ |
| 4356 | /* Simulate a read capacity command to a logical drive */ |
| 4357 | /* */ |
| 4358 | /****************************************************************************/ |
| 4359 | static int |
| 4360 | ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) |
| 4361 | { |
| 4362 | IPS_SCSI_CAPACITY cap; |
| 4363 | |
| 4364 | METHOD_TRACE("ips_rdcap", 1); |
| 4365 | |
| 4366 | if (scb->scsi_cmd->bufflen < 8) |
| 4367 | return (0); |
| 4368 | |
| 4369 | cap.lba = |
| 4370 | cpu_to_be32(le32_to_cpu |
| 4371 | (ha->logical_drive_info-> |
| 4372 | drive_info[scb->target_id].sector_count) - 1); |
| 4373 | cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); |
| 4374 | |
| 4375 | ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap)); |
| 4376 | |
| 4377 | return (1); |
| 4378 | } |
| 4379 | |
| 4380 | /****************************************************************************/ |
| 4381 | /* */ |
| 4382 | /* Routine Name: ips_msense */ |
| 4383 | /* */ |
| 4384 | /* Routine Description: */ |
| 4385 | /* */ |
| 4386 | /* Simulate a mode sense command to a logical drive */ |
| 4387 | /* */ |
| 4388 | /****************************************************************************/ |
| 4389 | static int |
| 4390 | ips_msense(ips_ha_t * ha, ips_scb_t * scb) |
| 4391 | { |
| 4392 | uint16_t heads; |
| 4393 | uint16_t sectors; |
| 4394 | uint32_t cylinders; |
| 4395 | IPS_SCSI_MODE_PAGE_DATA mdata; |
| 4396 | |
| 4397 | METHOD_TRACE("ips_msense", 1); |
| 4398 | |
| 4399 | if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && |
| 4400 | (ha->enq->ucMiscFlag & 0x8) == 0) { |
| 4401 | heads = IPS_NORM_HEADS; |
| 4402 | sectors = IPS_NORM_SECTORS; |
| 4403 | } else { |
| 4404 | heads = IPS_COMP_HEADS; |
| 4405 | sectors = IPS_COMP_SECTORS; |
| 4406 | } |
| 4407 | |
| 4408 | cylinders = |
| 4409 | (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - |
| 4410 | 1) / (heads * sectors); |
| 4411 | |
| 4412 | memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); |
| 4413 | |
| 4414 | mdata.hdr.BlockDescLength = 8; |
| 4415 | |
| 4416 | switch (scb->scsi_cmd->cmnd[2] & 0x3f) { |
| 4417 | case 0x03: /* page 3 */ |
| 4418 | mdata.pdata.pg3.PageCode = 3; |
| 4419 | mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); |
| 4420 | mdata.hdr.DataLength = |
| 4421 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; |
| 4422 | mdata.pdata.pg3.TracksPerZone = 0; |
| 4423 | mdata.pdata.pg3.AltSectorsPerZone = 0; |
| 4424 | mdata.pdata.pg3.AltTracksPerZone = 0; |
| 4425 | mdata.pdata.pg3.AltTracksPerVolume = 0; |
| 4426 | mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); |
| 4427 | mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); |
| 4428 | mdata.pdata.pg3.Interleave = cpu_to_be16(1); |
| 4429 | mdata.pdata.pg3.TrackSkew = 0; |
| 4430 | mdata.pdata.pg3.CylinderSkew = 0; |
| 4431 | mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; |
| 4432 | break; |
| 4433 | |
| 4434 | case 0x4: |
| 4435 | mdata.pdata.pg4.PageCode = 4; |
| 4436 | mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); |
| 4437 | mdata.hdr.DataLength = |
| 4438 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; |
| 4439 | mdata.pdata.pg4.CylindersHigh = |
| 4440 | cpu_to_be16((cylinders >> 8) & 0xFFFF); |
| 4441 | mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); |
| 4442 | mdata.pdata.pg4.Heads = heads; |
| 4443 | mdata.pdata.pg4.WritePrecompHigh = 0; |
| 4444 | mdata.pdata.pg4.WritePrecompLow = 0; |
| 4445 | mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; |
| 4446 | mdata.pdata.pg4.ReducedWriteCurrentLow = 0; |
| 4447 | mdata.pdata.pg4.StepRate = cpu_to_be16(1); |
| 4448 | mdata.pdata.pg4.LandingZoneHigh = 0; |
| 4449 | mdata.pdata.pg4.LandingZoneLow = 0; |
| 4450 | mdata.pdata.pg4.flags = 0; |
| 4451 | mdata.pdata.pg4.RotationalOffset = 0; |
| 4452 | mdata.pdata.pg4.MediumRotationRate = 0; |
| 4453 | break; |
| 4454 | case 0x8: |
| 4455 | mdata.pdata.pg8.PageCode = 8; |
| 4456 | mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); |
| 4457 | mdata.hdr.DataLength = |
| 4458 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; |
| 4459 | /* everything else is left set to 0 */ |
| 4460 | break; |
| 4461 | |
| 4462 | default: |
| 4463 | return (0); |
| 4464 | } /* end switch */ |
| 4465 | |
| 4466 | ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata)); |
| 4467 | |
| 4468 | return (1); |
| 4469 | } |
| 4470 | |
| 4471 | /****************************************************************************/ |
| 4472 | /* */ |
| 4473 | /* Routine Name: ips_reqsen */ |
| 4474 | /* */ |
| 4475 | /* Routine Description: */ |
| 4476 | /* */ |
| 4477 | /* Simulate a request sense command to a logical drive */ |
| 4478 | /* */ |
| 4479 | /****************************************************************************/ |
| 4480 | static int |
| 4481 | ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) |
| 4482 | { |
| 4483 | IPS_SCSI_REQSEN reqsen; |
| 4484 | |
| 4485 | METHOD_TRACE("ips_reqsen", 1); |
| 4486 | |
| 4487 | memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); |
| 4488 | |
| 4489 | reqsen.ResponseCode = |
| 4490 | IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; |
| 4491 | reqsen.AdditionalLength = 10; |
| 4492 | reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; |
| 4493 | reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; |
| 4494 | |
| 4495 | ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen)); |
| 4496 | |
| 4497 | return (1); |
| 4498 | } |
| 4499 | |
| 4500 | /****************************************************************************/ |
| 4501 | /* */ |
| 4502 | /* Routine Name: ips_free */ |
| 4503 | /* */ |
| 4504 | /* Routine Description: */ |
| 4505 | /* */ |
| 4506 | /* Free any allocated space for this controller */ |
| 4507 | /* */ |
| 4508 | /****************************************************************************/ |
| 4509 | static void |
| 4510 | ips_free(ips_ha_t * ha) |
| 4511 | { |
| 4512 | |
| 4513 | METHOD_TRACE("ips_free", 1); |
| 4514 | |
| 4515 | if (ha) { |
| 4516 | if (ha->enq) { |
| 4517 | pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ), |
| 4518 | ha->enq, ha->enq_busaddr); |
| 4519 | ha->enq = NULL; |
| 4520 | } |
| 4521 | |
Jesper Juhl | c9475cb | 2005-11-07 01:01:26 -0800 | [diff] [blame] | 4522 | kfree(ha->conf); |
| 4523 | ha->conf = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4524 | |
| 4525 | if (ha->adapt) { |
| 4526 | pci_free_consistent(ha->pcidev, |
| 4527 | sizeof (IPS_ADAPTER) + |
| 4528 | sizeof (IPS_IO_CMD), ha->adapt, |
| 4529 | ha->adapt->hw_status_start); |
| 4530 | ha->adapt = NULL; |
| 4531 | } |
| 4532 | |
| 4533 | if (ha->logical_drive_info) { |
| 4534 | pci_free_consistent(ha->pcidev, |
| 4535 | sizeof (IPS_LD_INFO), |
| 4536 | ha->logical_drive_info, |
| 4537 | ha->logical_drive_info_dma_addr); |
| 4538 | ha->logical_drive_info = NULL; |
| 4539 | } |
| 4540 | |
Jesper Juhl | c9475cb | 2005-11-07 01:01:26 -0800 | [diff] [blame] | 4541 | kfree(ha->nvram); |
| 4542 | ha->nvram = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4543 | |
Jesper Juhl | c9475cb | 2005-11-07 01:01:26 -0800 | [diff] [blame] | 4544 | kfree(ha->subsys); |
| 4545 | ha->subsys = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4546 | |
| 4547 | if (ha->ioctl_data) { |
| 4548 | pci_free_consistent(ha->pcidev, ha->ioctl_len, |
| 4549 | ha->ioctl_data, ha->ioctl_busaddr); |
| 4550 | ha->ioctl_data = NULL; |
| 4551 | ha->ioctl_datasize = 0; |
| 4552 | ha->ioctl_len = 0; |
| 4553 | } |
| 4554 | ips_deallocatescbs(ha, ha->max_cmds); |
| 4555 | |
| 4556 | /* free memory mapped (if applicable) */ |
| 4557 | if (ha->mem_ptr) { |
| 4558 | iounmap(ha->ioremap_ptr); |
| 4559 | ha->ioremap_ptr = NULL; |
| 4560 | ha->mem_ptr = NULL; |
| 4561 | } |
| 4562 | |
| 4563 | if (ha->mem_addr) |
| 4564 | release_mem_region(ha->mem_addr, ha->mem_len); |
| 4565 | ha->mem_addr = 0; |
| 4566 | |
| 4567 | } |
| 4568 | } |
| 4569 | |
| 4570 | /****************************************************************************/ |
| 4571 | /* */ |
| 4572 | /* Routine Name: ips_deallocatescbs */ |
| 4573 | /* */ |
| 4574 | /* Routine Description: */ |
| 4575 | /* */ |
| 4576 | /* Free the command blocks */ |
| 4577 | /* */ |
| 4578 | /****************************************************************************/ |
| 4579 | static int |
| 4580 | ips_deallocatescbs(ips_ha_t * ha, int cmds) |
| 4581 | { |
| 4582 | if (ha->scbs) { |
| 4583 | pci_free_consistent(ha->pcidev, |
| 4584 | IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, |
| 4585 | ha->scbs->sg_list.list, |
| 4586 | ha->scbs->sg_busaddr); |
| 4587 | pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds, |
| 4588 | ha->scbs, ha->scbs->scb_busaddr); |
| 4589 | ha->scbs = NULL; |
| 4590 | } /* end if */ |
| 4591 | return 1; |
| 4592 | } |
| 4593 | |
| 4594 | /****************************************************************************/ |
| 4595 | /* */ |
| 4596 | /* Routine Name: ips_allocatescbs */ |
| 4597 | /* */ |
| 4598 | /* Routine Description: */ |
| 4599 | /* */ |
| 4600 | /* Allocate the command blocks */ |
| 4601 | /* */ |
| 4602 | /****************************************************************************/ |
| 4603 | static int |
| 4604 | ips_allocatescbs(ips_ha_t * ha) |
| 4605 | { |
| 4606 | ips_scb_t *scb_p; |
| 4607 | IPS_SG_LIST ips_sg; |
| 4608 | int i; |
| 4609 | dma_addr_t command_dma, sg_dma; |
| 4610 | |
| 4611 | METHOD_TRACE("ips_allocatescbs", 1); |
| 4612 | |
| 4613 | /* Allocate memory for the SCBs */ |
| 4614 | ha->scbs = |
| 4615 | pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t), |
| 4616 | &command_dma); |
| 4617 | if (ha->scbs == NULL) |
| 4618 | return 0; |
| 4619 | ips_sg.list = |
| 4620 | pci_alloc_consistent(ha->pcidev, |
| 4621 | IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * |
| 4622 | ha->max_cmds, &sg_dma); |
| 4623 | if (ips_sg.list == NULL) { |
| 4624 | pci_free_consistent(ha->pcidev, |
| 4625 | ha->max_cmds * sizeof (ips_scb_t), ha->scbs, |
| 4626 | command_dma); |
| 4627 | return 0; |
| 4628 | } |
| 4629 | |
| 4630 | memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); |
| 4631 | |
| 4632 | for (i = 0; i < ha->max_cmds; i++) { |
| 4633 | scb_p = &ha->scbs[i]; |
| 4634 | scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; |
| 4635 | /* set up S/G list */ |
| 4636 | if (IPS_USE_ENH_SGLIST(ha)) { |
| 4637 | scb_p->sg_list.enh_list = |
| 4638 | ips_sg.enh_list + i * IPS_MAX_SG; |
| 4639 | scb_p->sg_busaddr = |
| 4640 | sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; |
| 4641 | } else { |
| 4642 | scb_p->sg_list.std_list = |
| 4643 | ips_sg.std_list + i * IPS_MAX_SG; |
| 4644 | scb_p->sg_busaddr = |
| 4645 | sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; |
| 4646 | } |
| 4647 | |
| 4648 | /* add to the free list */ |
| 4649 | if (i < ha->max_cmds - 1) { |
| 4650 | scb_p->q_next = ha->scb_freelist; |
| 4651 | ha->scb_freelist = scb_p; |
| 4652 | } |
| 4653 | } |
| 4654 | |
| 4655 | /* success */ |
| 4656 | return (1); |
| 4657 | } |
| 4658 | |
| 4659 | /****************************************************************************/ |
| 4660 | /* */ |
| 4661 | /* Routine Name: ips_init_scb */ |
| 4662 | /* */ |
| 4663 | /* Routine Description: */ |
| 4664 | /* */ |
| 4665 | /* Initialize a CCB to default values */ |
| 4666 | /* */ |
| 4667 | /****************************************************************************/ |
| 4668 | static void |
| 4669 | ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) |
| 4670 | { |
| 4671 | IPS_SG_LIST sg_list; |
| 4672 | uint32_t cmd_busaddr, sg_busaddr; |
| 4673 | METHOD_TRACE("ips_init_scb", 1); |
| 4674 | |
| 4675 | if (scb == NULL) |
| 4676 | return; |
| 4677 | |
| 4678 | sg_list.list = scb->sg_list.list; |
| 4679 | cmd_busaddr = scb->scb_busaddr; |
| 4680 | sg_busaddr = scb->sg_busaddr; |
| 4681 | /* zero fill */ |
| 4682 | memset(scb, 0, sizeof (ips_scb_t)); |
| 4683 | memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); |
| 4684 | |
| 4685 | /* Initialize dummy command bucket */ |
| 4686 | ha->dummy->op_code = 0xFF; |
| 4687 | ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start |
| 4688 | + sizeof (IPS_ADAPTER)); |
| 4689 | ha->dummy->command_id = IPS_MAX_CMDS; |
| 4690 | |
| 4691 | /* set bus address of scb */ |
| 4692 | scb->scb_busaddr = cmd_busaddr; |
| 4693 | scb->sg_busaddr = sg_busaddr; |
| 4694 | scb->sg_list.list = sg_list.list; |
| 4695 | |
| 4696 | /* Neptune Fix */ |
| 4697 | scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); |
| 4698 | scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start |
| 4699 | + sizeof (IPS_ADAPTER)); |
| 4700 | } |
| 4701 | |
| 4702 | /****************************************************************************/ |
| 4703 | /* */ |
| 4704 | /* Routine Name: ips_get_scb */ |
| 4705 | /* */ |
| 4706 | /* Routine Description: */ |
| 4707 | /* */ |
| 4708 | /* Initialize a CCB to default values */ |
| 4709 | /* */ |
| 4710 | /* ASSUMED to be callled from within a lock */ |
| 4711 | /* */ |
| 4712 | /****************************************************************************/ |
| 4713 | static ips_scb_t * |
| 4714 | ips_getscb(ips_ha_t * ha) |
| 4715 | { |
| 4716 | ips_scb_t *scb; |
| 4717 | |
| 4718 | METHOD_TRACE("ips_getscb", 1); |
| 4719 | |
| 4720 | if ((scb = ha->scb_freelist) == NULL) { |
| 4721 | |
| 4722 | return (NULL); |
| 4723 | } |
| 4724 | |
| 4725 | ha->scb_freelist = scb->q_next; |
| 4726 | scb->flags = 0; |
| 4727 | scb->q_next = NULL; |
| 4728 | |
| 4729 | ips_init_scb(ha, scb); |
| 4730 | |
| 4731 | return (scb); |
| 4732 | } |
| 4733 | |
| 4734 | /****************************************************************************/ |
| 4735 | /* */ |
| 4736 | /* Routine Name: ips_free_scb */ |
| 4737 | /* */ |
| 4738 | /* Routine Description: */ |
| 4739 | /* */ |
| 4740 | /* Return an unused CCB back to the free list */ |
| 4741 | /* */ |
| 4742 | /* ASSUMED to be called from within a lock */ |
| 4743 | /* */ |
| 4744 | /****************************************************************************/ |
| 4745 | static void |
| 4746 | ips_freescb(ips_ha_t * ha, ips_scb_t * scb) |
| 4747 | { |
| 4748 | |
| 4749 | METHOD_TRACE("ips_freescb", 1); |
| 4750 | if (scb->flags & IPS_SCB_MAP_SG) |
| 4751 | pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer, |
| 4752 | scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb)); |
| 4753 | else if (scb->flags & IPS_SCB_MAP_SINGLE) |
| 4754 | pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len, |
| 4755 | IPS_DMA_DIR(scb)); |
| 4756 | |
| 4757 | /* check to make sure this is not our "special" scb */ |
| 4758 | if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { |
| 4759 | scb->q_next = ha->scb_freelist; |
| 4760 | ha->scb_freelist = scb; |
| 4761 | } |
| 4762 | } |
| 4763 | |
| 4764 | /****************************************************************************/ |
| 4765 | /* */ |
| 4766 | /* Routine Name: ips_isinit_copperhead */ |
| 4767 | /* */ |
| 4768 | /* Routine Description: */ |
| 4769 | /* */ |
| 4770 | /* Is controller initialized ? */ |
| 4771 | /* */ |
| 4772 | /****************************************************************************/ |
| 4773 | static int |
| 4774 | ips_isinit_copperhead(ips_ha_t * ha) |
| 4775 | { |
| 4776 | uint8_t scpr; |
| 4777 | uint8_t isr; |
| 4778 | |
| 4779 | METHOD_TRACE("ips_isinit_copperhead", 1); |
| 4780 | |
| 4781 | isr = inb(ha->io_addr + IPS_REG_HISR); |
| 4782 | scpr = inb(ha->io_addr + IPS_REG_SCPR); |
| 4783 | |
| 4784 | if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) |
| 4785 | return (0); |
| 4786 | else |
| 4787 | return (1); |
| 4788 | } |
| 4789 | |
| 4790 | /****************************************************************************/ |
| 4791 | /* */ |
| 4792 | /* Routine Name: ips_isinit_copperhead_memio */ |
| 4793 | /* */ |
| 4794 | /* Routine Description: */ |
| 4795 | /* */ |
| 4796 | /* Is controller initialized ? */ |
| 4797 | /* */ |
| 4798 | /****************************************************************************/ |
| 4799 | static int |
| 4800 | ips_isinit_copperhead_memio(ips_ha_t * ha) |
| 4801 | { |
| 4802 | uint8_t isr = 0; |
| 4803 | uint8_t scpr; |
| 4804 | |
| 4805 | METHOD_TRACE("ips_is_init_copperhead_memio", 1); |
| 4806 | |
| 4807 | isr = readb(ha->mem_ptr + IPS_REG_HISR); |
| 4808 | scpr = readb(ha->mem_ptr + IPS_REG_SCPR); |
| 4809 | |
| 4810 | if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) |
| 4811 | return (0); |
| 4812 | else |
| 4813 | return (1); |
| 4814 | } |
| 4815 | |
| 4816 | /****************************************************************************/ |
| 4817 | /* */ |
| 4818 | /* Routine Name: ips_isinit_morpheus */ |
| 4819 | /* */ |
| 4820 | /* Routine Description: */ |
| 4821 | /* */ |
| 4822 | /* Is controller initialized ? */ |
| 4823 | /* */ |
| 4824 | /****************************************************************************/ |
| 4825 | static int |
| 4826 | ips_isinit_morpheus(ips_ha_t * ha) |
| 4827 | { |
| 4828 | uint32_t post; |
| 4829 | uint32_t bits; |
| 4830 | |
| 4831 | METHOD_TRACE("ips_is_init_morpheus", 1); |
Jack Hammer | ee807c2 | 2005-08-29 10:44:34 -0400 | [diff] [blame] | 4832 | |
| 4833 | if (ips_isintr_morpheus(ha)) |
| 4834 | ips_flush_and_reset(ha); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4835 | |
| 4836 | post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); |
| 4837 | bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); |
| 4838 | |
| 4839 | if (post == 0) |
| 4840 | return (0); |
| 4841 | else if (bits & 0x3) |
| 4842 | return (0); |
| 4843 | else |
| 4844 | return (1); |
| 4845 | } |
| 4846 | |
| 4847 | /****************************************************************************/ |
| 4848 | /* */ |
Jack Hammer | ee807c2 | 2005-08-29 10:44:34 -0400 | [diff] [blame] | 4849 | /* Routine Name: ips_flush_and_reset */ |
| 4850 | /* */ |
| 4851 | /* Routine Description: */ |
| 4852 | /* */ |
| 4853 | /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ |
| 4854 | /* state ( was trying to INIT and an interrupt was already pending ) ... */ |
| 4855 | /* */ |
| 4856 | /****************************************************************************/ |
| 4857 | static void |
| 4858 | ips_flush_and_reset(ips_ha_t *ha) |
| 4859 | { |
| 4860 | ips_scb_t *scb; |
| 4861 | int ret; |
| 4862 | int time; |
| 4863 | int done; |
| 4864 | dma_addr_t command_dma; |
| 4865 | |
| 4866 | /* Create a usuable SCB */ |
| 4867 | scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma); |
| 4868 | if (scb) { |
| 4869 | memset(scb, 0, sizeof(ips_scb_t)); |
| 4870 | ips_init_scb(ha, scb); |
| 4871 | scb->scb_busaddr = command_dma; |
| 4872 | |
| 4873 | scb->timeout = ips_cmd_timeout; |
| 4874 | scb->cdb[0] = IPS_CMD_FLUSH; |
| 4875 | |
| 4876 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
| 4877 | scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ |
| 4878 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
| 4879 | scb->cmd.flush_cache.reserved = 0; |
| 4880 | scb->cmd.flush_cache.reserved2 = 0; |
| 4881 | scb->cmd.flush_cache.reserved3 = 0; |
| 4882 | scb->cmd.flush_cache.reserved4 = 0; |
| 4883 | |
| 4884 | ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ |
| 4885 | |
| 4886 | if (ret == IPS_SUCCESS) { |
| 4887 | time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ |
| 4888 | done = 0; |
| 4889 | |
| 4890 | while ((time > 0) && (!done)) { |
| 4891 | done = ips_poll_for_flush_complete(ha); |
| 4892 | /* This may look evil, but it's only done during extremely rare start-up conditions ! */ |
| 4893 | udelay(1000); |
| 4894 | time--; |
| 4895 | } |
| 4896 | } |
| 4897 | } |
| 4898 | |
| 4899 | /* Now RESET and INIT the adapter */ |
| 4900 | (*ha->func.reset) (ha); |
| 4901 | |
| 4902 | pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma); |
| 4903 | return; |
| 4904 | } |
| 4905 | |
| 4906 | /****************************************************************************/ |
| 4907 | /* */ |
| 4908 | /* Routine Name: ips_poll_for_flush_complete */ |
| 4909 | /* */ |
| 4910 | /* Routine Description: */ |
| 4911 | /* */ |
| 4912 | /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ |
| 4913 | /* All other responses are just taken off the queue and ignored */ |
| 4914 | /* */ |
| 4915 | /****************************************************************************/ |
| 4916 | static int |
| 4917 | ips_poll_for_flush_complete(ips_ha_t * ha) |
| 4918 | { |
| 4919 | IPS_STATUS cstatus; |
| 4920 | |
| 4921 | while (TRUE) { |
| 4922 | cstatus.value = (*ha->func.statupd) (ha); |
| 4923 | |
| 4924 | if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ |
| 4925 | break; |
| 4926 | |
| 4927 | /* Success is when we see the Flush Command ID */ |
| 4928 | if (cstatus.fields.command_id == IPS_MAX_CMDS ) |
| 4929 | return 1; |
| 4930 | } |
| 4931 | |
| 4932 | return 0; |
James Bottomley | 0ee957c | 2005-11-04 23:22:55 -0600 | [diff] [blame] | 4933 | } |
Jack Hammer | ee807c2 | 2005-08-29 10:44:34 -0400 | [diff] [blame] | 4934 | |
| 4935 | /****************************************************************************/ |
| 4936 | /* */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4937 | /* Routine Name: ips_enable_int_copperhead */ |
| 4938 | /* */ |
| 4939 | /* Routine Description: */ |
| 4940 | /* Turn on interrupts */ |
| 4941 | /* */ |
| 4942 | /****************************************************************************/ |
| 4943 | static void |
| 4944 | ips_enable_int_copperhead(ips_ha_t * ha) |
| 4945 | { |
| 4946 | METHOD_TRACE("ips_enable_int_copperhead", 1); |
| 4947 | |
| 4948 | outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); |
| 4949 | inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ |
| 4950 | } |
| 4951 | |
| 4952 | /****************************************************************************/ |
| 4953 | /* */ |
| 4954 | /* Routine Name: ips_enable_int_copperhead_memio */ |
| 4955 | /* */ |
| 4956 | /* Routine Description: */ |
| 4957 | /* Turn on interrupts */ |
| 4958 | /* */ |
| 4959 | /****************************************************************************/ |
| 4960 | static void |
| 4961 | ips_enable_int_copperhead_memio(ips_ha_t * ha) |
| 4962 | { |
| 4963 | METHOD_TRACE("ips_enable_int_copperhead_memio", 1); |
| 4964 | |
| 4965 | writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); |
| 4966 | readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ |
| 4967 | } |
| 4968 | |
| 4969 | /****************************************************************************/ |
| 4970 | /* */ |
| 4971 | /* Routine Name: ips_enable_int_morpheus */ |
| 4972 | /* */ |
| 4973 | /* Routine Description: */ |
| 4974 | /* Turn on interrupts */ |
| 4975 | /* */ |
| 4976 | /****************************************************************************/ |
| 4977 | static void |
| 4978 | ips_enable_int_morpheus(ips_ha_t * ha) |
| 4979 | { |
| 4980 | uint32_t Oimr; |
| 4981 | |
| 4982 | METHOD_TRACE("ips_enable_int_morpheus", 1); |
| 4983 | |
| 4984 | Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); |
| 4985 | Oimr &= ~0x08; |
| 4986 | writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); |
| 4987 | readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ |
| 4988 | } |
| 4989 | |
| 4990 | /****************************************************************************/ |
| 4991 | /* */ |
| 4992 | /* Routine Name: ips_init_copperhead */ |
| 4993 | /* */ |
| 4994 | /* Routine Description: */ |
| 4995 | /* */ |
| 4996 | /* Initialize a copperhead controller */ |
| 4997 | /* */ |
| 4998 | /****************************************************************************/ |
| 4999 | static int |
| 5000 | ips_init_copperhead(ips_ha_t * ha) |
| 5001 | { |
| 5002 | uint8_t Isr; |
| 5003 | uint8_t Cbsp; |
| 5004 | uint8_t PostByte[IPS_MAX_POST_BYTES]; |
| 5005 | uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; |
| 5006 | int i, j; |
| 5007 | |
| 5008 | METHOD_TRACE("ips_init_copperhead", 1); |
| 5009 | |
| 5010 | for (i = 0; i < IPS_MAX_POST_BYTES; i++) { |
| 5011 | for (j = 0; j < 45; j++) { |
| 5012 | Isr = inb(ha->io_addr + IPS_REG_HISR); |
| 5013 | if (Isr & IPS_BIT_GHI) |
| 5014 | break; |
| 5015 | |
| 5016 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5017 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5018 | } |
| 5019 | |
| 5020 | if (j >= 45) |
| 5021 | /* error occurred */ |
| 5022 | return (0); |
| 5023 | |
| 5024 | PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR); |
| 5025 | outb(Isr, ha->io_addr + IPS_REG_HISR); |
| 5026 | } |
| 5027 | |
| 5028 | if (PostByte[0] < IPS_GOOD_POST_STATUS) { |
| 5029 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5030 | "reset controller fails (post status %x %x).\n", |
| 5031 | PostByte[0], PostByte[1]); |
| 5032 | |
| 5033 | return (0); |
| 5034 | } |
| 5035 | |
| 5036 | for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { |
| 5037 | for (j = 0; j < 240; j++) { |
| 5038 | Isr = inb(ha->io_addr + IPS_REG_HISR); |
| 5039 | if (Isr & IPS_BIT_GHI) |
| 5040 | break; |
| 5041 | |
| 5042 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5043 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5044 | } |
| 5045 | |
| 5046 | if (j >= 240) |
| 5047 | /* error occurred */ |
| 5048 | return (0); |
| 5049 | |
| 5050 | ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR); |
| 5051 | outb(Isr, ha->io_addr + IPS_REG_HISR); |
| 5052 | } |
| 5053 | |
| 5054 | for (i = 0; i < 240; i++) { |
| 5055 | Cbsp = inb(ha->io_addr + IPS_REG_CBSP); |
| 5056 | |
| 5057 | if ((Cbsp & IPS_BIT_OP) == 0) |
| 5058 | break; |
| 5059 | |
| 5060 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5061 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5062 | } |
| 5063 | |
| 5064 | if (i >= 240) |
| 5065 | /* reset failed */ |
| 5066 | return (0); |
| 5067 | |
| 5068 | /* setup CCCR */ |
| 5069 | outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR); |
| 5070 | |
| 5071 | /* Enable busmastering */ |
| 5072 | outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); |
| 5073 | |
| 5074 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 5075 | /* fix for anaconda64 */ |
| 5076 | outl(0, ha->io_addr + IPS_REG_NDAE); |
| 5077 | |
| 5078 | /* Enable interrupts */ |
| 5079 | outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR); |
| 5080 | |
| 5081 | return (1); |
| 5082 | } |
| 5083 | |
| 5084 | /****************************************************************************/ |
| 5085 | /* */ |
| 5086 | /* Routine Name: ips_init_copperhead_memio */ |
| 5087 | /* */ |
| 5088 | /* Routine Description: */ |
| 5089 | /* */ |
| 5090 | /* Initialize a copperhead controller with memory mapped I/O */ |
| 5091 | /* */ |
| 5092 | /****************************************************************************/ |
| 5093 | static int |
| 5094 | ips_init_copperhead_memio(ips_ha_t * ha) |
| 5095 | { |
| 5096 | uint8_t Isr = 0; |
| 5097 | uint8_t Cbsp; |
| 5098 | uint8_t PostByte[IPS_MAX_POST_BYTES]; |
| 5099 | uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; |
| 5100 | int i, j; |
| 5101 | |
| 5102 | METHOD_TRACE("ips_init_copperhead_memio", 1); |
| 5103 | |
| 5104 | for (i = 0; i < IPS_MAX_POST_BYTES; i++) { |
| 5105 | for (j = 0; j < 45; j++) { |
| 5106 | Isr = readb(ha->mem_ptr + IPS_REG_HISR); |
| 5107 | if (Isr & IPS_BIT_GHI) |
| 5108 | break; |
| 5109 | |
| 5110 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5111 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5112 | } |
| 5113 | |
| 5114 | if (j >= 45) |
| 5115 | /* error occurred */ |
| 5116 | return (0); |
| 5117 | |
| 5118 | PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); |
| 5119 | writeb(Isr, ha->mem_ptr + IPS_REG_HISR); |
| 5120 | } |
| 5121 | |
| 5122 | if (PostByte[0] < IPS_GOOD_POST_STATUS) { |
| 5123 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5124 | "reset controller fails (post status %x %x).\n", |
| 5125 | PostByte[0], PostByte[1]); |
| 5126 | |
| 5127 | return (0); |
| 5128 | } |
| 5129 | |
| 5130 | for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { |
| 5131 | for (j = 0; j < 240; j++) { |
| 5132 | Isr = readb(ha->mem_ptr + IPS_REG_HISR); |
| 5133 | if (Isr & IPS_BIT_GHI) |
| 5134 | break; |
| 5135 | |
| 5136 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5137 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5138 | } |
| 5139 | |
| 5140 | if (j >= 240) |
| 5141 | /* error occurred */ |
| 5142 | return (0); |
| 5143 | |
| 5144 | ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); |
| 5145 | writeb(Isr, ha->mem_ptr + IPS_REG_HISR); |
| 5146 | } |
| 5147 | |
| 5148 | for (i = 0; i < 240; i++) { |
| 5149 | Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); |
| 5150 | |
| 5151 | if ((Cbsp & IPS_BIT_OP) == 0) |
| 5152 | break; |
| 5153 | |
| 5154 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5155 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5156 | } |
| 5157 | |
| 5158 | if (i >= 240) |
| 5159 | /* error occurred */ |
| 5160 | return (0); |
| 5161 | |
| 5162 | /* setup CCCR */ |
| 5163 | writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); |
| 5164 | |
| 5165 | /* Enable busmastering */ |
| 5166 | writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); |
| 5167 | |
| 5168 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 5169 | /* fix for anaconda64 */ |
| 5170 | writel(0, ha->mem_ptr + IPS_REG_NDAE); |
| 5171 | |
| 5172 | /* Enable interrupts */ |
| 5173 | writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); |
| 5174 | |
| 5175 | /* if we get here then everything went OK */ |
| 5176 | return (1); |
| 5177 | } |
| 5178 | |
| 5179 | /****************************************************************************/ |
| 5180 | /* */ |
| 5181 | /* Routine Name: ips_init_morpheus */ |
| 5182 | /* */ |
| 5183 | /* Routine Description: */ |
| 5184 | /* */ |
| 5185 | /* Initialize a morpheus controller */ |
| 5186 | /* */ |
| 5187 | /****************************************************************************/ |
| 5188 | static int |
| 5189 | ips_init_morpheus(ips_ha_t * ha) |
| 5190 | { |
| 5191 | uint32_t Post; |
| 5192 | uint32_t Config; |
| 5193 | uint32_t Isr; |
| 5194 | uint32_t Oimr; |
| 5195 | int i; |
| 5196 | |
| 5197 | METHOD_TRACE("ips_init_morpheus", 1); |
| 5198 | |
| 5199 | /* Wait up to 45 secs for Post */ |
| 5200 | for (i = 0; i < 45; i++) { |
| 5201 | Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5202 | |
| 5203 | if (Isr & IPS_BIT_I960_MSG0I) |
| 5204 | break; |
| 5205 | |
| 5206 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5207 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5208 | } |
| 5209 | |
| 5210 | if (i >= 45) { |
| 5211 | /* error occurred */ |
| 5212 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5213 | "timeout waiting for post.\n"); |
| 5214 | |
| 5215 | return (0); |
| 5216 | } |
| 5217 | |
| 5218 | Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); |
| 5219 | |
| 5220 | if (Post == 0x4F00) { /* If Flashing the Battery PIC */ |
| 5221 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5222 | "Flashing Battery PIC, Please wait ...\n"); |
| 5223 | |
| 5224 | /* Clear the interrupt bit */ |
| 5225 | Isr = (uint32_t) IPS_BIT_I960_MSG0I; |
| 5226 | writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5227 | |
| 5228 | for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ |
| 5229 | Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); |
| 5230 | if (Post != 0x4F00) |
| 5231 | break; |
| 5232 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5233 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5234 | } |
| 5235 | |
| 5236 | if (i >= 120) { |
| 5237 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5238 | "timeout waiting for Battery PIC Flash\n"); |
| 5239 | return (0); |
| 5240 | } |
| 5241 | |
| 5242 | } |
| 5243 | |
| 5244 | /* Clear the interrupt bit */ |
| 5245 | Isr = (uint32_t) IPS_BIT_I960_MSG0I; |
| 5246 | writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5247 | |
| 5248 | if (Post < (IPS_GOOD_POST_STATUS << 8)) { |
| 5249 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5250 | "reset controller fails (post status %x).\n", Post); |
| 5251 | |
| 5252 | return (0); |
| 5253 | } |
| 5254 | |
| 5255 | /* Wait up to 240 secs for config bytes */ |
| 5256 | for (i = 0; i < 240; i++) { |
| 5257 | Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5258 | |
| 5259 | if (Isr & IPS_BIT_I960_MSG1I) |
| 5260 | break; |
| 5261 | |
| 5262 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5263 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5264 | } |
| 5265 | |
| 5266 | if (i >= 240) { |
| 5267 | /* error occurred */ |
| 5268 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5269 | "timeout waiting for config.\n"); |
| 5270 | |
| 5271 | return (0); |
| 5272 | } |
| 5273 | |
| 5274 | Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); |
| 5275 | |
| 5276 | /* Clear interrupt bit */ |
| 5277 | Isr = (uint32_t) IPS_BIT_I960_MSG1I; |
| 5278 | writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5279 | |
| 5280 | /* Turn on the interrupts */ |
| 5281 | Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); |
| 5282 | Oimr &= ~0x8; |
| 5283 | writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); |
| 5284 | |
| 5285 | /* if we get here then everything went OK */ |
| 5286 | |
| 5287 | /* Since we did a RESET, an EraseStripeLock may be needed */ |
| 5288 | if (Post == 0xEF10) { |
| 5289 | if ((Config == 0x000F) || (Config == 0x0009)) |
| 5290 | ha->requires_esl = 1; |
| 5291 | } |
| 5292 | |
| 5293 | return (1); |
| 5294 | } |
| 5295 | |
| 5296 | /****************************************************************************/ |
| 5297 | /* */ |
| 5298 | /* Routine Name: ips_reset_copperhead */ |
| 5299 | /* */ |
| 5300 | /* Routine Description: */ |
| 5301 | /* */ |
| 5302 | /* Reset the controller */ |
| 5303 | /* */ |
| 5304 | /****************************************************************************/ |
| 5305 | static int |
| 5306 | ips_reset_copperhead(ips_ha_t * ha) |
| 5307 | { |
| 5308 | int reset_counter; |
| 5309 | |
| 5310 | METHOD_TRACE("ips_reset_copperhead", 1); |
| 5311 | |
| 5312 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", |
| 5313 | ips_name, ha->host_num, ha->io_addr, ha->irq); |
| 5314 | |
| 5315 | reset_counter = 0; |
| 5316 | |
| 5317 | while (reset_counter < 2) { |
| 5318 | reset_counter++; |
| 5319 | |
| 5320 | outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR); |
| 5321 | |
| 5322 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5323 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5324 | |
| 5325 | outb(0, ha->io_addr + IPS_REG_SCPR); |
| 5326 | |
| 5327 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5328 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5329 | |
| 5330 | if ((*ha->func.init) (ha)) |
| 5331 | break; |
| 5332 | else if (reset_counter >= 2) { |
| 5333 | |
| 5334 | return (0); |
| 5335 | } |
| 5336 | } |
| 5337 | |
| 5338 | return (1); |
| 5339 | } |
| 5340 | |
| 5341 | /****************************************************************************/ |
| 5342 | /* */ |
| 5343 | /* Routine Name: ips_reset_copperhead_memio */ |
| 5344 | /* */ |
| 5345 | /* Routine Description: */ |
| 5346 | /* */ |
| 5347 | /* Reset the controller */ |
| 5348 | /* */ |
| 5349 | /****************************************************************************/ |
| 5350 | static int |
| 5351 | ips_reset_copperhead_memio(ips_ha_t * ha) |
| 5352 | { |
| 5353 | int reset_counter; |
| 5354 | |
| 5355 | METHOD_TRACE("ips_reset_copperhead_memio", 1); |
| 5356 | |
| 5357 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", |
| 5358 | ips_name, ha->host_num, ha->mem_addr, ha->irq); |
| 5359 | |
| 5360 | reset_counter = 0; |
| 5361 | |
| 5362 | while (reset_counter < 2) { |
| 5363 | reset_counter++; |
| 5364 | |
| 5365 | writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); |
| 5366 | |
| 5367 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5368 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5369 | |
| 5370 | writeb(0, ha->mem_ptr + IPS_REG_SCPR); |
| 5371 | |
| 5372 | /* Delay for 1 Second */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5373 | msleep(IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5374 | |
| 5375 | if ((*ha->func.init) (ha)) |
| 5376 | break; |
| 5377 | else if (reset_counter >= 2) { |
| 5378 | |
| 5379 | return (0); |
| 5380 | } |
| 5381 | } |
| 5382 | |
| 5383 | return (1); |
| 5384 | } |
| 5385 | |
| 5386 | /****************************************************************************/ |
| 5387 | /* */ |
| 5388 | /* Routine Name: ips_reset_morpheus */ |
| 5389 | /* */ |
| 5390 | /* Routine Description: */ |
| 5391 | /* */ |
| 5392 | /* Reset the controller */ |
| 5393 | /* */ |
| 5394 | /****************************************************************************/ |
| 5395 | static int |
| 5396 | ips_reset_morpheus(ips_ha_t * ha) |
| 5397 | { |
| 5398 | int reset_counter; |
| 5399 | uint8_t junk; |
| 5400 | |
| 5401 | METHOD_TRACE("ips_reset_morpheus", 1); |
| 5402 | |
| 5403 | DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", |
| 5404 | ips_name, ha->host_num, ha->mem_addr, ha->irq); |
| 5405 | |
| 5406 | reset_counter = 0; |
| 5407 | |
| 5408 | while (reset_counter < 2) { |
| 5409 | reset_counter++; |
| 5410 | |
| 5411 | writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); |
| 5412 | |
| 5413 | /* Delay for 5 Seconds */ |
Jack Hammer | 15084a4 | 2006-01-24 14:43:41 -0500 | [diff] [blame] | 5414 | msleep(5 * IPS_ONE_SEC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5415 | |
| 5416 | /* Do a PCI config read to wait for adapter */ |
| 5417 | pci_read_config_byte(ha->pcidev, 4, &junk); |
| 5418 | |
| 5419 | if ((*ha->func.init) (ha)) |
| 5420 | break; |
| 5421 | else if (reset_counter >= 2) { |
| 5422 | |
| 5423 | return (0); |
| 5424 | } |
| 5425 | } |
| 5426 | |
| 5427 | return (1); |
| 5428 | } |
| 5429 | |
| 5430 | /****************************************************************************/ |
| 5431 | /* */ |
| 5432 | /* Routine Name: ips_statinit */ |
| 5433 | /* */ |
| 5434 | /* Routine Description: */ |
| 5435 | /* */ |
| 5436 | /* Initialize the status queues on the controller */ |
| 5437 | /* */ |
| 5438 | /****************************************************************************/ |
| 5439 | static void |
| 5440 | ips_statinit(ips_ha_t * ha) |
| 5441 | { |
| 5442 | uint32_t phys_status_start; |
| 5443 | |
| 5444 | METHOD_TRACE("ips_statinit", 1); |
| 5445 | |
| 5446 | ha->adapt->p_status_start = ha->adapt->status; |
| 5447 | ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; |
| 5448 | ha->adapt->p_status_tail = ha->adapt->status; |
| 5449 | |
| 5450 | phys_status_start = ha->adapt->hw_status_start; |
| 5451 | outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR); |
| 5452 | outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE), |
| 5453 | ha->io_addr + IPS_REG_SQER); |
| 5454 | outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE), |
| 5455 | ha->io_addr + IPS_REG_SQHR); |
| 5456 | outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR); |
| 5457 | |
| 5458 | ha->adapt->hw_status_tail = phys_status_start; |
| 5459 | } |
| 5460 | |
| 5461 | /****************************************************************************/ |
| 5462 | /* */ |
| 5463 | /* Routine Name: ips_statinit_memio */ |
| 5464 | /* */ |
| 5465 | /* Routine Description: */ |
| 5466 | /* */ |
| 5467 | /* Initialize the status queues on the controller */ |
| 5468 | /* */ |
| 5469 | /****************************************************************************/ |
| 5470 | static void |
| 5471 | ips_statinit_memio(ips_ha_t * ha) |
| 5472 | { |
| 5473 | uint32_t phys_status_start; |
| 5474 | |
| 5475 | METHOD_TRACE("ips_statinit_memio", 1); |
| 5476 | |
| 5477 | ha->adapt->p_status_start = ha->adapt->status; |
| 5478 | ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; |
| 5479 | ha->adapt->p_status_tail = ha->adapt->status; |
| 5480 | |
| 5481 | phys_status_start = ha->adapt->hw_status_start; |
| 5482 | writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); |
| 5483 | writel(phys_status_start + IPS_STATUS_Q_SIZE, |
| 5484 | ha->mem_ptr + IPS_REG_SQER); |
| 5485 | writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); |
| 5486 | writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); |
| 5487 | |
| 5488 | ha->adapt->hw_status_tail = phys_status_start; |
| 5489 | } |
| 5490 | |
| 5491 | /****************************************************************************/ |
| 5492 | /* */ |
| 5493 | /* Routine Name: ips_statupd_copperhead */ |
| 5494 | /* */ |
| 5495 | /* Routine Description: */ |
| 5496 | /* */ |
| 5497 | /* Remove an element from the status queue */ |
| 5498 | /* */ |
| 5499 | /****************************************************************************/ |
| 5500 | static uint32_t |
| 5501 | ips_statupd_copperhead(ips_ha_t * ha) |
| 5502 | { |
| 5503 | METHOD_TRACE("ips_statupd_copperhead", 1); |
| 5504 | |
| 5505 | if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { |
| 5506 | ha->adapt->p_status_tail++; |
| 5507 | ha->adapt->hw_status_tail += sizeof (IPS_STATUS); |
| 5508 | } else { |
| 5509 | ha->adapt->p_status_tail = ha->adapt->p_status_start; |
| 5510 | ha->adapt->hw_status_tail = ha->adapt->hw_status_start; |
| 5511 | } |
| 5512 | |
| 5513 | outl(cpu_to_le32(ha->adapt->hw_status_tail), |
| 5514 | ha->io_addr + IPS_REG_SQTR); |
| 5515 | |
| 5516 | return (ha->adapt->p_status_tail->value); |
| 5517 | } |
| 5518 | |
| 5519 | /****************************************************************************/ |
| 5520 | /* */ |
| 5521 | /* Routine Name: ips_statupd_copperhead_memio */ |
| 5522 | /* */ |
| 5523 | /* Routine Description: */ |
| 5524 | /* */ |
| 5525 | /* Remove an element from the status queue */ |
| 5526 | /* */ |
| 5527 | /****************************************************************************/ |
| 5528 | static uint32_t |
| 5529 | ips_statupd_copperhead_memio(ips_ha_t * ha) |
| 5530 | { |
| 5531 | METHOD_TRACE("ips_statupd_copperhead_memio", 1); |
| 5532 | |
| 5533 | if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { |
| 5534 | ha->adapt->p_status_tail++; |
| 5535 | ha->adapt->hw_status_tail += sizeof (IPS_STATUS); |
| 5536 | } else { |
| 5537 | ha->adapt->p_status_tail = ha->adapt->p_status_start; |
| 5538 | ha->adapt->hw_status_tail = ha->adapt->hw_status_start; |
| 5539 | } |
| 5540 | |
| 5541 | writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); |
| 5542 | |
| 5543 | return (ha->adapt->p_status_tail->value); |
| 5544 | } |
| 5545 | |
| 5546 | /****************************************************************************/ |
| 5547 | /* */ |
| 5548 | /* Routine Name: ips_statupd_morpheus */ |
| 5549 | /* */ |
| 5550 | /* Routine Description: */ |
| 5551 | /* */ |
| 5552 | /* Remove an element from the status queue */ |
| 5553 | /* */ |
| 5554 | /****************************************************************************/ |
| 5555 | static uint32_t |
| 5556 | ips_statupd_morpheus(ips_ha_t * ha) |
| 5557 | { |
| 5558 | uint32_t val; |
| 5559 | |
| 5560 | METHOD_TRACE("ips_statupd_morpheus", 1); |
| 5561 | |
| 5562 | val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); |
| 5563 | |
| 5564 | return (val); |
| 5565 | } |
| 5566 | |
| 5567 | /****************************************************************************/ |
| 5568 | /* */ |
| 5569 | /* Routine Name: ips_issue_copperhead */ |
| 5570 | /* */ |
| 5571 | /* Routine Description: */ |
| 5572 | /* */ |
| 5573 | /* Send a command down to the controller */ |
| 5574 | /* */ |
| 5575 | /****************************************************************************/ |
| 5576 | static int |
| 5577 | ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) |
| 5578 | { |
| 5579 | uint32_t TimeOut; |
| 5580 | uint32_t val; |
| 5581 | |
| 5582 | METHOD_TRACE("ips_issue_copperhead", 1); |
| 5583 | |
| 5584 | if (scb->scsi_cmd) { |
| 5585 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", |
| 5586 | ips_name, |
| 5587 | ha->host_num, |
| 5588 | scb->cdb[0], |
| 5589 | scb->cmd.basic_io.command_id, |
| 5590 | scb->bus, scb->target_id, scb->lun); |
| 5591 | } else { |
| 5592 | DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d", |
| 5593 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
| 5594 | } |
| 5595 | |
| 5596 | TimeOut = 0; |
| 5597 | |
| 5598 | while ((val = |
| 5599 | le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { |
| 5600 | udelay(1000); |
| 5601 | |
| 5602 | if (++TimeOut >= IPS_SEM_TIMEOUT) { |
| 5603 | if (!(val & IPS_BIT_START_STOP)) |
| 5604 | break; |
| 5605 | |
| 5606 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5607 | "ips_issue val [0x%x].\n", val); |
| 5608 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5609 | "ips_issue semaphore chk timeout.\n"); |
| 5610 | |
| 5611 | return (IPS_FAILURE); |
| 5612 | } /* end if */ |
| 5613 | } /* end while */ |
| 5614 | |
| 5615 | outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR); |
| 5616 | outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR); |
| 5617 | |
| 5618 | return (IPS_SUCCESS); |
| 5619 | } |
| 5620 | |
| 5621 | /****************************************************************************/ |
| 5622 | /* */ |
| 5623 | /* Routine Name: ips_issue_copperhead_memio */ |
| 5624 | /* */ |
| 5625 | /* Routine Description: */ |
| 5626 | /* */ |
| 5627 | /* Send a command down to the controller */ |
| 5628 | /* */ |
| 5629 | /****************************************************************************/ |
| 5630 | static int |
| 5631 | ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) |
| 5632 | { |
| 5633 | uint32_t TimeOut; |
| 5634 | uint32_t val; |
| 5635 | |
| 5636 | METHOD_TRACE("ips_issue_copperhead_memio", 1); |
| 5637 | |
| 5638 | if (scb->scsi_cmd) { |
| 5639 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", |
| 5640 | ips_name, |
| 5641 | ha->host_num, |
| 5642 | scb->cdb[0], |
| 5643 | scb->cmd.basic_io.command_id, |
| 5644 | scb->bus, scb->target_id, scb->lun); |
| 5645 | } else { |
| 5646 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", |
| 5647 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
| 5648 | } |
| 5649 | |
| 5650 | TimeOut = 0; |
| 5651 | |
| 5652 | while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { |
| 5653 | udelay(1000); |
| 5654 | |
| 5655 | if (++TimeOut >= IPS_SEM_TIMEOUT) { |
| 5656 | if (!(val & IPS_BIT_START_STOP)) |
| 5657 | break; |
| 5658 | |
| 5659 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5660 | "ips_issue val [0x%x].\n", val); |
| 5661 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5662 | "ips_issue semaphore chk timeout.\n"); |
| 5663 | |
| 5664 | return (IPS_FAILURE); |
| 5665 | } /* end if */ |
| 5666 | } /* end while */ |
| 5667 | |
| 5668 | writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); |
| 5669 | writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); |
| 5670 | |
| 5671 | return (IPS_SUCCESS); |
| 5672 | } |
| 5673 | |
| 5674 | /****************************************************************************/ |
| 5675 | /* */ |
| 5676 | /* Routine Name: ips_issue_i2o */ |
| 5677 | /* */ |
| 5678 | /* Routine Description: */ |
| 5679 | /* */ |
| 5680 | /* Send a command down to the controller */ |
| 5681 | /* */ |
| 5682 | /****************************************************************************/ |
| 5683 | static int |
| 5684 | ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) |
| 5685 | { |
| 5686 | |
| 5687 | METHOD_TRACE("ips_issue_i2o", 1); |
| 5688 | |
| 5689 | if (scb->scsi_cmd) { |
| 5690 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", |
| 5691 | ips_name, |
| 5692 | ha->host_num, |
| 5693 | scb->cdb[0], |
| 5694 | scb->cmd.basic_io.command_id, |
| 5695 | scb->bus, scb->target_id, scb->lun); |
| 5696 | } else { |
| 5697 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", |
| 5698 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
| 5699 | } |
| 5700 | |
| 5701 | outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ); |
| 5702 | |
| 5703 | return (IPS_SUCCESS); |
| 5704 | } |
| 5705 | |
| 5706 | /****************************************************************************/ |
| 5707 | /* */ |
| 5708 | /* Routine Name: ips_issue_i2o_memio */ |
| 5709 | /* */ |
| 5710 | /* Routine Description: */ |
| 5711 | /* */ |
| 5712 | /* Send a command down to the controller */ |
| 5713 | /* */ |
| 5714 | /****************************************************************************/ |
| 5715 | static int |
| 5716 | ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) |
| 5717 | { |
| 5718 | |
| 5719 | METHOD_TRACE("ips_issue_i2o_memio", 1); |
| 5720 | |
| 5721 | if (scb->scsi_cmd) { |
| 5722 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", |
| 5723 | ips_name, |
| 5724 | ha->host_num, |
| 5725 | scb->cdb[0], |
| 5726 | scb->cmd.basic_io.command_id, |
| 5727 | scb->bus, scb->target_id, scb->lun); |
| 5728 | } else { |
| 5729 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", |
| 5730 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
| 5731 | } |
| 5732 | |
| 5733 | writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); |
| 5734 | |
| 5735 | return (IPS_SUCCESS); |
| 5736 | } |
| 5737 | |
| 5738 | /****************************************************************************/ |
| 5739 | /* */ |
| 5740 | /* Routine Name: ips_isintr_copperhead */ |
| 5741 | /* */ |
| 5742 | /* Routine Description: */ |
| 5743 | /* */ |
| 5744 | /* Test to see if an interrupt is for us */ |
| 5745 | /* */ |
| 5746 | /****************************************************************************/ |
| 5747 | static int |
| 5748 | ips_isintr_copperhead(ips_ha_t * ha) |
| 5749 | { |
| 5750 | uint8_t Isr; |
| 5751 | |
| 5752 | METHOD_TRACE("ips_isintr_copperhead", 2); |
| 5753 | |
| 5754 | Isr = inb(ha->io_addr + IPS_REG_HISR); |
| 5755 | |
| 5756 | if (Isr == 0xFF) |
| 5757 | /* ?!?! Nothing really there */ |
| 5758 | return (0); |
| 5759 | |
| 5760 | if (Isr & IPS_BIT_SCE) |
| 5761 | return (1); |
| 5762 | else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { |
| 5763 | /* status queue overflow or GHI */ |
| 5764 | /* just clear the interrupt */ |
| 5765 | outb(Isr, ha->io_addr + IPS_REG_HISR); |
| 5766 | } |
| 5767 | |
| 5768 | return (0); |
| 5769 | } |
| 5770 | |
| 5771 | /****************************************************************************/ |
| 5772 | /* */ |
| 5773 | /* Routine Name: ips_isintr_copperhead_memio */ |
| 5774 | /* */ |
| 5775 | /* Routine Description: */ |
| 5776 | /* */ |
| 5777 | /* Test to see if an interrupt is for us */ |
| 5778 | /* */ |
| 5779 | /****************************************************************************/ |
| 5780 | static int |
| 5781 | ips_isintr_copperhead_memio(ips_ha_t * ha) |
| 5782 | { |
| 5783 | uint8_t Isr; |
| 5784 | |
| 5785 | METHOD_TRACE("ips_isintr_memio", 2); |
| 5786 | |
| 5787 | Isr = readb(ha->mem_ptr + IPS_REG_HISR); |
| 5788 | |
| 5789 | if (Isr == 0xFF) |
| 5790 | /* ?!?! Nothing really there */ |
| 5791 | return (0); |
| 5792 | |
| 5793 | if (Isr & IPS_BIT_SCE) |
| 5794 | return (1); |
| 5795 | else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { |
| 5796 | /* status queue overflow or GHI */ |
| 5797 | /* just clear the interrupt */ |
| 5798 | writeb(Isr, ha->mem_ptr + IPS_REG_HISR); |
| 5799 | } |
| 5800 | |
| 5801 | return (0); |
| 5802 | } |
| 5803 | |
| 5804 | /****************************************************************************/ |
| 5805 | /* */ |
| 5806 | /* Routine Name: ips_isintr_morpheus */ |
| 5807 | /* */ |
| 5808 | /* Routine Description: */ |
| 5809 | /* */ |
| 5810 | /* Test to see if an interrupt is for us */ |
| 5811 | /* */ |
| 5812 | /****************************************************************************/ |
| 5813 | static int |
| 5814 | ips_isintr_morpheus(ips_ha_t * ha) |
| 5815 | { |
| 5816 | uint32_t Isr; |
| 5817 | |
| 5818 | METHOD_TRACE("ips_isintr_morpheus", 2); |
| 5819 | |
| 5820 | Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); |
| 5821 | |
| 5822 | if (Isr & IPS_BIT_I2O_OPQI) |
| 5823 | return (1); |
| 5824 | else |
| 5825 | return (0); |
| 5826 | } |
| 5827 | |
| 5828 | /****************************************************************************/ |
| 5829 | /* */ |
| 5830 | /* Routine Name: ips_wait */ |
| 5831 | /* */ |
| 5832 | /* Routine Description: */ |
| 5833 | /* */ |
| 5834 | /* Wait for a command to complete */ |
| 5835 | /* */ |
| 5836 | /****************************************************************************/ |
| 5837 | static int |
| 5838 | ips_wait(ips_ha_t * ha, int time, int intr) |
| 5839 | { |
| 5840 | int ret; |
| 5841 | int done; |
| 5842 | |
| 5843 | METHOD_TRACE("ips_wait", 1); |
| 5844 | |
| 5845 | ret = IPS_FAILURE; |
| 5846 | done = FALSE; |
| 5847 | |
| 5848 | time *= IPS_ONE_SEC; /* convert seconds */ |
| 5849 | |
| 5850 | while ((time > 0) && (!done)) { |
| 5851 | if (intr == IPS_INTR_ON) { |
| 5852 | if (ha->waitflag == FALSE) { |
| 5853 | ret = IPS_SUCCESS; |
| 5854 | done = TRUE; |
| 5855 | break; |
| 5856 | } |
| 5857 | } else if (intr == IPS_INTR_IORL) { |
| 5858 | if (ha->waitflag == FALSE) { |
| 5859 | /* |
| 5860 | * controller generated an interrupt to |
| 5861 | * acknowledge completion of the command |
| 5862 | * and ips_intr() has serviced the interrupt. |
| 5863 | */ |
| 5864 | ret = IPS_SUCCESS; |
| 5865 | done = TRUE; |
| 5866 | break; |
| 5867 | } |
| 5868 | |
| 5869 | /* |
| 5870 | * NOTE: we already have the io_request_lock so |
| 5871 | * even if we get an interrupt it won't get serviced |
| 5872 | * until after we finish. |
| 5873 | */ |
| 5874 | |
| 5875 | (*ha->func.intr) (ha); |
| 5876 | } |
| 5877 | |
| 5878 | /* This looks like a very evil loop, but it only does this during start-up */ |
| 5879 | udelay(1000); |
| 5880 | time--; |
| 5881 | } |
| 5882 | |
| 5883 | return (ret); |
| 5884 | } |
| 5885 | |
| 5886 | /****************************************************************************/ |
| 5887 | /* */ |
| 5888 | /* Routine Name: ips_write_driver_status */ |
| 5889 | /* */ |
| 5890 | /* Routine Description: */ |
| 5891 | /* */ |
| 5892 | /* Write OS/Driver version to Page 5 of the nvram on the controller */ |
| 5893 | /* */ |
| 5894 | /****************************************************************************/ |
| 5895 | static int |
| 5896 | ips_write_driver_status(ips_ha_t * ha, int intr) |
| 5897 | { |
| 5898 | METHOD_TRACE("ips_write_driver_status", 1); |
| 5899 | |
| 5900 | if (!ips_readwrite_page5(ha, FALSE, intr)) { |
| 5901 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5902 | "unable to read NVRAM page 5.\n"); |
| 5903 | |
| 5904 | return (0); |
| 5905 | } |
| 5906 | |
| 5907 | /* check to make sure the page has a valid */ |
| 5908 | /* signature */ |
| 5909 | if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { |
| 5910 | DEBUG_VAR(1, |
| 5911 | "(%s%d) NVRAM page 5 has an invalid signature: %X.", |
| 5912 | ips_name, ha->host_num, ha->nvram->signature); |
| 5913 | ha->nvram->signature = IPS_NVRAM_P5_SIG; |
| 5914 | } |
| 5915 | |
| 5916 | DEBUG_VAR(2, |
| 5917 | "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.", |
| 5918 | ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), |
| 5919 | ha->nvram->adapter_slot, ha->nvram->bios_high[0], |
| 5920 | ha->nvram->bios_high[1], ha->nvram->bios_high[2], |
| 5921 | ha->nvram->bios_high[3], ha->nvram->bios_low[0], |
| 5922 | ha->nvram->bios_low[1], ha->nvram->bios_low[2], |
| 5923 | ha->nvram->bios_low[3]); |
| 5924 | |
| 5925 | ips_get_bios_version(ha, intr); |
| 5926 | |
| 5927 | /* change values (as needed) */ |
| 5928 | ha->nvram->operating_system = IPS_OS_LINUX; |
| 5929 | ha->nvram->adapter_type = ha->ad_type; |
| 5930 | strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); |
| 5931 | strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); |
| 5932 | strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4); |
| 5933 | strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); |
| 5934 | |
Jack Hammer | a60768e | 2005-11-03 09:46:00 -0500 | [diff] [blame] | 5935 | ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5936 | |
| 5937 | /* now update the page */ |
| 5938 | if (!ips_readwrite_page5(ha, TRUE, intr)) { |
| 5939 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 5940 | "unable to write NVRAM page 5.\n"); |
| 5941 | |
| 5942 | return (0); |
| 5943 | } |
| 5944 | |
| 5945 | /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ |
| 5946 | ha->slot_num = ha->nvram->adapter_slot; |
| 5947 | |
| 5948 | return (1); |
| 5949 | } |
| 5950 | |
| 5951 | /****************************************************************************/ |
| 5952 | /* */ |
| 5953 | /* Routine Name: ips_read_adapter_status */ |
| 5954 | /* */ |
| 5955 | /* Routine Description: */ |
| 5956 | /* */ |
| 5957 | /* Do an Inquiry command to the adapter */ |
| 5958 | /* */ |
| 5959 | /****************************************************************************/ |
| 5960 | static int |
| 5961 | ips_read_adapter_status(ips_ha_t * ha, int intr) |
| 5962 | { |
| 5963 | ips_scb_t *scb; |
| 5964 | int ret; |
| 5965 | |
| 5966 | METHOD_TRACE("ips_read_adapter_status", 1); |
| 5967 | |
| 5968 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 5969 | |
| 5970 | ips_init_scb(ha, scb); |
| 5971 | |
| 5972 | scb->timeout = ips_cmd_timeout; |
| 5973 | scb->cdb[0] = IPS_CMD_ENQUIRY; |
| 5974 | |
| 5975 | scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; |
| 5976 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 5977 | scb->cmd.basic_io.sg_count = 0; |
| 5978 | scb->cmd.basic_io.lba = 0; |
| 5979 | scb->cmd.basic_io.sector_count = 0; |
| 5980 | scb->cmd.basic_io.log_drv = 0; |
| 5981 | scb->data_len = sizeof (*ha->enq); |
| 5982 | scb->cmd.basic_io.sg_addr = ha->enq_busaddr; |
| 5983 | |
| 5984 | /* send command */ |
| 5985 | if (((ret = |
| 5986 | ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) |
| 5987 | || (ret == IPS_SUCCESS_IMM) |
| 5988 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
| 5989 | return (0); |
| 5990 | |
| 5991 | return (1); |
| 5992 | } |
| 5993 | |
| 5994 | /****************************************************************************/ |
| 5995 | /* */ |
| 5996 | /* Routine Name: ips_read_subsystem_parameters */ |
| 5997 | /* */ |
| 5998 | /* Routine Description: */ |
| 5999 | /* */ |
| 6000 | /* Read subsystem parameters from the adapter */ |
| 6001 | /* */ |
| 6002 | /****************************************************************************/ |
| 6003 | static int |
| 6004 | ips_read_subsystem_parameters(ips_ha_t * ha, int intr) |
| 6005 | { |
| 6006 | ips_scb_t *scb; |
| 6007 | int ret; |
| 6008 | |
| 6009 | METHOD_TRACE("ips_read_subsystem_parameters", 1); |
| 6010 | |
| 6011 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6012 | |
| 6013 | ips_init_scb(ha, scb); |
| 6014 | |
| 6015 | scb->timeout = ips_cmd_timeout; |
| 6016 | scb->cdb[0] = IPS_CMD_GET_SUBSYS; |
| 6017 | |
| 6018 | scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; |
| 6019 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 6020 | scb->cmd.basic_io.sg_count = 0; |
| 6021 | scb->cmd.basic_io.lba = 0; |
| 6022 | scb->cmd.basic_io.sector_count = 0; |
| 6023 | scb->cmd.basic_io.log_drv = 0; |
| 6024 | scb->data_len = sizeof (*ha->subsys); |
| 6025 | scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; |
| 6026 | |
| 6027 | /* send command */ |
| 6028 | if (((ret = |
| 6029 | ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) |
| 6030 | || (ret == IPS_SUCCESS_IMM) |
| 6031 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
| 6032 | return (0); |
| 6033 | |
| 6034 | memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); |
| 6035 | return (1); |
| 6036 | } |
| 6037 | |
| 6038 | /****************************************************************************/ |
| 6039 | /* */ |
| 6040 | /* Routine Name: ips_read_config */ |
| 6041 | /* */ |
| 6042 | /* Routine Description: */ |
| 6043 | /* */ |
| 6044 | /* Read the configuration on the adapter */ |
| 6045 | /* */ |
| 6046 | /****************************************************************************/ |
| 6047 | static int |
| 6048 | ips_read_config(ips_ha_t * ha, int intr) |
| 6049 | { |
| 6050 | ips_scb_t *scb; |
| 6051 | int i; |
| 6052 | int ret; |
| 6053 | |
| 6054 | METHOD_TRACE("ips_read_config", 1); |
| 6055 | |
| 6056 | /* set defaults for initiator IDs */ |
| 6057 | for (i = 0; i < 4; i++) |
| 6058 | ha->conf->init_id[i] = 7; |
| 6059 | |
| 6060 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6061 | |
| 6062 | ips_init_scb(ha, scb); |
| 6063 | |
| 6064 | scb->timeout = ips_cmd_timeout; |
| 6065 | scb->cdb[0] = IPS_CMD_READ_CONF; |
| 6066 | |
| 6067 | scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; |
| 6068 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
| 6069 | scb->data_len = sizeof (*ha->conf); |
| 6070 | scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; |
| 6071 | |
| 6072 | /* send command */ |
| 6073 | if (((ret = |
| 6074 | ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) |
| 6075 | || (ret == IPS_SUCCESS_IMM) |
| 6076 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
| 6077 | |
| 6078 | memset(ha->conf, 0, sizeof (IPS_CONF)); |
| 6079 | |
| 6080 | /* reset initiator IDs */ |
| 6081 | for (i = 0; i < 4; i++) |
| 6082 | ha->conf->init_id[i] = 7; |
| 6083 | |
| 6084 | /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ |
| 6085 | if ((scb->basic_status & IPS_GSC_STATUS_MASK) == |
| 6086 | IPS_CMD_CMPLT_WERROR) |
| 6087 | return (1); |
| 6088 | |
| 6089 | return (0); |
| 6090 | } |
| 6091 | |
| 6092 | memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); |
| 6093 | return (1); |
| 6094 | } |
| 6095 | |
| 6096 | /****************************************************************************/ |
| 6097 | /* */ |
| 6098 | /* Routine Name: ips_readwrite_page5 */ |
| 6099 | /* */ |
| 6100 | /* Routine Description: */ |
| 6101 | /* */ |
| 6102 | /* Read nvram page 5 from the adapter */ |
| 6103 | /* */ |
| 6104 | /****************************************************************************/ |
| 6105 | static int |
| 6106 | ips_readwrite_page5(ips_ha_t * ha, int write, int intr) |
| 6107 | { |
| 6108 | ips_scb_t *scb; |
| 6109 | int ret; |
| 6110 | |
| 6111 | METHOD_TRACE("ips_readwrite_page5", 1); |
| 6112 | |
| 6113 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6114 | |
| 6115 | ips_init_scb(ha, scb); |
| 6116 | |
| 6117 | scb->timeout = ips_cmd_timeout; |
| 6118 | scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; |
| 6119 | |
| 6120 | scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; |
| 6121 | scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); |
| 6122 | scb->cmd.nvram.page = 5; |
| 6123 | scb->cmd.nvram.write = write; |
| 6124 | scb->cmd.nvram.reserved = 0; |
| 6125 | scb->cmd.nvram.reserved2 = 0; |
| 6126 | scb->data_len = sizeof (*ha->nvram); |
| 6127 | scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; |
| 6128 | if (write) |
| 6129 | memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); |
| 6130 | |
| 6131 | /* issue the command */ |
| 6132 | if (((ret = |
| 6133 | ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) |
| 6134 | || (ret == IPS_SUCCESS_IMM) |
| 6135 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
| 6136 | |
| 6137 | memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); |
| 6138 | |
| 6139 | return (0); |
| 6140 | } |
| 6141 | if (!write) |
| 6142 | memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); |
| 6143 | return (1); |
| 6144 | } |
| 6145 | |
| 6146 | /****************************************************************************/ |
| 6147 | /* */ |
| 6148 | /* Routine Name: ips_clear_adapter */ |
| 6149 | /* */ |
| 6150 | /* Routine Description: */ |
| 6151 | /* */ |
| 6152 | /* Clear the stripe lock tables */ |
| 6153 | /* */ |
| 6154 | /****************************************************************************/ |
| 6155 | static int |
| 6156 | ips_clear_adapter(ips_ha_t * ha, int intr) |
| 6157 | { |
| 6158 | ips_scb_t *scb; |
| 6159 | int ret; |
| 6160 | |
| 6161 | METHOD_TRACE("ips_clear_adapter", 1); |
| 6162 | |
| 6163 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6164 | |
| 6165 | ips_init_scb(ha, scb); |
| 6166 | |
| 6167 | scb->timeout = ips_reset_timeout; |
| 6168 | scb->cdb[0] = IPS_CMD_CONFIG_SYNC; |
| 6169 | |
| 6170 | scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; |
| 6171 | scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); |
| 6172 | scb->cmd.config_sync.channel = 0; |
| 6173 | scb->cmd.config_sync.source_target = IPS_POCL; |
| 6174 | scb->cmd.config_sync.reserved = 0; |
| 6175 | scb->cmd.config_sync.reserved2 = 0; |
| 6176 | scb->cmd.config_sync.reserved3 = 0; |
| 6177 | |
| 6178 | /* issue command */ |
| 6179 | if (((ret = |
| 6180 | ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE) |
| 6181 | || (ret == IPS_SUCCESS_IMM) |
| 6182 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
| 6183 | return (0); |
| 6184 | |
| 6185 | /* send unlock stripe command */ |
| 6186 | ips_init_scb(ha, scb); |
| 6187 | |
| 6188 | scb->cdb[0] = IPS_CMD_ERROR_TABLE; |
| 6189 | scb->timeout = ips_reset_timeout; |
| 6190 | |
| 6191 | scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; |
| 6192 | scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); |
| 6193 | scb->cmd.unlock_stripe.log_drv = 0; |
| 6194 | scb->cmd.unlock_stripe.control = IPS_CSL; |
| 6195 | scb->cmd.unlock_stripe.reserved = 0; |
| 6196 | scb->cmd.unlock_stripe.reserved2 = 0; |
| 6197 | scb->cmd.unlock_stripe.reserved3 = 0; |
| 6198 | |
| 6199 | /* issue command */ |
| 6200 | if (((ret = |
| 6201 | ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) |
| 6202 | || (ret == IPS_SUCCESS_IMM) |
| 6203 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
| 6204 | return (0); |
| 6205 | |
| 6206 | return (1); |
| 6207 | } |
| 6208 | |
| 6209 | /****************************************************************************/ |
| 6210 | /* */ |
| 6211 | /* Routine Name: ips_ffdc_reset */ |
| 6212 | /* */ |
| 6213 | /* Routine Description: */ |
| 6214 | /* */ |
| 6215 | /* FFDC: write reset info */ |
| 6216 | /* */ |
| 6217 | /****************************************************************************/ |
| 6218 | static void |
| 6219 | ips_ffdc_reset(ips_ha_t * ha, int intr) |
| 6220 | { |
| 6221 | ips_scb_t *scb; |
| 6222 | |
| 6223 | METHOD_TRACE("ips_ffdc_reset", 1); |
| 6224 | |
| 6225 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6226 | |
| 6227 | ips_init_scb(ha, scb); |
| 6228 | |
| 6229 | scb->timeout = ips_cmd_timeout; |
| 6230 | scb->cdb[0] = IPS_CMD_FFDC; |
| 6231 | scb->cmd.ffdc.op_code = IPS_CMD_FFDC; |
| 6232 | scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); |
| 6233 | scb->cmd.ffdc.reset_count = ha->reset_count; |
| 6234 | scb->cmd.ffdc.reset_type = 0x80; |
| 6235 | |
| 6236 | /* convert time to what the card wants */ |
| 6237 | ips_fix_ffdc_time(ha, scb, ha->last_ffdc); |
| 6238 | |
| 6239 | /* issue command */ |
| 6240 | ips_send_wait(ha, scb, ips_cmd_timeout, intr); |
| 6241 | } |
| 6242 | |
| 6243 | /****************************************************************************/ |
| 6244 | /* */ |
| 6245 | /* Routine Name: ips_ffdc_time */ |
| 6246 | /* */ |
| 6247 | /* Routine Description: */ |
| 6248 | /* */ |
| 6249 | /* FFDC: write time info */ |
| 6250 | /* */ |
| 6251 | /****************************************************************************/ |
| 6252 | static void |
| 6253 | ips_ffdc_time(ips_ha_t * ha) |
| 6254 | { |
| 6255 | ips_scb_t *scb; |
| 6256 | |
| 6257 | METHOD_TRACE("ips_ffdc_time", 1); |
| 6258 | |
| 6259 | DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num); |
| 6260 | |
| 6261 | scb = &ha->scbs[ha->max_cmds - 1]; |
| 6262 | |
| 6263 | ips_init_scb(ha, scb); |
| 6264 | |
| 6265 | scb->timeout = ips_cmd_timeout; |
| 6266 | scb->cdb[0] = IPS_CMD_FFDC; |
| 6267 | scb->cmd.ffdc.op_code = IPS_CMD_FFDC; |
| 6268 | scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); |
| 6269 | scb->cmd.ffdc.reset_count = 0; |
| 6270 | scb->cmd.ffdc.reset_type = 0; |
| 6271 | |
| 6272 | /* convert time to what the card wants */ |
| 6273 | ips_fix_ffdc_time(ha, scb, ha->last_ffdc); |
| 6274 | |
| 6275 | /* issue command */ |
| 6276 | ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC); |
| 6277 | } |
| 6278 | |
| 6279 | /****************************************************************************/ |
| 6280 | /* */ |
| 6281 | /* Routine Name: ips_fix_ffdc_time */ |
| 6282 | /* */ |
| 6283 | /* Routine Description: */ |
| 6284 | /* Adjust time_t to what the card wants */ |
| 6285 | /* */ |
| 6286 | /****************************************************************************/ |
| 6287 | static void |
| 6288 | ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time) |
| 6289 | { |
| 6290 | long days; |
| 6291 | long rem; |
| 6292 | int i; |
| 6293 | int year; |
| 6294 | int yleap; |
| 6295 | int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR }; |
| 6296 | int month_lengths[12][2] = { {31, 31}, |
| 6297 | {28, 29}, |
| 6298 | {31, 31}, |
| 6299 | {30, 30}, |
| 6300 | {31, 31}, |
| 6301 | {30, 30}, |
| 6302 | {31, 31}, |
| 6303 | {31, 31}, |
| 6304 | {30, 30}, |
| 6305 | {31, 31}, |
| 6306 | {30, 30}, |
| 6307 | {31, 31} |
| 6308 | }; |
| 6309 | |
| 6310 | METHOD_TRACE("ips_fix_ffdc_time", 1); |
| 6311 | |
| 6312 | days = current_time / IPS_SECS_DAY; |
| 6313 | rem = current_time % IPS_SECS_DAY; |
| 6314 | |
| 6315 | scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR); |
| 6316 | rem = rem % IPS_SECS_HOUR; |
| 6317 | scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN); |
| 6318 | scb->cmd.ffdc.second = (rem % IPS_SECS_MIN); |
| 6319 | |
| 6320 | year = IPS_EPOCH_YEAR; |
| 6321 | while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) { |
| 6322 | int newy; |
| 6323 | |
| 6324 | newy = year + (days / IPS_DAYS_NORMAL_YEAR); |
| 6325 | if (days < 0) |
| 6326 | --newy; |
| 6327 | days -= (newy - year) * IPS_DAYS_NORMAL_YEAR + |
| 6328 | IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) - |
| 6329 | IPS_NUM_LEAP_YEARS_THROUGH(year - 1); |
| 6330 | year = newy; |
| 6331 | } |
| 6332 | |
| 6333 | scb->cmd.ffdc.yearH = year / 100; |
| 6334 | scb->cmd.ffdc.yearL = year % 100; |
| 6335 | |
| 6336 | for (i = 0; days >= month_lengths[i][yleap]; ++i) |
| 6337 | days -= month_lengths[i][yleap]; |
| 6338 | |
| 6339 | scb->cmd.ffdc.month = i + 1; |
| 6340 | scb->cmd.ffdc.day = days + 1; |
| 6341 | } |
| 6342 | |
| 6343 | /**************************************************************************** |
| 6344 | * BIOS Flash Routines * |
| 6345 | ****************************************************************************/ |
| 6346 | |
| 6347 | /****************************************************************************/ |
| 6348 | /* */ |
| 6349 | /* Routine Name: ips_erase_bios */ |
| 6350 | /* */ |
| 6351 | /* Routine Description: */ |
| 6352 | /* Erase the BIOS on the adapter */ |
| 6353 | /* */ |
| 6354 | /****************************************************************************/ |
| 6355 | static int |
| 6356 | ips_erase_bios(ips_ha_t * ha) |
| 6357 | { |
| 6358 | int timeout; |
| 6359 | uint8_t status = 0; |
| 6360 | |
| 6361 | METHOD_TRACE("ips_erase_bios", 1); |
| 6362 | |
| 6363 | status = 0; |
| 6364 | |
| 6365 | /* Clear the status register */ |
| 6366 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6367 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6368 | udelay(25); /* 25 us */ |
| 6369 | |
| 6370 | outb(0x50, ha->io_addr + IPS_REG_FLDP); |
| 6371 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6372 | udelay(25); /* 25 us */ |
| 6373 | |
| 6374 | /* Erase Setup */ |
| 6375 | outb(0x20, ha->io_addr + IPS_REG_FLDP); |
| 6376 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6377 | udelay(25); /* 25 us */ |
| 6378 | |
| 6379 | /* Erase Confirm */ |
| 6380 | outb(0xD0, ha->io_addr + IPS_REG_FLDP); |
| 6381 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6382 | udelay(25); /* 25 us */ |
| 6383 | |
| 6384 | /* Erase Status */ |
| 6385 | outb(0x70, ha->io_addr + IPS_REG_FLDP); |
| 6386 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6387 | udelay(25); /* 25 us */ |
| 6388 | |
| 6389 | timeout = 80000; /* 80 seconds */ |
| 6390 | |
| 6391 | while (timeout > 0) { |
| 6392 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6393 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6394 | udelay(25); /* 25 us */ |
| 6395 | } |
| 6396 | |
| 6397 | status = inb(ha->io_addr + IPS_REG_FLDP); |
| 6398 | |
| 6399 | if (status & 0x80) |
| 6400 | break; |
| 6401 | |
| 6402 | MDELAY(1); |
| 6403 | timeout--; |
| 6404 | } |
| 6405 | |
| 6406 | /* check for timeout */ |
| 6407 | if (timeout <= 0) { |
| 6408 | /* timeout */ |
| 6409 | |
| 6410 | /* try to suspend the erase */ |
| 6411 | outb(0xB0, ha->io_addr + IPS_REG_FLDP); |
| 6412 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6413 | udelay(25); /* 25 us */ |
| 6414 | |
| 6415 | /* wait for 10 seconds */ |
| 6416 | timeout = 10000; |
| 6417 | while (timeout > 0) { |
| 6418 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6419 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6420 | udelay(25); /* 25 us */ |
| 6421 | } |
| 6422 | |
| 6423 | status = inb(ha->io_addr + IPS_REG_FLDP); |
| 6424 | |
| 6425 | if (status & 0xC0) |
| 6426 | break; |
| 6427 | |
| 6428 | MDELAY(1); |
| 6429 | timeout--; |
| 6430 | } |
| 6431 | |
| 6432 | return (1); |
| 6433 | } |
| 6434 | |
| 6435 | /* check for valid VPP */ |
| 6436 | if (status & 0x08) |
| 6437 | /* VPP failure */ |
| 6438 | return (1); |
| 6439 | |
| 6440 | /* check for succesful flash */ |
| 6441 | if (status & 0x30) |
| 6442 | /* sequence error */ |
| 6443 | return (1); |
| 6444 | |
| 6445 | /* Otherwise, we were successful */ |
| 6446 | /* clear status */ |
| 6447 | outb(0x50, ha->io_addr + IPS_REG_FLDP); |
| 6448 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6449 | udelay(25); /* 25 us */ |
| 6450 | |
| 6451 | /* enable reads */ |
| 6452 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
| 6453 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6454 | udelay(25); /* 25 us */ |
| 6455 | |
| 6456 | return (0); |
| 6457 | } |
| 6458 | |
| 6459 | /****************************************************************************/ |
| 6460 | /* */ |
| 6461 | /* Routine Name: ips_erase_bios_memio */ |
| 6462 | /* */ |
| 6463 | /* Routine Description: */ |
| 6464 | /* Erase the BIOS on the adapter */ |
| 6465 | /* */ |
| 6466 | /****************************************************************************/ |
| 6467 | static int |
| 6468 | ips_erase_bios_memio(ips_ha_t * ha) |
| 6469 | { |
| 6470 | int timeout; |
| 6471 | uint8_t status; |
| 6472 | |
| 6473 | METHOD_TRACE("ips_erase_bios_memio", 1); |
| 6474 | |
| 6475 | status = 0; |
| 6476 | |
| 6477 | /* Clear the status register */ |
| 6478 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6479 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6480 | udelay(25); /* 25 us */ |
| 6481 | |
| 6482 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); |
| 6483 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6484 | udelay(25); /* 25 us */ |
| 6485 | |
| 6486 | /* Erase Setup */ |
| 6487 | writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); |
| 6488 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6489 | udelay(25); /* 25 us */ |
| 6490 | |
| 6491 | /* Erase Confirm */ |
| 6492 | writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); |
| 6493 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6494 | udelay(25); /* 25 us */ |
| 6495 | |
| 6496 | /* Erase Status */ |
| 6497 | writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); |
| 6498 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6499 | udelay(25); /* 25 us */ |
| 6500 | |
| 6501 | timeout = 80000; /* 80 seconds */ |
| 6502 | |
| 6503 | while (timeout > 0) { |
| 6504 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6505 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6506 | udelay(25); /* 25 us */ |
| 6507 | } |
| 6508 | |
| 6509 | status = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 6510 | |
| 6511 | if (status & 0x80) |
| 6512 | break; |
| 6513 | |
| 6514 | MDELAY(1); |
| 6515 | timeout--; |
| 6516 | } |
| 6517 | |
| 6518 | /* check for timeout */ |
| 6519 | if (timeout <= 0) { |
| 6520 | /* timeout */ |
| 6521 | |
| 6522 | /* try to suspend the erase */ |
| 6523 | writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); |
| 6524 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6525 | udelay(25); /* 25 us */ |
| 6526 | |
| 6527 | /* wait for 10 seconds */ |
| 6528 | timeout = 10000; |
| 6529 | while (timeout > 0) { |
| 6530 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6531 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6532 | udelay(25); /* 25 us */ |
| 6533 | } |
| 6534 | |
| 6535 | status = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 6536 | |
| 6537 | if (status & 0xC0) |
| 6538 | break; |
| 6539 | |
| 6540 | MDELAY(1); |
| 6541 | timeout--; |
| 6542 | } |
| 6543 | |
| 6544 | return (1); |
| 6545 | } |
| 6546 | |
| 6547 | /* check for valid VPP */ |
| 6548 | if (status & 0x08) |
| 6549 | /* VPP failure */ |
| 6550 | return (1); |
| 6551 | |
| 6552 | /* check for succesful flash */ |
| 6553 | if (status & 0x30) |
| 6554 | /* sequence error */ |
| 6555 | return (1); |
| 6556 | |
| 6557 | /* Otherwise, we were successful */ |
| 6558 | /* clear status */ |
| 6559 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); |
| 6560 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6561 | udelay(25); /* 25 us */ |
| 6562 | |
| 6563 | /* enable reads */ |
| 6564 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
| 6565 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6566 | udelay(25); /* 25 us */ |
| 6567 | |
| 6568 | return (0); |
| 6569 | } |
| 6570 | |
| 6571 | /****************************************************************************/ |
| 6572 | /* */ |
| 6573 | /* Routine Name: ips_program_bios */ |
| 6574 | /* */ |
| 6575 | /* Routine Description: */ |
| 6576 | /* Program the BIOS on the adapter */ |
| 6577 | /* */ |
| 6578 | /****************************************************************************/ |
| 6579 | static int |
| 6580 | ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
| 6581 | uint32_t offset) |
| 6582 | { |
| 6583 | int i; |
| 6584 | int timeout; |
| 6585 | uint8_t status = 0; |
| 6586 | |
| 6587 | METHOD_TRACE("ips_program_bios", 1); |
| 6588 | |
| 6589 | status = 0; |
| 6590 | |
| 6591 | for (i = 0; i < buffersize; i++) { |
| 6592 | /* write a byte */ |
| 6593 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); |
| 6594 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6595 | udelay(25); /* 25 us */ |
| 6596 | |
| 6597 | outb(0x40, ha->io_addr + IPS_REG_FLDP); |
| 6598 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6599 | udelay(25); /* 25 us */ |
| 6600 | |
| 6601 | outb(buffer[i], ha->io_addr + IPS_REG_FLDP); |
| 6602 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6603 | udelay(25); /* 25 us */ |
| 6604 | |
| 6605 | /* wait up to one second */ |
| 6606 | timeout = 1000; |
| 6607 | while (timeout > 0) { |
| 6608 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6609 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6610 | udelay(25); /* 25 us */ |
| 6611 | } |
| 6612 | |
| 6613 | status = inb(ha->io_addr + IPS_REG_FLDP); |
| 6614 | |
| 6615 | if (status & 0x80) |
| 6616 | break; |
| 6617 | |
| 6618 | MDELAY(1); |
| 6619 | timeout--; |
| 6620 | } |
| 6621 | |
| 6622 | if (timeout == 0) { |
| 6623 | /* timeout error */ |
| 6624 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6625 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6626 | udelay(25); /* 25 us */ |
| 6627 | |
| 6628 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
| 6629 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6630 | udelay(25); /* 25 us */ |
| 6631 | |
| 6632 | return (1); |
| 6633 | } |
| 6634 | |
| 6635 | /* check the status */ |
| 6636 | if (status & 0x18) { |
| 6637 | /* programming error */ |
| 6638 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6639 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6640 | udelay(25); /* 25 us */ |
| 6641 | |
| 6642 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
| 6643 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6644 | udelay(25); /* 25 us */ |
| 6645 | |
| 6646 | return (1); |
| 6647 | } |
| 6648 | } /* end for */ |
| 6649 | |
| 6650 | /* Enable reading */ |
| 6651 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6652 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6653 | udelay(25); /* 25 us */ |
| 6654 | |
| 6655 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
| 6656 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6657 | udelay(25); /* 25 us */ |
| 6658 | |
| 6659 | return (0); |
| 6660 | } |
| 6661 | |
| 6662 | /****************************************************************************/ |
| 6663 | /* */ |
| 6664 | /* Routine Name: ips_program_bios_memio */ |
| 6665 | /* */ |
| 6666 | /* Routine Description: */ |
| 6667 | /* Program the BIOS on the adapter */ |
| 6668 | /* */ |
| 6669 | /****************************************************************************/ |
| 6670 | static int |
| 6671 | ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
| 6672 | uint32_t offset) |
| 6673 | { |
| 6674 | int i; |
| 6675 | int timeout; |
| 6676 | uint8_t status = 0; |
| 6677 | |
| 6678 | METHOD_TRACE("ips_program_bios_memio", 1); |
| 6679 | |
| 6680 | status = 0; |
| 6681 | |
| 6682 | for (i = 0; i < buffersize; i++) { |
| 6683 | /* write a byte */ |
| 6684 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); |
| 6685 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6686 | udelay(25); /* 25 us */ |
| 6687 | |
| 6688 | writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); |
| 6689 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6690 | udelay(25); /* 25 us */ |
| 6691 | |
| 6692 | writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); |
| 6693 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6694 | udelay(25); /* 25 us */ |
| 6695 | |
| 6696 | /* wait up to one second */ |
| 6697 | timeout = 1000; |
| 6698 | while (timeout > 0) { |
| 6699 | if (ha->revision_id == IPS_REVID_TROMBONE64) { |
| 6700 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6701 | udelay(25); /* 25 us */ |
| 6702 | } |
| 6703 | |
| 6704 | status = readb(ha->mem_ptr + IPS_REG_FLDP); |
| 6705 | |
| 6706 | if (status & 0x80) |
| 6707 | break; |
| 6708 | |
| 6709 | MDELAY(1); |
| 6710 | timeout--; |
| 6711 | } |
| 6712 | |
| 6713 | if (timeout == 0) { |
| 6714 | /* timeout error */ |
| 6715 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6716 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6717 | udelay(25); /* 25 us */ |
| 6718 | |
| 6719 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
| 6720 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6721 | udelay(25); /* 25 us */ |
| 6722 | |
| 6723 | return (1); |
| 6724 | } |
| 6725 | |
| 6726 | /* check the status */ |
| 6727 | if (status & 0x18) { |
| 6728 | /* programming error */ |
| 6729 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6730 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6731 | udelay(25); /* 25 us */ |
| 6732 | |
| 6733 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
| 6734 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6735 | udelay(25); /* 25 us */ |
| 6736 | |
| 6737 | return (1); |
| 6738 | } |
| 6739 | } /* end for */ |
| 6740 | |
| 6741 | /* Enable reading */ |
| 6742 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6743 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6744 | udelay(25); /* 25 us */ |
| 6745 | |
| 6746 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
| 6747 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6748 | udelay(25); /* 25 us */ |
| 6749 | |
| 6750 | return (0); |
| 6751 | } |
| 6752 | |
| 6753 | /****************************************************************************/ |
| 6754 | /* */ |
| 6755 | /* Routine Name: ips_verify_bios */ |
| 6756 | /* */ |
| 6757 | /* Routine Description: */ |
| 6758 | /* Verify the BIOS on the adapter */ |
| 6759 | /* */ |
| 6760 | /****************************************************************************/ |
| 6761 | static int |
| 6762 | ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
| 6763 | uint32_t offset) |
| 6764 | { |
| 6765 | uint8_t checksum; |
| 6766 | int i; |
| 6767 | |
| 6768 | METHOD_TRACE("ips_verify_bios", 1); |
| 6769 | |
| 6770 | /* test 1st byte */ |
| 6771 | outl(0, ha->io_addr + IPS_REG_FLAP); |
| 6772 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6773 | udelay(25); /* 25 us */ |
| 6774 | |
| 6775 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) |
| 6776 | return (1); |
| 6777 | |
| 6778 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); |
| 6779 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6780 | udelay(25); /* 25 us */ |
| 6781 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) |
| 6782 | return (1); |
| 6783 | |
| 6784 | checksum = 0xff; |
| 6785 | for (i = 2; i < buffersize; i++) { |
| 6786 | |
| 6787 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); |
| 6788 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6789 | udelay(25); /* 25 us */ |
| 6790 | |
| 6791 | checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); |
| 6792 | } |
| 6793 | |
| 6794 | if (checksum != 0) |
| 6795 | /* failure */ |
| 6796 | return (1); |
| 6797 | else |
| 6798 | /* success */ |
| 6799 | return (0); |
| 6800 | } |
| 6801 | |
| 6802 | /****************************************************************************/ |
| 6803 | /* */ |
| 6804 | /* Routine Name: ips_verify_bios_memio */ |
| 6805 | /* */ |
| 6806 | /* Routine Description: */ |
| 6807 | /* Verify the BIOS on the adapter */ |
| 6808 | /* */ |
| 6809 | /****************************************************************************/ |
| 6810 | static int |
| 6811 | ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
| 6812 | uint32_t offset) |
| 6813 | { |
| 6814 | uint8_t checksum; |
| 6815 | int i; |
| 6816 | |
| 6817 | METHOD_TRACE("ips_verify_bios_memio", 1); |
| 6818 | |
| 6819 | /* test 1st byte */ |
| 6820 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
| 6821 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6822 | udelay(25); /* 25 us */ |
| 6823 | |
| 6824 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
| 6825 | return (1); |
| 6826 | |
| 6827 | writel(1, ha->mem_ptr + IPS_REG_FLAP); |
| 6828 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6829 | udelay(25); /* 25 us */ |
| 6830 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
| 6831 | return (1); |
| 6832 | |
| 6833 | checksum = 0xff; |
| 6834 | for (i = 2; i < buffersize; i++) { |
| 6835 | |
| 6836 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); |
| 6837 | if (ha->revision_id == IPS_REVID_TROMBONE64) |
| 6838 | udelay(25); /* 25 us */ |
| 6839 | |
| 6840 | checksum = |
| 6841 | (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); |
| 6842 | } |
| 6843 | |
| 6844 | if (checksum != 0) |
| 6845 | /* failure */ |
| 6846 | return (1); |
| 6847 | else |
| 6848 | /* success */ |
| 6849 | return (0); |
| 6850 | } |
| 6851 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6852 | /****************************************************************************/ |
| 6853 | /* */ |
| 6854 | /* Routine Name: ips_abort_init */ |
| 6855 | /* */ |
| 6856 | /* Routine Description: */ |
| 6857 | /* cleanup routine for a failed adapter initialization */ |
| 6858 | /****************************************************************************/ |
| 6859 | static int |
| 6860 | ips_abort_init(ips_ha_t * ha, int index) |
| 6861 | { |
| 6862 | ha->active = 0; |
| 6863 | ips_free(ha); |
| 6864 | ips_ha[index] = NULL; |
| 6865 | ips_sh[index] = NULL; |
| 6866 | return -1; |
| 6867 | } |
| 6868 | |
| 6869 | /****************************************************************************/ |
| 6870 | /* */ |
| 6871 | /* Routine Name: ips_shift_controllers */ |
| 6872 | /* */ |
| 6873 | /* Routine Description: */ |
| 6874 | /* helper function for ordering adapters */ |
| 6875 | /****************************************************************************/ |
| 6876 | static void |
| 6877 | ips_shift_controllers(int lowindex, int highindex) |
| 6878 | { |
| 6879 | ips_ha_t *ha_sav = ips_ha[highindex]; |
| 6880 | struct Scsi_Host *sh_sav = ips_sh[highindex]; |
| 6881 | int i; |
| 6882 | |
| 6883 | for (i = highindex; i > lowindex; i--) { |
| 6884 | ips_ha[i] = ips_ha[i - 1]; |
| 6885 | ips_sh[i] = ips_sh[i - 1]; |
| 6886 | ips_ha[i]->host_num = i; |
| 6887 | } |
| 6888 | ha_sav->host_num = lowindex; |
| 6889 | ips_ha[lowindex] = ha_sav; |
| 6890 | ips_sh[lowindex] = sh_sav; |
| 6891 | } |
| 6892 | |
| 6893 | /****************************************************************************/ |
| 6894 | /* */ |
| 6895 | /* Routine Name: ips_order_controllers */ |
| 6896 | /* */ |
| 6897 | /* Routine Description: */ |
| 6898 | /* place controllers is the "proper" boot order */ |
| 6899 | /****************************************************************************/ |
| 6900 | static void |
| 6901 | ips_order_controllers(void) |
| 6902 | { |
| 6903 | int i, j, tmp, position = 0; |
| 6904 | IPS_NVRAM_P5 *nvram; |
| 6905 | if (!ips_ha[0]) |
| 6906 | return; |
| 6907 | nvram = ips_ha[0]->nvram; |
| 6908 | |
| 6909 | if (nvram->adapter_order[0]) { |
| 6910 | for (i = 1; i <= nvram->adapter_order[0]; i++) { |
| 6911 | for (j = position; j < ips_num_controllers; j++) { |
| 6912 | switch (ips_ha[j]->ad_type) { |
| 6913 | case IPS_ADTYPE_SERVERAID6M: |
| 6914 | case IPS_ADTYPE_SERVERAID7M: |
| 6915 | if (nvram->adapter_order[i] == 'M') { |
| 6916 | ips_shift_controllers(position, |
| 6917 | j); |
| 6918 | position++; |
| 6919 | } |
| 6920 | break; |
| 6921 | case IPS_ADTYPE_SERVERAID4L: |
| 6922 | case IPS_ADTYPE_SERVERAID4M: |
| 6923 | case IPS_ADTYPE_SERVERAID4MX: |
| 6924 | case IPS_ADTYPE_SERVERAID4LX: |
| 6925 | if (nvram->adapter_order[i] == 'N') { |
| 6926 | ips_shift_controllers(position, |
| 6927 | j); |
| 6928 | position++; |
| 6929 | } |
| 6930 | break; |
| 6931 | case IPS_ADTYPE_SERVERAID6I: |
| 6932 | case IPS_ADTYPE_SERVERAID5I2: |
| 6933 | case IPS_ADTYPE_SERVERAID5I1: |
| 6934 | case IPS_ADTYPE_SERVERAID7k: |
| 6935 | if (nvram->adapter_order[i] == 'S') { |
| 6936 | ips_shift_controllers(position, |
| 6937 | j); |
| 6938 | position++; |
| 6939 | } |
| 6940 | break; |
| 6941 | case IPS_ADTYPE_SERVERAID: |
| 6942 | case IPS_ADTYPE_SERVERAID2: |
| 6943 | case IPS_ADTYPE_NAVAJO: |
| 6944 | case IPS_ADTYPE_KIOWA: |
| 6945 | case IPS_ADTYPE_SERVERAID3L: |
| 6946 | case IPS_ADTYPE_SERVERAID3: |
| 6947 | case IPS_ADTYPE_SERVERAID4H: |
| 6948 | if (nvram->adapter_order[i] == 'A') { |
| 6949 | ips_shift_controllers(position, |
| 6950 | j); |
| 6951 | position++; |
| 6952 | } |
| 6953 | break; |
| 6954 | default: |
| 6955 | break; |
| 6956 | } |
| 6957 | } |
| 6958 | } |
| 6959 | /* if adapter_order[0], then ordering is complete */ |
| 6960 | return; |
| 6961 | } |
| 6962 | /* old bios, use older ordering */ |
| 6963 | tmp = 0; |
| 6964 | for (i = position; i < ips_num_controllers; i++) { |
| 6965 | if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || |
| 6966 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { |
| 6967 | ips_shift_controllers(position, i); |
| 6968 | position++; |
| 6969 | tmp = 1; |
| 6970 | } |
| 6971 | } |
| 6972 | /* if there were no 5I cards, then don't do any extra ordering */ |
| 6973 | if (!tmp) |
| 6974 | return; |
| 6975 | for (i = position; i < ips_num_controllers; i++) { |
| 6976 | if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || |
| 6977 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || |
| 6978 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || |
| 6979 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { |
| 6980 | ips_shift_controllers(position, i); |
| 6981 | position++; |
| 6982 | } |
| 6983 | } |
| 6984 | |
| 6985 | return; |
| 6986 | } |
| 6987 | |
| 6988 | /****************************************************************************/ |
| 6989 | /* */ |
| 6990 | /* Routine Name: ips_register_scsi */ |
| 6991 | /* */ |
| 6992 | /* Routine Description: */ |
| 6993 | /* perform any registration and setup with the scsi layer */ |
| 6994 | /****************************************************************************/ |
| 6995 | static int |
| 6996 | ips_register_scsi(int index) |
| 6997 | { |
| 6998 | struct Scsi_Host *sh; |
| 6999 | ips_ha_t *ha, *oldha = ips_ha[index]; |
| 7000 | sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); |
| 7001 | if (!sh) { |
| 7002 | IPS_PRINTK(KERN_WARNING, oldha->pcidev, |
| 7003 | "Unable to register controller with SCSI subsystem\n"); |
| 7004 | return -1; |
| 7005 | } |
| 7006 | ha = IPS_HA(sh); |
| 7007 | memcpy(ha, oldha, sizeof (ips_ha_t)); |
| 7008 | free_irq(oldha->irq, oldha); |
| 7009 | /* Install the interrupt handler with the new ha */ |
| 7010 | if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) { |
| 7011 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 7012 | "Unable to install interrupt handler\n"); |
| 7013 | scsi_host_put(sh); |
| 7014 | return -1; |
| 7015 | } |
| 7016 | |
| 7017 | kfree(oldha); |
| 7018 | ips_sh[index] = sh; |
| 7019 | ips_ha[index] = ha; |
| 7020 | IPS_SCSI_SET_DEVICE(sh, ha); |
| 7021 | |
| 7022 | /* Store away needed values for later use */ |
| 7023 | sh->io_port = ha->io_addr; |
| 7024 | sh->n_io_port = ha->io_addr ? 255 : 0; |
| 7025 | sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; |
| 7026 | sh->irq = ha->irq; |
| 7027 | sh->sg_tablesize = sh->hostt->sg_tablesize; |
| 7028 | sh->can_queue = sh->hostt->can_queue; |
| 7029 | sh->cmd_per_lun = sh->hostt->cmd_per_lun; |
| 7030 | sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma; |
| 7031 | sh->use_clustering = sh->hostt->use_clustering; |
| 7032 | |
| 7033 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7) |
| 7034 | sh->max_sectors = 128; |
| 7035 | #endif |
| 7036 | |
| 7037 | sh->max_id = ha->ntargets; |
| 7038 | sh->max_lun = ha->nlun; |
| 7039 | sh->max_channel = ha->nbus - 1; |
| 7040 | sh->can_queue = ha->max_cmds - 1; |
| 7041 | |
| 7042 | IPS_ADD_HOST(sh, NULL); |
| 7043 | return 0; |
| 7044 | } |
| 7045 | |
| 7046 | /*---------------------------------------------------------------------------*/ |
| 7047 | /* Routine Name: ips_remove_device */ |
| 7048 | /* */ |
| 7049 | /* Routine Description: */ |
| 7050 | /* Remove one Adapter ( Hot Plugging ) */ |
| 7051 | /*---------------------------------------------------------------------------*/ |
| 7052 | static void __devexit |
| 7053 | ips_remove_device(struct pci_dev *pci_dev) |
| 7054 | { |
| 7055 | int i; |
| 7056 | struct Scsi_Host *sh; |
| 7057 | ips_ha_t *ha; |
| 7058 | |
| 7059 | for (i = 0; i < IPS_MAX_ADAPTERS; i++) { |
| 7060 | ha = ips_ha[i]; |
| 7061 | if (ha) { |
| 7062 | if ((pci_dev->bus->number == ha->pcidev->bus->number) && |
| 7063 | (pci_dev->devfn == ha->pcidev->devfn)) { |
| 7064 | sh = ips_sh[i]; |
| 7065 | ips_release(sh); |
| 7066 | } |
| 7067 | } |
| 7068 | } |
| 7069 | } |
| 7070 | |
| 7071 | /****************************************************************************/ |
| 7072 | /* */ |
| 7073 | /* Routine Name: ips_module_init */ |
| 7074 | /* */ |
| 7075 | /* Routine Description: */ |
| 7076 | /* function called on module load */ |
| 7077 | /****************************************************************************/ |
| 7078 | static int __init |
| 7079 | ips_module_init(void) |
| 7080 | { |
| 7081 | if (pci_module_init(&ips_pci_driver) < 0) |
| 7082 | return -ENODEV; |
| 7083 | ips_driver_template.module = THIS_MODULE; |
| 7084 | ips_order_controllers(); |
| 7085 | if (IPS_REGISTER_HOSTS(&ips_driver_template)) { |
| 7086 | pci_unregister_driver(&ips_pci_driver); |
| 7087 | return -ENODEV; |
| 7088 | } |
| 7089 | register_reboot_notifier(&ips_notifier); |
| 7090 | return 0; |
| 7091 | } |
| 7092 | |
| 7093 | /****************************************************************************/ |
| 7094 | /* */ |
| 7095 | /* Routine Name: ips_module_exit */ |
| 7096 | /* */ |
| 7097 | /* Routine Description: */ |
| 7098 | /* function called on module unload */ |
| 7099 | /****************************************************************************/ |
| 7100 | static void __exit |
| 7101 | ips_module_exit(void) |
| 7102 | { |
| 7103 | IPS_UNREGISTER_HOSTS(&ips_driver_template); |
| 7104 | pci_unregister_driver(&ips_pci_driver); |
| 7105 | unregister_reboot_notifier(&ips_notifier); |
| 7106 | } |
| 7107 | |
| 7108 | module_init(ips_module_init); |
| 7109 | module_exit(ips_module_exit); |
| 7110 | |
| 7111 | /*---------------------------------------------------------------------------*/ |
| 7112 | /* Routine Name: ips_insert_device */ |
| 7113 | /* */ |
| 7114 | /* Routine Description: */ |
| 7115 | /* Add One Adapter ( Hot Plug ) */ |
| 7116 | /* */ |
| 7117 | /* Return Value: */ |
| 7118 | /* 0 if Successful, else non-zero */ |
| 7119 | /*---------------------------------------------------------------------------*/ |
| 7120 | static int __devinit |
| 7121 | ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) |
| 7122 | { |
| 7123 | int index; |
| 7124 | int rc; |
| 7125 | |
| 7126 | METHOD_TRACE("ips_insert_device", 1); |
| 7127 | if (pci_enable_device(pci_dev)) |
| 7128 | return -1; |
| 7129 | |
| 7130 | rc = ips_init_phase1(pci_dev, &index); |
| 7131 | if (rc == SUCCESS) |
| 7132 | rc = ips_init_phase2(index); |
| 7133 | |
| 7134 | if (ips_hotplug) |
| 7135 | if (ips_register_scsi(index)) { |
| 7136 | ips_free(ips_ha[index]); |
| 7137 | rc = -1; |
| 7138 | } |
| 7139 | |
| 7140 | if (rc == SUCCESS) |
| 7141 | ips_num_controllers++; |
| 7142 | |
| 7143 | ips_next_controller = ips_num_controllers; |
| 7144 | return rc; |
| 7145 | } |
| 7146 | |
| 7147 | /*---------------------------------------------------------------------------*/ |
| 7148 | /* Routine Name: ips_init_phase1 */ |
| 7149 | /* */ |
| 7150 | /* Routine Description: */ |
| 7151 | /* Adapter Initialization */ |
| 7152 | /* */ |
| 7153 | /* Return Value: */ |
| 7154 | /* 0 if Successful, else non-zero */ |
| 7155 | /*---------------------------------------------------------------------------*/ |
| 7156 | static int |
| 7157 | ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) |
| 7158 | { |
| 7159 | ips_ha_t *ha; |
| 7160 | uint32_t io_addr; |
| 7161 | uint32_t mem_addr; |
| 7162 | uint32_t io_len; |
| 7163 | uint32_t mem_len; |
| 7164 | uint8_t revision_id; |
| 7165 | uint8_t bus; |
| 7166 | uint8_t func; |
| 7167 | uint8_t irq; |
| 7168 | uint16_t subdevice_id; |
| 7169 | int j; |
| 7170 | int index; |
| 7171 | dma_addr_t dma_address; |
| 7172 | char __iomem *ioremap_ptr; |
| 7173 | char __iomem *mem_ptr; |
| 7174 | uint32_t IsDead; |
| 7175 | |
| 7176 | METHOD_TRACE("ips_init_phase1", 1); |
| 7177 | index = IPS_MAX_ADAPTERS; |
| 7178 | for (j = 0; j < IPS_MAX_ADAPTERS; j++) { |
| 7179 | if (ips_ha[j] == 0) { |
| 7180 | index = j; |
| 7181 | break; |
| 7182 | } |
| 7183 | } |
| 7184 | |
| 7185 | if (index >= IPS_MAX_ADAPTERS) |
| 7186 | return -1; |
| 7187 | |
| 7188 | /* stuff that we get in dev */ |
| 7189 | irq = pci_dev->irq; |
| 7190 | bus = pci_dev->bus->number; |
| 7191 | func = pci_dev->devfn; |
| 7192 | |
| 7193 | /* Init MEM/IO addresses to 0 */ |
| 7194 | mem_addr = 0; |
| 7195 | io_addr = 0; |
| 7196 | mem_len = 0; |
| 7197 | io_len = 0; |
| 7198 | |
| 7199 | for (j = 0; j < 2; j++) { |
| 7200 | if (!pci_resource_start(pci_dev, j)) |
| 7201 | break; |
| 7202 | |
| 7203 | if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { |
| 7204 | io_addr = pci_resource_start(pci_dev, j); |
| 7205 | io_len = pci_resource_len(pci_dev, j); |
| 7206 | } else { |
| 7207 | mem_addr = pci_resource_start(pci_dev, j); |
| 7208 | mem_len = pci_resource_len(pci_dev, j); |
| 7209 | } |
| 7210 | } |
| 7211 | |
| 7212 | /* setup memory mapped area (if applicable) */ |
| 7213 | if (mem_addr) { |
| 7214 | uint32_t base; |
| 7215 | uint32_t offs; |
| 7216 | |
| 7217 | if (!request_mem_region(mem_addr, mem_len, "ips")) { |
| 7218 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7219 | "Couldn't allocate IO Memory space %x len %d.\n", |
| 7220 | mem_addr, mem_len); |
| 7221 | return -1; |
| 7222 | } |
| 7223 | |
| 7224 | base = mem_addr & PAGE_MASK; |
| 7225 | offs = mem_addr - base; |
| 7226 | ioremap_ptr = ioremap(base, PAGE_SIZE); |
| 7227 | mem_ptr = ioremap_ptr + offs; |
| 7228 | } else { |
| 7229 | ioremap_ptr = NULL; |
| 7230 | mem_ptr = NULL; |
| 7231 | } |
| 7232 | |
| 7233 | /* setup I/O mapped area (if applicable) */ |
| 7234 | if (io_addr) { |
| 7235 | if (!request_region(io_addr, io_len, "ips")) { |
| 7236 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7237 | "Couldn't allocate IO space %x len %d.\n", |
| 7238 | io_addr, io_len); |
| 7239 | return -1; |
| 7240 | } |
| 7241 | } |
| 7242 | |
| 7243 | /* get the revision ID */ |
| 7244 | if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) { |
| 7245 | IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n"); |
| 7246 | return -1; |
| 7247 | } |
| 7248 | |
| 7249 | subdevice_id = pci_dev->subsystem_device; |
| 7250 | |
| 7251 | /* found a controller */ |
| 7252 | ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL); |
| 7253 | if (ha == NULL) { |
| 7254 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7255 | "Unable to allocate temporary ha struct\n"); |
| 7256 | return -1; |
| 7257 | } |
| 7258 | |
| 7259 | memset(ha, 0, sizeof (ips_ha_t)); |
| 7260 | |
| 7261 | ips_sh[index] = NULL; |
| 7262 | ips_ha[index] = ha; |
| 7263 | ha->active = 1; |
| 7264 | |
| 7265 | /* Store info in HA structure */ |
| 7266 | ha->irq = irq; |
| 7267 | ha->io_addr = io_addr; |
| 7268 | ha->io_len = io_len; |
| 7269 | ha->mem_addr = mem_addr; |
| 7270 | ha->mem_len = mem_len; |
| 7271 | ha->mem_ptr = mem_ptr; |
| 7272 | ha->ioremap_ptr = ioremap_ptr; |
| 7273 | ha->host_num = (uint32_t) index; |
| 7274 | ha->revision_id = revision_id; |
| 7275 | ha->slot_num = PCI_SLOT(pci_dev->devfn); |
| 7276 | ha->device_id = pci_dev->device; |
| 7277 | ha->subdevice_id = subdevice_id; |
| 7278 | ha->pcidev = pci_dev; |
| 7279 | |
| 7280 | /* |
| 7281 | * Set the pci_dev's dma_mask. Not all adapters support 64bit |
| 7282 | * addressing so don't enable it if the adapter can't support |
| 7283 | * it! Also, don't use 64bit addressing if dma addresses |
| 7284 | * are guaranteed to be < 4G. |
| 7285 | */ |
| 7286 | if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) && |
| 7287 | !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) { |
| 7288 | (ha)->flags |= IPS_HA_ENH_SG; |
| 7289 | } else { |
| 7290 | if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) { |
| 7291 | printk(KERN_WARNING "Unable to set DMA Mask\n"); |
| 7292 | return ips_abort_init(ha, index); |
| 7293 | } |
| 7294 | } |
| 7295 | if(ips_cd_boot && !ips_FlashData){ |
| 7296 | ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7, |
| 7297 | &ips_flashbusaddr); |
| 7298 | } |
| 7299 | |
| 7300 | ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ), |
| 7301 | &ha->enq_busaddr); |
| 7302 | if (!ha->enq) { |
| 7303 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7304 | "Unable to allocate host inquiry structure\n"); |
| 7305 | return ips_abort_init(ha, index); |
| 7306 | } |
| 7307 | |
| 7308 | ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) + |
| 7309 | sizeof (IPS_IO_CMD), &dma_address); |
| 7310 | if (!ha->adapt) { |
| 7311 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7312 | "Unable to allocate host adapt & dummy structures\n"); |
| 7313 | return ips_abort_init(ha, index); |
| 7314 | } |
| 7315 | ha->adapt->hw_status_start = dma_address; |
| 7316 | ha->dummy = (void *) (ha->adapt + 1); |
| 7317 | |
| 7318 | |
| 7319 | |
| 7320 | ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address); |
| 7321 | if (!ha->logical_drive_info) { |
| 7322 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7323 | "Unable to allocate logical drive info structure\n"); |
| 7324 | return ips_abort_init(ha, index); |
| 7325 | } |
| 7326 | ha->logical_drive_info_dma_addr = dma_address; |
| 7327 | |
| 7328 | |
| 7329 | ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL); |
| 7330 | |
| 7331 | if (!ha->conf) { |
| 7332 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7333 | "Unable to allocate host conf structure\n"); |
| 7334 | return ips_abort_init(ha, index); |
| 7335 | } |
| 7336 | |
| 7337 | ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL); |
| 7338 | |
| 7339 | if (!ha->nvram) { |
| 7340 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7341 | "Unable to allocate host NVRAM structure\n"); |
| 7342 | return ips_abort_init(ha, index); |
| 7343 | } |
| 7344 | |
| 7345 | ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL); |
| 7346 | |
| 7347 | if (!ha->subsys) { |
| 7348 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7349 | "Unable to allocate host subsystem structure\n"); |
| 7350 | return ips_abort_init(ha, index); |
| 7351 | } |
| 7352 | |
| 7353 | /* the ioctl buffer is now used during adapter initialization, so its |
| 7354 | * successful allocation is now required */ |
| 7355 | if (ips_ioctlsize < PAGE_SIZE) |
| 7356 | ips_ioctlsize = PAGE_SIZE; |
| 7357 | |
| 7358 | ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize, |
| 7359 | &ha->ioctl_busaddr); |
| 7360 | ha->ioctl_len = ips_ioctlsize; |
| 7361 | if (!ha->ioctl_data) { |
| 7362 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7363 | "Unable to allocate IOCTL data\n"); |
| 7364 | return ips_abort_init(ha, index); |
| 7365 | } |
| 7366 | |
| 7367 | /* |
| 7368 | * Setup Functions |
| 7369 | */ |
| 7370 | ips_setup_funclist(ha); |
| 7371 | |
| 7372 | if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { |
| 7373 | /* If Morpheus appears dead, reset it */ |
| 7374 | IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); |
| 7375 | if (IsDead == 0xDEADBEEF) { |
| 7376 | ips_reset_morpheus(ha); |
| 7377 | } |
| 7378 | } |
| 7379 | |
| 7380 | /* |
| 7381 | * Initialize the card if it isn't already |
| 7382 | */ |
| 7383 | |
| 7384 | if (!(*ha->func.isinit) (ha)) { |
| 7385 | if (!(*ha->func.init) (ha)) { |
| 7386 | /* |
| 7387 | * Initialization failed |
| 7388 | */ |
| 7389 | IPS_PRINTK(KERN_WARNING, pci_dev, |
| 7390 | "Unable to initialize controller\n"); |
| 7391 | return ips_abort_init(ha, index); |
| 7392 | } |
| 7393 | } |
| 7394 | |
| 7395 | *indexPtr = index; |
| 7396 | return SUCCESS; |
| 7397 | } |
| 7398 | |
| 7399 | /*---------------------------------------------------------------------------*/ |
| 7400 | /* Routine Name: ips_init_phase2 */ |
| 7401 | /* */ |
| 7402 | /* Routine Description: */ |
| 7403 | /* Adapter Initialization Phase 2 */ |
| 7404 | /* */ |
| 7405 | /* Return Value: */ |
| 7406 | /* 0 if Successful, else non-zero */ |
| 7407 | /*---------------------------------------------------------------------------*/ |
| 7408 | static int |
| 7409 | ips_init_phase2(int index) |
| 7410 | { |
| 7411 | ips_ha_t *ha; |
| 7412 | |
| 7413 | ha = ips_ha[index]; |
| 7414 | |
| 7415 | METHOD_TRACE("ips_init_phase2", 1); |
| 7416 | if (!ha->active) { |
| 7417 | ips_ha[index] = NULL; |
| 7418 | return -1; |
| 7419 | } |
| 7420 | |
| 7421 | /* Install the interrupt handler */ |
| 7422 | if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) { |
| 7423 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 7424 | "Unable to install interrupt handler\n"); |
| 7425 | return ips_abort_init(ha, index); |
| 7426 | } |
| 7427 | |
| 7428 | /* |
| 7429 | * Allocate a temporary SCB for initialization |
| 7430 | */ |
| 7431 | ha->max_cmds = 1; |
| 7432 | if (!ips_allocatescbs(ha)) { |
| 7433 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 7434 | "Unable to allocate a CCB\n"); |
| 7435 | free_irq(ha->irq, ha); |
| 7436 | return ips_abort_init(ha, index); |
| 7437 | } |
| 7438 | |
| 7439 | if (!ips_hainit(ha)) { |
| 7440 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 7441 | "Unable to initialize controller\n"); |
| 7442 | free_irq(ha->irq, ha); |
| 7443 | return ips_abort_init(ha, index); |
| 7444 | } |
| 7445 | /* Free the temporary SCB */ |
| 7446 | ips_deallocatescbs(ha, 1); |
| 7447 | |
| 7448 | /* allocate CCBs */ |
| 7449 | if (!ips_allocatescbs(ha)) { |
| 7450 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
| 7451 | "Unable to allocate CCBs\n"); |
| 7452 | free_irq(ha->irq, ha); |
| 7453 | return ips_abort_init(ha, index); |
| 7454 | } |
| 7455 | |
| 7456 | return SUCCESS; |
| 7457 | } |
| 7458 | |
| 7459 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9) |
| 7460 | MODULE_LICENSE("GPL"); |
| 7461 | #endif |
| 7462 | |
| 7463 | MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); |
| 7464 | |
| 7465 | #ifdef MODULE_VERSION |
| 7466 | MODULE_VERSION(IPS_VER_STRING); |
| 7467 | #endif |
| 7468 | |
| 7469 | |
| 7470 | /* |
| 7471 | * Overrides for Emacs so that we almost follow Linus's tabbing style. |
| 7472 | * Emacs will notice this stuff at the end of the file and automatically |
| 7473 | * adjust the settings for this buffer only. This must remain at the end |
| 7474 | * of the file. |
| 7475 | * --------------------------------------------------------------------------- |
| 7476 | * Local variables: |
| 7477 | * c-indent-level: 2 |
| 7478 | * c-brace-imaginary-offset: 0 |
| 7479 | * c-brace-offset: -2 |
| 7480 | * c-argdecl-indent: 2 |
| 7481 | * c-label-offset: -2 |
| 7482 | * c-continued-statement-offset: 2 |
| 7483 | * c-continued-brace-offset: 0 |
| 7484 | * indent-tabs-mode: nil |
| 7485 | * tab-width: 8 |
| 7486 | * End: |
| 7487 | */ |