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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef _IOAT_REGISTERS_H_
22#define _IOAT_REGISTERS_H_
23
24
25/* MMIO Device Registers */
26#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
27
28#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
29#define IOAT_XFERCAP_4KB 12
30#define IOAT_XFERCAP_8KB 13
31#define IOAT_XFERCAP_16KB 14
32#define IOAT_XFERCAP_32KB 15
33#define IOAT_XFERCAP_32GB 0
34
35#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
36#define IOAT_GENCTRL_DEBUG_EN 0x01
37
38#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
39#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
40#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
41#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
42
43#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
44
45#define IOAT_VER_OFFSET 0x08 /* 8-bit */
46#define IOAT_VER_MAJOR_MASK 0xF0
47#define IOAT_VER_MINOR_MASK 0x0F
48#define GET_IOAT_VER_MAJOR(x) ((x) & IOAT_VER_MAJOR_MASK)
49#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
50
51#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
52
53#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
54#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */
55#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalesing Supported */
56
57#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
58#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
59
60
61#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
62
63/* DMA Channel Registers */
64#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
65#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
66#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
67#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
68#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
69#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
70#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
71#define IOAT_CHANCTRL_INT_DISABLE 0x0001
72
73#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatability */
74#define IOAT_DMA_COMP_V1 0x0001 /* Compatability with DMA version 1 */
75
76#define IOAT_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
77#define IOAT_CHANSTS_OFFSET_LOW 0x04
78#define IOAT_CHANSTS_OFFSET_HIGH 0x08
Randy Dunlapc1b4df52006-07-03 19:24:19 -070079#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR 0xFFFFFFFFFFFFFFC0UL
Chris Leech0bbd5f42006-05-23 17:35:34 -070080#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
81#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
82#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
83#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1
84#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2
85#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
86
87#define IOAT_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
88#define IOAT_CHAINADDR_OFFSET_LOW 0x0C
89#define IOAT_CHAINADDR_OFFSET_HIGH 0x10
90
91#define IOAT_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
92#define IOAT_CHANCMD_RESET 0x20
93#define IOAT_CHANCMD_RESUME 0x10
94#define IOAT_CHANCMD_ABORT 0x08
95#define IOAT_CHANCMD_SUSPEND 0x04
96#define IOAT_CHANCMD_APPEND 0x02
97#define IOAT_CHANCMD_START 0x01
98
99#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
100#define IOAT_CHANCMP_OFFSET_LOW 0x18
101#define IOAT_CHANCMP_OFFSET_HIGH 0x1C
102
103#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
104#define IOAT_CDAR_OFFSET_LOW 0x20
105#define IOAT_CDAR_OFFSET_HIGH 0x24
106
107#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
108#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001
109#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
110#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004
111#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008
112#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
113#define IOAT_CHANERR_CHANCMD_ERR 0x0020
114#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
115#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
116#define IOAT_CHANERR_READ_DATA_ERR 0x0100
117#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
118#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400
119#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800
120#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
121#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
122#define IOAT_CHANERR_SOFT_ERR 0x4000
123
124#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
125
126#endif /* _IOAT_REGISTERS_H_ */