Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/console.h> |
| 29 | #include <drm/drmP.h> |
| 30 | #include <drm/drm_crtc_helper.h> |
| 31 | #include <drm/radeon_drm.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame^] | 32 | #include <linux/vgaarb.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 33 | #include "radeon_reg.h" |
| 34 | #include "radeon.h" |
| 35 | #include "radeon_asic.h" |
| 36 | #include "atom.h" |
| 37 | |
| 38 | /* |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 39 | * Clear GPU surface registers. |
| 40 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 41 | void radeon_surface_init(struct radeon_device *rdev) |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 42 | { |
| 43 | /* FIXME: check this out */ |
| 44 | if (rdev->family < CHIP_R600) { |
| 45 | int i; |
| 46 | |
| 47 | for (i = 0; i < 8; i++) { |
| 48 | WREG32(RADEON_SURFACE0_INFO + |
| 49 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
| 50 | 0); |
| 51 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 52 | /* enable surfaces */ |
| 53 | WREG32(RADEON_SURFACE_CNTL, 0); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 54 | } |
| 55 | } |
| 56 | |
| 57 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 58 | * GPU scratch registers helpers function. |
| 59 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 60 | void radeon_scratch_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 61 | { |
| 62 | int i; |
| 63 | |
| 64 | /* FIXME: check this out */ |
| 65 | if (rdev->family < CHIP_R300) { |
| 66 | rdev->scratch.num_reg = 5; |
| 67 | } else { |
| 68 | rdev->scratch.num_reg = 7; |
| 69 | } |
| 70 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 71 | rdev->scratch.free[i] = true; |
| 72 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
| 77 | { |
| 78 | int i; |
| 79 | |
| 80 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 81 | if (rdev->scratch.free[i]) { |
| 82 | rdev->scratch.free[i] = false; |
| 83 | *reg = rdev->scratch.reg[i]; |
| 84 | return 0; |
| 85 | } |
| 86 | } |
| 87 | return -EINVAL; |
| 88 | } |
| 89 | |
| 90 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
| 91 | { |
| 92 | int i; |
| 93 | |
| 94 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 95 | if (rdev->scratch.reg[i] == reg) { |
| 96 | rdev->scratch.free[i] = true; |
| 97 | return; |
| 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * MC common functions |
| 104 | */ |
| 105 | int radeon_mc_setup(struct radeon_device *rdev) |
| 106 | { |
| 107 | uint32_t tmp; |
| 108 | |
| 109 | /* Some chips have an "issue" with the memory controller, the |
| 110 | * location must be aligned to the size. We just align it down, |
| 111 | * too bad if we walk over the top of system memory, we don't |
| 112 | * use DMA without a remapped anyway. |
| 113 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
| 114 | */ |
| 115 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
| 116 | */ |
| 117 | /* |
| 118 | * Note: from R6xx the address space is 40bits but here we only |
| 119 | * use 32bits (still have to see a card which would exhaust 4G |
| 120 | * address space). |
| 121 | */ |
| 122 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
| 123 | /* vram location was already setup try to put gtt after |
| 124 | * if it fits */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 125 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 126 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
| 127 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
| 128 | rdev->mc.gtt_location = tmp; |
| 129 | } else { |
| 130 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
| 131 | printk(KERN_ERR "[drm] GTT too big to fit " |
| 132 | "before or after vram location.\n"); |
| 133 | return -EINVAL; |
| 134 | } |
| 135 | rdev->mc.gtt_location = 0; |
| 136 | } |
| 137 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
| 138 | /* gtt location was already setup try to put vram before |
| 139 | * if it fits */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 140 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | rdev->mc.vram_location = 0; |
| 142 | } else { |
| 143 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 144 | tmp += (rdev->mc.mc_vram_size - 1); |
| 145 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
| 146 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 147 | rdev->mc.vram_location = tmp; |
| 148 | } else { |
| 149 | printk(KERN_ERR "[drm] vram too big to fit " |
| 150 | "before or after GTT location.\n"); |
| 151 | return -EINVAL; |
| 152 | } |
| 153 | } |
| 154 | } else { |
| 155 | rdev->mc.vram_location = 0; |
Dave Airlie | 1733292 | 2009-08-07 11:03:26 +1000 | [diff] [blame] | 156 | tmp = rdev->mc.mc_vram_size; |
| 157 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
| 158 | rdev->mc.gtt_location = tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | } |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 160 | rdev->mc.vram_start = rdev->mc.vram_location; |
| 161 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| 162 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
| 163 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 164 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 165 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 166 | (unsigned)rdev->mc.vram_location, |
| 167 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
| 168 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 170 | (unsigned)rdev->mc.gtt_location, |
| 171 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | |
| 176 | /* |
| 177 | * GPU helpers function. |
| 178 | */ |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 179 | bool radeon_card_posted(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | { |
| 181 | uint32_t reg; |
| 182 | |
| 183 | /* first check CRTCs */ |
| 184 | if (ASIC_IS_AVIVO(rdev)) { |
| 185 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
| 186 | RREG32(AVIVO_D2CRTC_CONTROL); |
| 187 | if (reg & AVIVO_CRTC_EN) { |
| 188 | return true; |
| 189 | } |
| 190 | } else { |
| 191 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
| 192 | RREG32(RADEON_CRTC2_GEN_CNTL); |
| 193 | if (reg & RADEON_CRTC_EN) { |
| 194 | return true; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | /* then check MEM_SIZE, in case the crtcs are off */ |
| 199 | if (rdev->family >= CHIP_R600) |
| 200 | reg = RREG32(R600_CONFIG_MEMSIZE); |
| 201 | else |
| 202 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
| 203 | |
| 204 | if (reg) |
| 205 | return true; |
| 206 | |
| 207 | return false; |
| 208 | |
| 209 | } |
| 210 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 211 | int radeon_dummy_page_init(struct radeon_device *rdev) |
| 212 | { |
| 213 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
| 214 | if (rdev->dummy_page.page == NULL) |
| 215 | return -ENOMEM; |
| 216 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
| 217 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 218 | if (!rdev->dummy_page.addr) { |
| 219 | __free_page(rdev->dummy_page.page); |
| 220 | rdev->dummy_page.page = NULL; |
| 221 | return -ENOMEM; |
| 222 | } |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
| 227 | { |
| 228 | if (rdev->dummy_page.page == NULL) |
| 229 | return; |
| 230 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, |
| 231 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 232 | __free_page(rdev->dummy_page.page); |
| 233 | rdev->dummy_page.page = NULL; |
| 234 | } |
| 235 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 236 | |
| 237 | /* |
| 238 | * Registers accessors functions. |
| 239 | */ |
| 240 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
| 241 | { |
| 242 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
| 243 | BUG_ON(1); |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 248 | { |
| 249 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
| 250 | reg, v); |
| 251 | BUG_ON(1); |
| 252 | } |
| 253 | |
| 254 | void radeon_register_accessor_init(struct radeon_device *rdev) |
| 255 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | rdev->mc_rreg = &radeon_invalid_rreg; |
| 257 | rdev->mc_wreg = &radeon_invalid_wreg; |
| 258 | rdev->pll_rreg = &radeon_invalid_rreg; |
| 259 | rdev->pll_wreg = &radeon_invalid_wreg; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | rdev->pciep_rreg = &radeon_invalid_rreg; |
| 261 | rdev->pciep_wreg = &radeon_invalid_wreg; |
| 262 | |
| 263 | /* Don't change order as we are overridding accessor. */ |
| 264 | if (rdev->family < CHIP_RV515) { |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 265 | rdev->pcie_reg_mask = 0xff; |
| 266 | } else { |
| 267 | rdev->pcie_reg_mask = 0x7ff; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | } |
| 269 | /* FIXME: not sure here */ |
| 270 | if (rdev->family <= CHIP_R580) { |
| 271 | rdev->pll_rreg = &r100_pll_rreg; |
| 272 | rdev->pll_wreg = &r100_pll_wreg; |
| 273 | } |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 274 | if (rdev->family >= CHIP_R420) { |
| 275 | rdev->mc_rreg = &r420_mc_rreg; |
| 276 | rdev->mc_wreg = &r420_mc_wreg; |
| 277 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 278 | if (rdev->family >= CHIP_RV515) { |
| 279 | rdev->mc_rreg = &rv515_mc_rreg; |
| 280 | rdev->mc_wreg = &rv515_mc_wreg; |
| 281 | } |
| 282 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| 283 | rdev->mc_rreg = &rs400_mc_rreg; |
| 284 | rdev->mc_wreg = &rs400_mc_wreg; |
| 285 | } |
| 286 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| 287 | rdev->mc_rreg = &rs690_mc_rreg; |
| 288 | rdev->mc_wreg = &rs690_mc_wreg; |
| 289 | } |
| 290 | if (rdev->family == CHIP_RS600) { |
| 291 | rdev->mc_rreg = &rs600_mc_rreg; |
| 292 | rdev->mc_wreg = &rs600_mc_wreg; |
| 293 | } |
| 294 | if (rdev->family >= CHIP_R600) { |
| 295 | rdev->pciep_rreg = &r600_pciep_rreg; |
| 296 | rdev->pciep_wreg = &r600_pciep_wreg; |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | |
| 301 | /* |
| 302 | * ASIC |
| 303 | */ |
| 304 | int radeon_asic_init(struct radeon_device *rdev) |
| 305 | { |
| 306 | radeon_register_accessor_init(rdev); |
| 307 | switch (rdev->family) { |
| 308 | case CHIP_R100: |
| 309 | case CHIP_RV100: |
| 310 | case CHIP_RS100: |
| 311 | case CHIP_RV200: |
| 312 | case CHIP_RS200: |
| 313 | case CHIP_R200: |
| 314 | case CHIP_RV250: |
| 315 | case CHIP_RS300: |
| 316 | case CHIP_RV280: |
| 317 | rdev->asic = &r100_asic; |
| 318 | break; |
| 319 | case CHIP_R300: |
| 320 | case CHIP_R350: |
| 321 | case CHIP_RV350: |
| 322 | case CHIP_RV380: |
| 323 | rdev->asic = &r300_asic; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 324 | if (rdev->flags & RADEON_IS_PCIE) { |
| 325 | rdev->asic->gart_init = &rv370_pcie_gart_init; |
| 326 | rdev->asic->gart_fini = &rv370_pcie_gart_fini; |
| 327 | rdev->asic->gart_enable = &rv370_pcie_gart_enable; |
| 328 | rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
| 329 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 330 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| 331 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 332 | break; |
| 333 | case CHIP_R420: |
| 334 | case CHIP_R423: |
| 335 | case CHIP_RV410: |
| 336 | rdev->asic = &r420_asic; |
| 337 | break; |
| 338 | case CHIP_RS400: |
| 339 | case CHIP_RS480: |
| 340 | rdev->asic = &rs400_asic; |
| 341 | break; |
| 342 | case CHIP_RS600: |
| 343 | rdev->asic = &rs600_asic; |
| 344 | break; |
| 345 | case CHIP_RS690: |
| 346 | case CHIP_RS740: |
| 347 | rdev->asic = &rs690_asic; |
| 348 | break; |
| 349 | case CHIP_RV515: |
| 350 | rdev->asic = &rv515_asic; |
| 351 | break; |
| 352 | case CHIP_R520: |
| 353 | case CHIP_RV530: |
| 354 | case CHIP_RV560: |
| 355 | case CHIP_RV570: |
| 356 | case CHIP_R580: |
| 357 | rdev->asic = &r520_asic; |
| 358 | break; |
| 359 | case CHIP_R600: |
| 360 | case CHIP_RV610: |
| 361 | case CHIP_RV630: |
| 362 | case CHIP_RV620: |
| 363 | case CHIP_RV635: |
| 364 | case CHIP_RV670: |
| 365 | case CHIP_RS780: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 366 | case CHIP_RS880: |
| 367 | rdev->asic = &r600_asic; |
| 368 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | case CHIP_RV770: |
| 370 | case CHIP_RV730: |
| 371 | case CHIP_RV710: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 372 | case CHIP_RV740: |
| 373 | rdev->asic = &rv770_asic; |
| 374 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 375 | default: |
| 376 | /* FIXME: not supported yet */ |
| 377 | return -EINVAL; |
| 378 | } |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | |
| 383 | /* |
| 384 | * Wrapper around modesetting bits. |
| 385 | */ |
| 386 | int radeon_clocks_init(struct radeon_device *rdev) |
| 387 | { |
| 388 | int r; |
| 389 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 390 | r = radeon_static_clocks_init(rdev->ddev); |
| 391 | if (r) { |
| 392 | return r; |
| 393 | } |
| 394 | DRM_INFO("Clocks initialized !\n"); |
| 395 | return 0; |
| 396 | } |
| 397 | |
| 398 | void radeon_clocks_fini(struct radeon_device *rdev) |
| 399 | { |
| 400 | } |
| 401 | |
| 402 | /* ATOM accessor methods */ |
| 403 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
| 404 | { |
| 405 | struct radeon_device *rdev = info->dev->dev_private; |
| 406 | uint32_t r; |
| 407 | |
| 408 | r = rdev->pll_rreg(rdev, reg); |
| 409 | return r; |
| 410 | } |
| 411 | |
| 412 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 413 | { |
| 414 | struct radeon_device *rdev = info->dev->dev_private; |
| 415 | |
| 416 | rdev->pll_wreg(rdev, reg, val); |
| 417 | } |
| 418 | |
| 419 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
| 420 | { |
| 421 | struct radeon_device *rdev = info->dev->dev_private; |
| 422 | uint32_t r; |
| 423 | |
| 424 | r = rdev->mc_rreg(rdev, reg); |
| 425 | return r; |
| 426 | } |
| 427 | |
| 428 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 429 | { |
| 430 | struct radeon_device *rdev = info->dev->dev_private; |
| 431 | |
| 432 | rdev->mc_wreg(rdev, reg, val); |
| 433 | } |
| 434 | |
| 435 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 436 | { |
| 437 | struct radeon_device *rdev = info->dev->dev_private; |
| 438 | |
| 439 | WREG32(reg*4, val); |
| 440 | } |
| 441 | |
| 442 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
| 443 | { |
| 444 | struct radeon_device *rdev = info->dev->dev_private; |
| 445 | uint32_t r; |
| 446 | |
| 447 | r = RREG32(reg*4); |
| 448 | return r; |
| 449 | } |
| 450 | |
| 451 | static struct card_info atom_card_info = { |
| 452 | .dev = NULL, |
| 453 | .reg_read = cail_reg_read, |
| 454 | .reg_write = cail_reg_write, |
| 455 | .mc_read = cail_mc_read, |
| 456 | .mc_write = cail_mc_write, |
| 457 | .pll_read = cail_pll_read, |
| 458 | .pll_write = cail_pll_write, |
| 459 | }; |
| 460 | |
| 461 | int radeon_atombios_init(struct radeon_device *rdev) |
| 462 | { |
| 463 | atom_card_info.dev = rdev->ddev; |
| 464 | rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); |
| 465 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
| 466 | return 0; |
| 467 | } |
| 468 | |
| 469 | void radeon_atombios_fini(struct radeon_device *rdev) |
| 470 | { |
| 471 | kfree(rdev->mode_info.atom_context); |
| 472 | } |
| 473 | |
| 474 | int radeon_combios_init(struct radeon_device *rdev) |
| 475 | { |
| 476 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | void radeon_combios_fini(struct radeon_device *rdev) |
| 481 | { |
| 482 | } |
| 483 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame^] | 484 | /* if we get transitioned to only one device, tak VGA back */ |
| 485 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
| 486 | { |
| 487 | struct radeon_device *rdev = cookie; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame^] | 489 | radeon_vga_set_state(rdev, state); |
| 490 | if (state) |
| 491 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 492 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 493 | else |
| 494 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 495 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 496 | /* |
| 497 | * Radeon device. |
| 498 | */ |
| 499 | int radeon_device_init(struct radeon_device *rdev, |
| 500 | struct drm_device *ddev, |
| 501 | struct pci_dev *pdev, |
| 502 | uint32_t flags) |
| 503 | { |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 504 | int r; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 505 | int dma_bits; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 506 | |
| 507 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
| 508 | rdev->shutdown = false; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 509 | rdev->dev = &pdev->dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 510 | rdev->ddev = ddev; |
| 511 | rdev->pdev = pdev; |
| 512 | rdev->flags = flags; |
| 513 | rdev->family = flags & RADEON_FAMILY_MASK; |
| 514 | rdev->is_atom_bios = false; |
| 515 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
| 516 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 517 | rdev->gpu_lockup = false; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 518 | rdev->accel_working = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 519 | /* mutex initialization are all done here so we |
| 520 | * can recall function without having locking issues */ |
| 521 | mutex_init(&rdev->cs_mutex); |
| 522 | mutex_init(&rdev->ib_pool.mutex); |
| 523 | mutex_init(&rdev->cp.mutex); |
| 524 | rwlock_init(&rdev->fence_drv.lock); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 525 | INIT_LIST_HEAD(&rdev->gem.objects); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 526 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 527 | /* Set asic functions */ |
| 528 | r = radeon_asic_init(rdev); |
| 529 | if (r) { |
| 530 | return r; |
| 531 | } |
| 532 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 533 | if (radeon_agpmode == -1) { |
| 534 | rdev->flags &= ~RADEON_IS_AGP; |
Jerome Glisse | c000273 | 2009-09-10 13:47:09 +0200 | [diff] [blame] | 535 | if (rdev->family >= CHIP_RV515 || |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 536 | rdev->family == CHIP_RV380 || |
| 537 | rdev->family == CHIP_RV410 || |
| 538 | rdev->family == CHIP_R423) { |
| 539 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 540 | rdev->flags |= RADEON_IS_PCIE; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 541 | rdev->asic->gart_init = &rv370_pcie_gart_init; |
| 542 | rdev->asic->gart_fini = &rv370_pcie_gart_fini; |
| 543 | rdev->asic->gart_enable = &rv370_pcie_gart_enable; |
| 544 | rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
| 545 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 546 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 547 | } else { |
| 548 | DRM_INFO("Forcing AGP to PCI mode\n"); |
| 549 | rdev->flags |= RADEON_IS_PCI; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 550 | rdev->asic->gart_init = &r100_pci_gart_init; |
| 551 | rdev->asic->gart_fini = &r100_pci_gart_fini; |
| 552 | rdev->asic->gart_enable = &r100_pci_gart_enable; |
| 553 | rdev->asic->gart_disable = &r100_pci_gart_disable; |
| 554 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
| 555 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 556 | } |
| 557 | } |
| 558 | |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 559 | /* set DMA mask + need_dma32 flags. |
| 560 | * PCIE - can handle 40-bits. |
| 561 | * IGP - can handle 40-bits (in theory) |
| 562 | * AGP - generally dma32 is safest |
| 563 | * PCI - only dma32 |
| 564 | */ |
| 565 | rdev->need_dma32 = false; |
| 566 | if (rdev->flags & RADEON_IS_AGP) |
| 567 | rdev->need_dma32 = true; |
| 568 | if (rdev->flags & RADEON_IS_PCI) |
| 569 | rdev->need_dma32 = true; |
| 570 | |
| 571 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| 572 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 573 | if (r) { |
| 574 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
| 575 | } |
| 576 | |
| 577 | /* Registers mapping */ |
| 578 | /* TODO: block userspace mapping of io register */ |
| 579 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); |
| 580 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); |
| 581 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
| 582 | if (rdev->rmmio == NULL) { |
| 583 | return -ENOMEM; |
| 584 | } |
| 585 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| 586 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| 587 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 588 | rdev->new_init_path = false; |
| 589 | r = radeon_init(rdev); |
| 590 | if (r) { |
| 591 | return r; |
| 592 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame^] | 593 | |
| 594 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
| 595 | r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
| 596 | if (r) { |
| 597 | return -EINVAL; |
| 598 | } |
| 599 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 600 | if (!rdev->new_init_path) { |
| 601 | /* Setup errata flags */ |
| 602 | radeon_errata(rdev); |
| 603 | /* Initialize scratch registers */ |
| 604 | radeon_scratch_init(rdev); |
| 605 | /* Initialize surface registers */ |
| 606 | radeon_surface_init(rdev); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 607 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 608 | /* BIOS*/ |
| 609 | if (!radeon_get_bios(rdev)) { |
| 610 | if (ASIC_IS_AVIVO(rdev)) |
| 611 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 612 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 613 | if (rdev->is_atom_bios) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 614 | r = radeon_atombios_init(rdev); |
| 615 | if (r) { |
| 616 | return r; |
| 617 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 618 | } else { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 619 | r = radeon_combios_init(rdev); |
| 620 | if (r) { |
| 621 | return r; |
| 622 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 623 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 624 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 625 | if (radeon_gpu_reset(rdev)) { |
| 626 | /* FIXME: what do we want to do here ? */ |
| 627 | } |
| 628 | /* check if cards are posted or not */ |
| 629 | if (!radeon_card_posted(rdev) && rdev->bios) { |
| 630 | DRM_INFO("GPU not posted. posting now...\n"); |
| 631 | if (rdev->is_atom_bios) { |
| 632 | atom_asic_init(rdev->mode_info.atom_context); |
| 633 | } else { |
| 634 | radeon_combios_asic_init(rdev->ddev); |
| 635 | } |
| 636 | } |
Michel Dänzer | 5e6dde7 | 2009-09-17 09:42:28 +0200 | [diff] [blame] | 637 | /* Get clock & vram information */ |
| 638 | radeon_get_clock_info(rdev->ddev); |
Michel Dänzer | 95a8f1b | 2009-09-15 17:09:26 +0200 | [diff] [blame] | 639 | radeon_vram_info(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 640 | /* Initialize clocks */ |
| 641 | r = radeon_clocks_init(rdev); |
| 642 | if (r) { |
| 643 | return r; |
| 644 | } |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 645 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 646 | /* Initialize memory controller (also test AGP) */ |
| 647 | r = radeon_mc_init(rdev); |
| 648 | if (r) { |
| 649 | return r; |
| 650 | } |
| 651 | /* Fence driver */ |
| 652 | r = radeon_fence_driver_init(rdev); |
| 653 | if (r) { |
| 654 | return r; |
| 655 | } |
| 656 | r = radeon_irq_kms_init(rdev); |
| 657 | if (r) { |
| 658 | return r; |
| 659 | } |
| 660 | /* Memory manager */ |
| 661 | r = radeon_object_init(rdev); |
| 662 | if (r) { |
| 663 | return r; |
| 664 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 665 | r = radeon_gpu_gart_init(rdev); |
| 666 | if (r) |
| 667 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 668 | /* Initialize GART (initialize after TTM so we can allocate |
| 669 | * memory through TTM but finalize after TTM) */ |
| 670 | r = radeon_gart_enable(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 671 | if (r) |
| 672 | return 0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 673 | r = radeon_gem_init(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 674 | if (r) |
| 675 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 676 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 677 | /* 1M ring buffer */ |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 678 | r = radeon_cp_init(rdev, 1024 * 1024); |
| 679 | if (r) |
| 680 | return 0; |
| 681 | r = radeon_wb_init(rdev); |
| 682 | if (r) |
| 683 | DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
| 684 | r = radeon_ib_pool_init(rdev); |
| 685 | if (r) |
| 686 | return 0; |
| 687 | r = radeon_ib_test(rdev); |
| 688 | if (r) |
| 689 | return 0; |
| 690 | rdev->accel_working = true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 691 | } |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 692 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 693 | if (radeon_testing) { |
| 694 | radeon_test_moves(rdev); |
| 695 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 696 | if (radeon_benchmarking) { |
| 697 | radeon_benchmark(rdev); |
| 698 | } |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 699 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | void radeon_device_fini(struct radeon_device *rdev) |
| 703 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 704 | DRM_INFO("radeon: finishing device.\n"); |
| 705 | rdev->shutdown = true; |
| 706 | /* Order matter so becarefull if you rearrange anythings */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 707 | if (!rdev->new_init_path) { |
| 708 | radeon_ib_pool_fini(rdev); |
| 709 | radeon_cp_fini(rdev); |
| 710 | radeon_wb_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 711 | radeon_gpu_gart_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 712 | radeon_gem_fini(rdev); |
| 713 | radeon_mc_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 714 | #if __OS_HAS_AGP |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 715 | radeon_agp_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 716 | #endif |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 717 | radeon_irq_kms_fini(rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame^] | 718 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 719 | radeon_fence_driver_fini(rdev); |
| 720 | radeon_clocks_fini(rdev); |
| 721 | radeon_object_fini(rdev); |
| 722 | if (rdev->is_atom_bios) { |
| 723 | radeon_atombios_fini(rdev); |
| 724 | } else { |
| 725 | radeon_combios_fini(rdev); |
| 726 | } |
| 727 | kfree(rdev->bios); |
| 728 | rdev->bios = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 729 | } else { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 730 | radeon_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 731 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 732 | iounmap(rdev->rmmio); |
| 733 | rdev->rmmio = NULL; |
| 734 | } |
| 735 | |
| 736 | |
| 737 | /* |
| 738 | * Suspend & resume. |
| 739 | */ |
| 740 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) |
| 741 | { |
| 742 | struct radeon_device *rdev = dev->dev_private; |
| 743 | struct drm_crtc *crtc; |
| 744 | |
| 745 | if (dev == NULL || rdev == NULL) { |
| 746 | return -ENODEV; |
| 747 | } |
| 748 | if (state.event == PM_EVENT_PRETHAW) { |
| 749 | return 0; |
| 750 | } |
| 751 | /* unpin the front buffers */ |
| 752 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 753 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); |
| 754 | struct radeon_object *robj; |
| 755 | |
| 756 | if (rfb == NULL || rfb->obj == NULL) { |
| 757 | continue; |
| 758 | } |
| 759 | robj = rfb->obj->driver_private; |
| 760 | if (robj != rdev->fbdev_robj) { |
| 761 | radeon_object_unpin(robj); |
| 762 | } |
| 763 | } |
| 764 | /* evict vram memory */ |
| 765 | radeon_object_evict_vram(rdev); |
| 766 | /* wait for gpu to finish processing current batch */ |
| 767 | radeon_fence_wait_last(rdev); |
| 768 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 769 | radeon_save_bios_scratch_regs(rdev); |
| 770 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 771 | if (!rdev->new_init_path) { |
| 772 | radeon_cp_disable(rdev); |
| 773 | radeon_gart_disable(rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 774 | rdev->irq.sw_int = false; |
| 775 | radeon_irq_set(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 776 | } else { |
| 777 | radeon_suspend(rdev); |
| 778 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 779 | /* evict remaining vram memory */ |
| 780 | radeon_object_evict_vram(rdev); |
| 781 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 782 | pci_save_state(dev->pdev); |
| 783 | if (state.event == PM_EVENT_SUSPEND) { |
| 784 | /* Shut down the device */ |
| 785 | pci_disable_device(dev->pdev); |
| 786 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 787 | } |
| 788 | acquire_console_sem(); |
| 789 | fb_set_suspend(rdev->fbdev_info, 1); |
| 790 | release_console_sem(); |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | int radeon_resume_kms(struct drm_device *dev) |
| 795 | { |
| 796 | struct radeon_device *rdev = dev->dev_private; |
| 797 | int r; |
| 798 | |
| 799 | acquire_console_sem(); |
| 800 | pci_set_power_state(dev->pdev, PCI_D0); |
| 801 | pci_restore_state(dev->pdev); |
| 802 | if (pci_enable_device(dev->pdev)) { |
| 803 | release_console_sem(); |
| 804 | return -1; |
| 805 | } |
| 806 | pci_set_master(dev->pdev); |
| 807 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 808 | if (!rdev->new_init_path) { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 809 | if (radeon_gpu_reset(rdev)) { |
| 810 | /* FIXME: what do we want to do here ? */ |
| 811 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 812 | /* post card */ |
| 813 | if (rdev->is_atom_bios) { |
| 814 | atom_asic_init(rdev->mode_info.atom_context); |
| 815 | } else { |
| 816 | radeon_combios_asic_init(rdev->ddev); |
| 817 | } |
| 818 | /* Initialize clocks */ |
| 819 | r = radeon_clocks_init(rdev); |
| 820 | if (r) { |
| 821 | release_console_sem(); |
| 822 | return r; |
| 823 | } |
| 824 | /* Enable IRQ */ |
| 825 | rdev->irq.sw_int = true; |
| 826 | radeon_irq_set(rdev); |
| 827 | /* Initialize GPU Memory Controller */ |
| 828 | r = radeon_mc_init(rdev); |
| 829 | if (r) { |
| 830 | goto out; |
| 831 | } |
| 832 | r = radeon_gart_enable(rdev); |
| 833 | if (r) { |
| 834 | goto out; |
| 835 | } |
| 836 | r = radeon_cp_init(rdev, rdev->cp.ring_size); |
| 837 | if (r) { |
| 838 | goto out; |
| 839 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 840 | } else { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 841 | radeon_resume(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 842 | } |
| 843 | out: |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 844 | radeon_restore_bios_scratch_regs(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 845 | fb_set_suspend(rdev->fbdev_info, 0); |
| 846 | release_console_sem(); |
| 847 | |
| 848 | /* blat the mode back in */ |
| 849 | drm_helper_resume_force_mode(dev); |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | |
| 854 | /* |
| 855 | * Debugfs |
| 856 | */ |
| 857 | struct radeon_debugfs { |
| 858 | struct drm_info_list *files; |
| 859 | unsigned num_files; |
| 860 | }; |
| 861 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; |
| 862 | static unsigned _radeon_debugfs_count = 0; |
| 863 | |
| 864 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 865 | struct drm_info_list *files, |
| 866 | unsigned nfiles) |
| 867 | { |
| 868 | unsigned i; |
| 869 | |
| 870 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 871 | if (_radeon_debugfs[i].files == files) { |
| 872 | /* Already registered */ |
| 873 | return 0; |
| 874 | } |
| 875 | } |
| 876 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { |
| 877 | DRM_ERROR("Reached maximum number of debugfs files.\n"); |
| 878 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); |
| 879 | return -EINVAL; |
| 880 | } |
| 881 | _radeon_debugfs[_radeon_debugfs_count].files = files; |
| 882 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; |
| 883 | _radeon_debugfs_count++; |
| 884 | #if defined(CONFIG_DEBUG_FS) |
| 885 | drm_debugfs_create_files(files, nfiles, |
| 886 | rdev->ddev->control->debugfs_root, |
| 887 | rdev->ddev->control); |
| 888 | drm_debugfs_create_files(files, nfiles, |
| 889 | rdev->ddev->primary->debugfs_root, |
| 890 | rdev->ddev->primary); |
| 891 | #endif |
| 892 | return 0; |
| 893 | } |
| 894 | |
| 895 | #if defined(CONFIG_DEBUG_FS) |
| 896 | int radeon_debugfs_init(struct drm_minor *minor) |
| 897 | { |
| 898 | return 0; |
| 899 | } |
| 900 | |
| 901 | void radeon_debugfs_cleanup(struct drm_minor *minor) |
| 902 | { |
| 903 | unsigned i; |
| 904 | |
| 905 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 906 | drm_debugfs_remove_files(_radeon_debugfs[i].files, |
| 907 | _radeon_debugfs[i].num_files, minor); |
| 908 | } |
| 909 | } |
| 910 | #endif |