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gerrit-public.fairphone.software / kernel / msm / 2b48716d1d2f2edb1e7cbc5ecf1cb2cb39373e33 / . / arch / ppc / platforms / radstone_ppc7d.h
blob: 938375510be48bdf4ea13bcfce9bfd0aa170459c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * arch/ppc/platforms/radstone_ppc7d.h
3 *
4 * Board definitions for the Radstone PPC7D boards.
5 *
6 * Author: James Chapman <jchapman@katalix.com>
7 *
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
19 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
20 * We'll only use one PCI MEM window on each PCI bus.
21 *
22 * This is the CPU physical memory map (windows must be at least 1MB
23 * and start on a boundary that is a multiple of the window size):
24 *
25 * 0xff800000-0xffffffff - Boot window
26 * 0xff000000-0xff000fff - AFIX registers (DevCS2)
27 * 0xfef00000-0xfef0ffff - Internal MV64x60 registers
28 * 0xfef40000-0xfef7ffff - Internal SRAM
29 * 0xfef00000-0xfef0ffff - MV64360 Registers
30 * 0x70000000-0x7fffffff - soldered flash (DevCS3)
31 * 0xe8000000-0xe9ffffff - PCI I/O
32 * 0x80000000-0xbfffffff - PCI MEM
33 */
34
35#ifndef __PPC_PLATFORMS_PPC7D_H
36#define __PPC_PLATFORMS_PPC7D_H
37
38#include <asm/ppcboot.h>
39
40/*****************************************************************************
41 * CPU Physical Memory Map setup.
42 *****************************************************************************/
43
44#define PPC7D_BOOT_WINDOW_BASE 0xff800000
45#define PPC7D_AFIX_REG_BASE 0xff000000
46#define PPC7D_INTERNAL_SRAM_BASE 0xfef40000
47#define PPC7D_FLASH_BASE 0x70000000
48
49#define PPC7D_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */
50#define PPC7D_FLASH_SIZE_ACTUAL 0x10000000 /* 256MB */
51
52#define PPC7D_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \
53 PPC7D_BOOT_WINDOW_SIZE_ACTUAL)
54#define PPC7D_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \
55 PPC7D_FLASH_SIZE_ACTUAL)
56#define PPC7D_AFIX_REG_SIZE max(MV64360_WINDOW_SIZE_MIN, 0xff)
57
58
59#define PPC7D_PCI0_MEM0_START_PROC_ADDR 0x80000000UL
60#define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR 0x00000000UL
61#define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR 0x80000000UL
62#define PPC7D_PCI0_MEM0_SIZE 0x20000000UL
63#define PPC7D_PCI0_MEM1_START_PROC_ADDR 0xe8010000UL
64#define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR 0x00000000UL
65#define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR 0x00000000UL
66#define PPC7D_PCI0_MEM1_SIZE 0x000f0000UL
67#define PPC7D_PCI0_IO_START_PROC_ADDR 0xe8000000UL
68#define PPC7D_PCI0_IO_START_PCI_ADDR 0x00000000UL
69#define PPC7D_PCI0_IO_SIZE 0x00010000UL
70
71#define PPC7D_PCI1_MEM0_START_PROC_ADDR 0xa0000000UL
72#define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR 0x00000000UL
73#define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR 0xa0000000UL
74#define PPC7D_PCI1_MEM0_SIZE 0x20000000UL
75#define PPC7D_PCI1_MEM1_START_PROC_ADDR 0xe9800000UL
76#define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR 0x00000000UL
77#define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR 0x00000000UL
78#define PPC7D_PCI1_MEM1_SIZE 0x00800000UL
79#define PPC7D_PCI1_IO_START_PROC_ADDR 0xe9000000UL
80#define PPC7D_PCI1_IO_START_PCI_ADDR 0x00000000UL
81#define PPC7D_PCI1_IO_SIZE 0x00010000UL
82
83#define PPC7D_DEFAULT_BAUD 9600
84#define PPC7D_MPSC_CLK_SRC 8 /* TCLK */
85#define PPC7D_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */
86
87#define PPC7D_ETH0_PHY_ADDR 8
88#define PPC7D_ETH1_PHY_ADDR 9
89#define PPC7D_ETH2_PHY_ADDR 0
90
91#define PPC7D_ETH_TX_QUEUE_SIZE 400
92#define PPC7D_ETH_RX_QUEUE_SIZE 400
93
94#define PPC7D_ETH_PORT_CONFIG_VALUE \
95 MV64340_ETH_UNICAST_NORMAL_MODE | \
96 MV64340_ETH_DEFAULT_RX_QUEUE_0 | \
97 MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
98 MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
99 MV64340_ETH_RECEIVE_BC_IF_IP | \
100 MV64340_ETH_RECEIVE_BC_IF_ARP | \
101 MV64340_ETH_CAPTURE_TCP_FRAMES_DIS | \
102 MV64340_ETH_CAPTURE_UDP_FRAMES_DIS | \
103 MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
104 MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
105 MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0
106
107#define PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE \
108 MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
109 MV64340_ETH_PARTITION_DISABLE
110
111#define GT_ETH_IPG_INT_RX(value) \
112 ((value & 0x3fff) << 8)
113
114#define PPC7D_ETH_PORT_SDMA_CONFIG_VALUE \
115 MV64340_ETH_RX_BURST_SIZE_4_64BIT | \
116 GT_ETH_IPG_INT_RX(0) | \
117 MV64340_ETH_TX_BURST_SIZE_4_64BIT
118
119#define PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE \
120 MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
121 MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
122 MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
123 MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
124 MV64340_ETH_FORCE_BP_MODE_NO_JAM | \
125 (1 << 9) | \
126 MV64340_ETH_DO_NOT_FORCE_LINK_FAIL | \
127 MV64340_ETH_RETRANSMIT_16_ATTEMPTS | \
128 MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
129 MV64340_ETH_DTE_ADV_0 | \
130 MV64340_ETH_DISABLE_AUTO_NEG_BYPASS | \
131 MV64340_ETH_AUTO_NEG_NO_CHANGE | \
132 MV64340_ETH_MAX_RX_PACKET_9700BYTE | \
133 MV64340_ETH_CLR_EXT_LOOPBACK | \
134 MV64340_ETH_SET_FULL_DUPLEX_MODE | \
135 MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
136
137/*****************************************************************************
138 * Serial defines.
139 *****************************************************************************/
140
141#define PPC7D_SERIAL_0 0xe80003f8
142#define PPC7D_SERIAL_1 0xe80002f8
143
144#define RS_TABLE_SIZE 2
145
146/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
147#define UART_CLK 1843200
148#define BASE_BAUD ( UART_CLK / 16 )
149
150#ifdef CONFIG_SERIAL_DETECT_IRQ
151#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
152#else
153#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
154#endif
155
156#define STD_SERIAL_PORT_DFNS \
157 { 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
158 iomem_base: (u8 *)PPC7D_SERIAL_0, \
159 io_type: SERIAL_IO_MEM, }, \
160 { 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
161 iomem_base: (u8 *)PPC7D_SERIAL_1, \
162 io_type: SERIAL_IO_MEM },
163
164#define SERIAL_PORT_DFNS \
165 STD_SERIAL_PORT_DFNS
166
167/*****************************************************************************
168 * CPLD defines.
169 *
170 * Register map:-
171 *
172 * 0000 to 000F South Bridge DMA 1 Control
173 * 0020 and 0021 South Bridge Interrupt 1 Control
174 * 0040 to 0043 South Bridge Counter Control
175 * 0060 Keyboard
176 * 0061 South Bridge NMI Status and Control
177 * 0064 Keyboard
178 * 0071 and 0072 RTC R/W
179 * 0078 to 007B South Bridge BIOS Timer
180 * 0080 to 0090 South Bridge DMA Pages
181 * 00A0 and 00A1 South Bridge Interrupt 2 Control
182 * 00C0 to 00DE South Bridge DMA 2 Control
183 * 02E8 to 02EF COM6 R/W
184 * 02F8 to 02FF South Bridge COM2 R/W
185 * 03E8 to 03EF COM5 R/W
186 * 03F8 to 03FF South Bridge COM1 R/W
187 * 040A South Bridge DMA Scatter/Gather RO
188 * 040B DMA 1 Extended Mode WO
189 * 0410 to 043F South Bridge DMA Scatter/Gather
190 * 0481 to 048B South Bridge DMA High Pages
191 * 04D0 and 04D1 South Bridge Edge/Level Control
192 * 04D6 DMA 2 Extended Mode WO
193 * 0804 Memory Configuration RO
194 * 0806 Memory Configuration Extend RO
195 * 0808 SCSI Activity LED R/W
196 * 080C Equipment Present 1 RO
197 * 080E Equipment Present 2 RO
198 * 0810 Equipment Present 3 RO
199 * 0812 Equipment Present 4 RO
200 * 0818 Key Lock RO
201 * 0820 LEDS R/W
202 * 0824 COMs R/W
203 * 0826 RTS R/W
204 * 0828 Reset R/W
205 * 082C Watchdog Trig R/W
206 * 082E Interrupt R/W
207 * 0830 Interrupt Status RO
208 * 0832 PCI configuration RO
209 * 0854 Board Revision RO
210 * 0858 Extended ID RO
211 * 0864 ID Link RO
212 * 0866 Motherboard Type RO
213 * 0868 FLASH Write control RO
214 * 086A Software FLASH write protect R/W
215 * 086E FLASH Control R/W
216 *****************************************************************************/
217
218#define PPC7D_CPLD_MEM_CONFIG 0x0804
219#define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806
220#define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808
221#define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C
222#define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E
223#define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810
224#define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812
225#define PPC7D_CPLD_KEY_LOCK 0x0818
226#define PPC7D_CPLD_LEDS 0x0820
227#define PPC7D_CPLD_COMS 0x0824
228#define PPC7D_CPLD_RTS 0x0826
229#define PPC7D_CPLD_RESET 0x0828
230#define PPC7D_CPLD_WATCHDOG_TRIG 0x082C
231#define PPC7D_CPLD_INTR 0x082E
232#define PPC7D_CPLD_INTR_STATUS 0x0830
233#define PPC7D_CPLD_PCI_CONFIG 0x0832
234#define PPC7D_CPLD_BOARD_REVISION 0x0854
235#define PPC7D_CPLD_EXTENDED_ID 0x0858
236#define PPC7D_CPLD_ID_LINK 0x0864
237#define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866
238#define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868
239#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A
240#define PPC7D_CPLD_FLASH_CNTL 0x086E
241
242/* MEMORY_CONFIG_EXTEND */
Chris Elston630710e2005-05-01 08:58:40 -0700[diff] [blame]243#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]244#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
245#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
246#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40
247#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80
248#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0
249#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03
250#define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c
251#define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0
252#define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1
253#define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3
254#define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00
255#define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04
256#define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08
257#define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c
258
259/* SCSI_LED */
260#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0
261#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1
262
263/* EQUIPMENT_PRESENT_1 */
264#define PPC7D_CPLD_EQPT_PRES_1_FITTED 0
265#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2)
266#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3)
267#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4)
268
269/* EQUIPMENT_PRESENT_2 */
270#define PPC7D_CPLD_EQPT_PRES_2_FITTED !0
271#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0)
272#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2)
273#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3)
274#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4)
275
276/* EQUIPMENT_PRESENT_3 */
277#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3)
278#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3)
279#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3)
280#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4)
281#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4)
282#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4)
283#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5)
284#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5)
285#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5)
286
287/* EQUIPMENT_PRESENT_4 */
288#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2)
289#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2)
290#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6)
291#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6)
292#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6)
293
294/* CPLD_LEDS */
295#define PPC7D_CPLD_LEDS_ON (!0)
296#define PPC7D_CPLD_LEDS_OFF (0)
297#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2)
298#define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4)
299#define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5)
300#define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6)
301#define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7)
302
303/* CPLD_COMS */
304#define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0)
305#define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1)
306#define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2)
307#define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0)
308#define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2)
309#define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3)
310#define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4)
311#define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5)
312#define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6)
313#define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0)
314#define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6)
315#define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7)
316
317/* CPLD_RTS */
318#define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0)
319#define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1)
320#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2)
321#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2)
322#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2)
323#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2)
324#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2)
325#define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4)
326#define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0)
327#define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4)
328#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5)
329#define PPC7D_CPLD_RTS_COM56_DISABLED (0)
330#define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5)
331#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6)
332#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6)
333#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6)
334#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6)
335#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6)
336
337/* WATCHDOG_TRIG */
338#define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0)
339#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0)
340#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0)
341#define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6)
342#define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6)
343#define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6)
344#define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7)
345#define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7)
346#define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7)
347
348/* Interrupt mask and status bits */
349#define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0)
350#define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1)
351#define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2)
352#define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3)
353#define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5)
354#define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6)
355
356/* CPLD_INTR */
357#define PPC7D_CPLD_INTR_ENABLE_OFF (0)
358#define PPC7D_CPLD_INTR_ENABLE_ON (!0)
359
360/* CPLD_INTR_STATUS */
361#define PPC7D_CPLD_INTR_STATUS_OFF (0)
362#define PPC7D_CPLD_INTR_STATUS_ON (!0)
363
364/* CPLD_PCI_CONFIG */
365#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70
366#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00
367#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10
368#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40
369#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50
370#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60
371#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70
372#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07
373#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00
374#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01
375#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04
376#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05
377#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06
378#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07
379
380/* CPLD_BOARD_REVISION */
381#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0
382#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f
383
384/* CPLD_EXTENDED_ID */
385#define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18
386
387/* CPLD_ID_LINK */
388#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2)
389#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3)
390#define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4)
391#define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5)
392#define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6)
393#define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7)
394
395/* CPLD_MOTHERBOARD_TYPE */
396#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0)
397#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0)
398#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0)
399#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3)
400#define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c
401#define PPC7D_CPLD_MB_TYPE_PLL_133 0x00
402#define PPC7D_CPLD_MB_TYPE_PLL_100 0x08
403#define PPC7D_CPLD_MB_TYPE_PLL_64 0x04
404#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03
405
406/* CPLD_FLASH_WRITE_CNTL */
407#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0)
408#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0)
409#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2)
410#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2)
411#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3)
412#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3)
413#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5)
414#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5)
415#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6)
416#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6)
417#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7)
418#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7)
419
420/* CPLD_SW_FLASH_WRITE_PROTECT */
421#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0)
422#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0)
423#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6)
424#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7)
425
426/* CPLD_FLASH_WRITE_CNTL */
427#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0)
428#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0)
429#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0)
430#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1)
431#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2)
432#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3)
433
434
435#endif /* __PPC_PLATFORMS_PPC7D_H */