Xiaozhe Shi | 28f5dd5 | 2013-01-04 12:19:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 13 | #define pr_fmt(fmt) "BMS: %s: " fmt, __func__ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/power_supply.h> |
| 23 | #include <linux/spmi.h> |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 24 | #include <linux/rtc.h> |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 25 | #include <linux/delay.h> |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 26 | #include <linux/qpnp/qpnp-adc.h> |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 27 | #include <linux/qpnp/power-on.h> |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 28 | #include <linux/of_batterydata.h> |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 29 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 30 | /* BMS Register Offsets */ |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 31 | #define REVISION1 0x0 |
| 32 | #define REVISION2 0x1 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 33 | #define BMS1_STATUS1 0x8 |
| 34 | #define BMS1_MODE_CTL 0X40 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 35 | /* Coulomb counter clear registers */ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 36 | #define BMS1_CC_DATA_CTL 0x42 |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 37 | #define BMS1_CC_CLEAR_CTL 0x43 |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 38 | /* BMS Tolerances */ |
| 39 | #define BMS1_TOL_CTL 0X44 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 40 | /* OCV limit registers */ |
| 41 | #define BMS1_OCV_USE_LOW_LIMIT_THR0 0x48 |
| 42 | #define BMS1_OCV_USE_LOW_LIMIT_THR1 0x49 |
| 43 | #define BMS1_OCV_USE_HIGH_LIMIT_THR0 0x4A |
| 44 | #define BMS1_OCV_USE_HIGH_LIMIT_THR1 0x4B |
| 45 | #define BMS1_OCV_USE_LIMIT_CTL 0x4C |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 46 | /* Delay control */ |
| 47 | #define BMS1_S1_DELAY_CTL 0x5A |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 48 | /* OCV interrupt threshold */ |
| 49 | #define BMS1_OCV_THR0 0x50 |
| 50 | /* SW CC interrupt threshold */ |
| 51 | #define BMS1_SW_CC_THR0 0xA0 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 52 | /* OCV for r registers */ |
| 53 | #define BMS1_OCV_FOR_R_DATA0 0x80 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 54 | #define BMS1_VSENSE_FOR_R_DATA0 0x82 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 55 | /* Coulomb counter data */ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 56 | #define BMS1_CC_DATA0 0x8A |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 57 | /* Shadow Coulomb counter data */ |
| 58 | #define BMS1_SW_CC_DATA0 0xA8 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 59 | /* OCV for soc data */ |
| 60 | #define BMS1_OCV_FOR_SOC_DATA0 0x90 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 61 | #define BMS1_VSENSE_PON_DATA0 0x94 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 62 | #define BMS1_VSENSE_AVG_DATA0 0x98 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 63 | #define BMS1_VBAT_AVG_DATA0 0x9E |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 64 | /* Extra bms registers */ |
Xiaozhe Shi | 5705894 | 2013-03-27 16:54:54 -0700 | [diff] [blame] | 65 | #define SOC_STORAGE_REG 0xB0 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 66 | #define IAVG_STORAGE_REG 0xB1 |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 67 | #define BMS_FCC_COUNT 0xB2 |
| 68 | #define BMS_FCC_BASE_REG 0xB3 /* FCC updates - 0xB3 to 0xB7 */ |
| 69 | #define BMS_CHGCYL_BASE_REG 0xB8 /* FCC chgcyl - 0xB8 to 0xBC */ |
| 70 | #define CHARGE_INCREASE_STORAGE 0xBD |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 71 | #define CHARGE_CYCLE_STORAGE_LSB 0xBE /* LSB=0xBE, MSB=0xBF */ |
| 72 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 73 | /* IADC Channel Select */ |
| 74 | #define IADC1_BMS_ADC_CH_SEL_CTL 0x48 |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 75 | #define IADC1_BMS_ADC_INT_RSNSN_CTL 0x49 |
| 76 | #define IADC1_BMS_FAST_AVG_EN 0x5B |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 77 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 78 | /* Configuration for saving of shutdown soc/iavg */ |
| 79 | #define IGNORE_SOC_TEMP_DECIDEG 50 |
| 80 | #define IAVG_STEP_SIZE_MA 50 |
| 81 | #define IAVG_START 600 |
Xiaozhe Shi | f5f966d | 2013-02-19 14:23:11 -0800 | [diff] [blame] | 82 | #define IAVG_INVALID 0xFF |
Xiaozhe Shi | c7cbd05 | 2013-03-29 12:03:11 -0700 | [diff] [blame] | 83 | #define SOC_INVALID 0xFF |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 84 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 85 | #define IAVG_SAMPLES 16 |
| 86 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 87 | /* FCC learning constants */ |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 88 | #define MAX_FCC_CYCLES 5 |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 89 | #define DELTA_FCC_PERCENT 5 |
| 90 | #define VALID_FCC_CHGCYL_RANGE 50 |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 91 | #define CHGCYL_RESOLUTION 20 |
| 92 | #define FCC_DEFAULT_TEMP 250 |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 93 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 94 | #define QPNP_BMS_DEV_NAME "qcom,qpnp-bms" |
| 95 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 96 | enum { |
| 97 | SHDW_CC, |
| 98 | CC |
| 99 | }; |
| 100 | |
| 101 | enum { |
| 102 | NORESET, |
| 103 | RESET |
| 104 | }; |
| 105 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 106 | struct soc_params { |
| 107 | int fcc_uah; |
| 108 | int cc_uah; |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 109 | int rbatt_mohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 110 | int iavg_ua; |
| 111 | int uuc_uah; |
| 112 | int ocv_charge_uah; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 113 | int delta_time_s; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | struct raw_soc_params { |
| 117 | uint16_t last_good_ocv_raw; |
| 118 | int64_t cc; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 119 | int64_t shdw_cc; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 120 | int last_good_ocv_uv; |
| 121 | }; |
| 122 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 123 | struct fcc_sample { |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 124 | int fcc_new; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 125 | int chargecycles; |
| 126 | }; |
| 127 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 128 | struct bms_irq { |
| 129 | unsigned int irq; |
| 130 | unsigned long disabled; |
| 131 | }; |
| 132 | |
| 133 | struct bms_wakeup_source { |
| 134 | struct wakeup_source source; |
| 135 | unsigned long disabled; |
| 136 | }; |
| 137 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 138 | struct qpnp_bms_chip { |
| 139 | struct device *dev; |
| 140 | struct power_supply bms_psy; |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 141 | bool bms_psy_registered; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 142 | struct power_supply *batt_psy; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 143 | struct spmi_device *spmi; |
| 144 | u16 base; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 145 | u16 iadc_base; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 146 | |
| 147 | u8 revision1; |
| 148 | u8 revision2; |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 149 | |
| 150 | u8 iadc_bms_revision1; |
| 151 | u8 iadc_bms_revision2; |
| 152 | |
Xiaozhe Shi | d5d2141 | 2013-02-06 17:14:41 -0800 | [diff] [blame] | 153 | int battery_present; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 154 | int battery_status; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 155 | bool new_battery; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 156 | bool done_charging; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 157 | bool last_soc_invalid; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 158 | /* platform data */ |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 159 | int r_sense_uohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 160 | unsigned int v_cutoff_uv; |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 161 | int max_voltage_uv; |
| 162 | int r_conn_mohm; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 163 | int shutdown_soc_valid_limit; |
| 164 | int adjust_soc_low_threshold; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 165 | int chg_term_ua; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 166 | enum battery_type batt_type; |
Xiaozhe Shi | 976618f | 2013-04-30 10:49:30 -0700 | [diff] [blame] | 167 | unsigned int fcc_mah; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 168 | struct single_row_lut *fcc_temp_lut; |
| 169 | struct single_row_lut *fcc_sf_lut; |
| 170 | struct pc_temp_ocv_lut *pc_temp_ocv_lut; |
| 171 | struct sf_lut *pc_sf_lut; |
| 172 | struct sf_lut *rbatt_sf_lut; |
| 173 | int default_rbatt_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 174 | int rbatt_capacitive_mohm; |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 175 | int rbatt_mohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 176 | |
| 177 | struct delayed_work calculate_soc_delayed_work; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 178 | struct work_struct recalc_work; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 179 | |
| 180 | struct mutex bms_output_lock; |
| 181 | struct mutex last_ocv_uv_mutex; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 182 | struct mutex vbat_monitor_mutex; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 183 | struct mutex soc_invalidation_mutex; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 184 | struct mutex last_soc_mutex; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 185 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 186 | bool use_external_rsense; |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 187 | bool use_ocv_thresholds; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 188 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 189 | bool ignore_shutdown_soc; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 190 | bool shutdown_soc_invalid; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 191 | int shutdown_soc; |
| 192 | int shutdown_iavg_ma; |
| 193 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 194 | struct wake_lock low_voltage_wake_lock; |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 195 | int low_voltage_threshold; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 196 | int low_soc_calc_threshold; |
| 197 | int low_soc_calculate_soc_ms; |
| 198 | int calculate_soc_ms; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 199 | struct bms_wakeup_source soc_wake_source; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 200 | struct wake_lock cv_wake_lock; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 201 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 202 | uint16_t ocv_reading_at_100; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 203 | uint16_t prev_last_good_ocv_raw; |
| 204 | int last_ocv_uv; |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 205 | int charging_adjusted_ocv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 206 | int last_ocv_temp; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 207 | int last_cc_uah; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 208 | unsigned long last_soc_change_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 209 | unsigned long tm_sec; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 210 | unsigned long report_tm_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 211 | bool first_time_calc_soc; |
| 212 | bool first_time_calc_uuc; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 213 | int64_t software_cc_uah; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 214 | int64_t software_shdw_cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 215 | |
| 216 | int iavg_samples_ma[IAVG_SAMPLES]; |
| 217 | int iavg_index; |
| 218 | int iavg_num_samples; |
| 219 | struct timespec t_soc_queried; |
| 220 | int last_soc; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 221 | int last_soc_est; |
Xiaozhe Shi | cc13726 | 2013-03-10 06:21:41 -0700 | [diff] [blame] | 222 | int last_soc_unbound; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 223 | bool was_charging_at_sleep; |
| 224 | int charge_start_tm_sec; |
| 225 | int catch_up_time_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 226 | struct single_row_lut *adjusted_fcc_temp_lut; |
| 227 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 228 | struct qpnp_adc_tm_btm_param vbat_monitor_params; |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 229 | struct qpnp_adc_tm_btm_param die_temp_monitor_params; |
| 230 | int temperature_margin; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 231 | unsigned int vadc_v0625; |
| 232 | unsigned int vadc_v1250; |
| 233 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 234 | int prev_uuc_iavg_ma; |
| 235 | int prev_pc_unusable; |
| 236 | int ibat_at_cv_ua; |
| 237 | int soc_at_cv; |
| 238 | int prev_chg_soc; |
| 239 | int calculated_soc; |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 240 | int prev_voltage_based_soc; |
| 241 | bool use_voltage_soc; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 242 | bool in_cv_range; |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 243 | |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 244 | int prev_batt_terminal_uv; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 245 | int high_ocv_correction_limit_uv; |
| 246 | int low_ocv_correction_limit_uv; |
| 247 | int flat_ocv_threshold_uv; |
| 248 | int hold_soc_est; |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 249 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 250 | int ocv_high_threshold_uv; |
| 251 | int ocv_low_threshold_uv; |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 252 | unsigned long last_recalc_time; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 253 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 254 | struct fcc_sample *fcc_learning_samples; |
| 255 | u8 fcc_sample_count; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 256 | int enable_fcc_learning; |
| 257 | int min_fcc_learning_soc; |
| 258 | int min_fcc_ocv_pc; |
| 259 | int min_fcc_learning_samples; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 260 | int start_soc; |
| 261 | int end_soc; |
| 262 | int start_pc; |
| 263 | int start_cc_uah; |
| 264 | int start_real_soc; |
| 265 | int end_cc_uah; |
| 266 | uint16_t fcc_new_mah; |
| 267 | int fcc_new_batt_temp; |
| 268 | uint16_t charge_cycles; |
| 269 | u8 charge_increase; |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 270 | int fcc_resolution; |
| 271 | bool battery_removed; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 272 | struct bms_irq sw_cc_thr_irq; |
| 273 | struct bms_irq ocv_thr_irq; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | static struct of_device_id qpnp_bms_match_table[] = { |
| 277 | { .compatible = QPNP_BMS_DEV_NAME }, |
| 278 | {} |
| 279 | }; |
| 280 | |
| 281 | static char *qpnp_bms_supplicants[] = { |
| 282 | "battery" |
| 283 | }; |
| 284 | |
| 285 | static enum power_supply_property msm_bms_power_props[] = { |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 286 | POWER_SUPPLY_PROP_CAPACITY, |
| 287 | POWER_SUPPLY_PROP_CURRENT_NOW, |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 288 | POWER_SUPPLY_PROP_RESISTANCE, |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 289 | POWER_SUPPLY_PROP_CHARGE_COUNTER, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 290 | POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 291 | POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 292 | POWER_SUPPLY_PROP_CHARGE_FULL, |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 293 | POWER_SUPPLY_PROP_CYCLE_COUNT, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 294 | }; |
| 295 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 296 | static int discard_backup_fcc_data(struct qpnp_bms_chip *chip); |
| 297 | static void backup_charge_cycle(struct qpnp_bms_chip *chip); |
| 298 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 299 | static bool bms_reset; |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 300 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 301 | static int qpnp_read_wrapper(struct qpnp_bms_chip *chip, u8 *val, |
| 302 | u16 base, int count) |
| 303 | { |
| 304 | int rc; |
| 305 | struct spmi_device *spmi = chip->spmi; |
| 306 | |
| 307 | rc = spmi_ext_register_readl(spmi->ctrl, spmi->sid, base, val, count); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 308 | if (rc) { |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 309 | pr_err("SPMI read failed rc=%d\n", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 310 | return rc; |
| 311 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 312 | return 0; |
| 313 | } |
| 314 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 315 | static int qpnp_write_wrapper(struct qpnp_bms_chip *chip, u8 *val, |
| 316 | u16 base, int count) |
| 317 | { |
| 318 | int rc; |
| 319 | struct spmi_device *spmi = chip->spmi; |
| 320 | |
| 321 | rc = spmi_ext_register_writel(spmi->ctrl, spmi->sid, base, val, count); |
| 322 | if (rc) { |
| 323 | pr_err("SPMI write failed rc=%d\n", rc); |
| 324 | return rc; |
| 325 | } |
| 326 | return 0; |
| 327 | } |
| 328 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 329 | static int qpnp_masked_write_base(struct qpnp_bms_chip *chip, u16 addr, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 330 | u8 mask, u8 val) |
| 331 | { |
| 332 | int rc; |
| 333 | u8 reg; |
| 334 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 335 | rc = qpnp_read_wrapper(chip, ®, addr, 1); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 336 | if (rc) { |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 337 | pr_err("read failed addr = %03X, rc = %d\n", addr, rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 338 | return rc; |
| 339 | } |
| 340 | reg &= ~mask; |
| 341 | reg |= val & mask; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 342 | rc = qpnp_write_wrapper(chip, ®, addr, 1); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 343 | if (rc) { |
| 344 | pr_err("write failed addr = %03X, val = %02x, mask = %02x, reg = %02x, rc = %d\n", |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 345 | addr, val, mask, reg, rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 346 | return rc; |
| 347 | } |
| 348 | return 0; |
| 349 | } |
| 350 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 351 | static int qpnp_masked_write_iadc(struct qpnp_bms_chip *chip, u16 addr, |
| 352 | u8 mask, u8 val) |
| 353 | { |
| 354 | return qpnp_masked_write_base(chip, chip->iadc_base + addr, mask, val); |
| 355 | } |
| 356 | |
| 357 | static int qpnp_masked_write(struct qpnp_bms_chip *chip, u16 addr, |
| 358 | u8 mask, u8 val) |
| 359 | { |
| 360 | return qpnp_masked_write_base(chip, chip->base + addr, mask, val); |
| 361 | } |
| 362 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 363 | static void bms_stay_awake(struct bms_wakeup_source *source) |
| 364 | { |
| 365 | if (__test_and_clear_bit(0, &source->disabled)) { |
| 366 | __pm_stay_awake(&source->source); |
| 367 | pr_debug("enabled source %s\n", source->source.name); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | static void bms_relax(struct bms_wakeup_source *source) |
| 372 | { |
| 373 | if (!__test_and_set_bit(0, &source->disabled)) { |
| 374 | __pm_relax(&source->source); |
| 375 | pr_debug("disabled source %s\n", source->source.name); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | static void enable_bms_irq(struct bms_irq *irq) |
| 380 | { |
| 381 | if (__test_and_clear_bit(0, &irq->disabled)) { |
| 382 | enable_irq(irq->irq); |
| 383 | pr_debug("enabled irq %d\n", irq->irq); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | static void disable_bms_irq(struct bms_irq *irq) |
| 388 | { |
| 389 | if (!__test_and_set_bit(0, &irq->disabled)) { |
| 390 | disable_irq(irq->irq); |
| 391 | pr_debug("disabled irq %d\n", irq->irq); |
| 392 | } |
| 393 | } |
| 394 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 395 | #define HOLD_OREG_DATA BIT(0) |
| 396 | static int lock_output_data(struct qpnp_bms_chip *chip) |
| 397 | { |
| 398 | int rc; |
| 399 | |
| 400 | rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL, |
| 401 | HOLD_OREG_DATA, HOLD_OREG_DATA); |
| 402 | if (rc) { |
| 403 | pr_err("couldnt lock bms output rc = %d\n", rc); |
| 404 | return rc; |
| 405 | } |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | static int unlock_output_data(struct qpnp_bms_chip *chip) |
| 410 | { |
| 411 | int rc; |
| 412 | |
| 413 | rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL, HOLD_OREG_DATA, 0); |
| 414 | if (rc) { |
| 415 | pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc); |
| 416 | return rc; |
| 417 | } |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | #define V_PER_BIT_MUL_FACTOR 97656 |
| 422 | #define V_PER_BIT_DIV_FACTOR 1000 |
| 423 | #define VADC_INTRINSIC_OFFSET 0x6000 |
| 424 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 425 | static int vadc_reading_to_uv(int reading) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 426 | { |
| 427 | if (reading <= VADC_INTRINSIC_OFFSET) |
| 428 | return 0; |
| 429 | |
| 430 | return (reading - VADC_INTRINSIC_OFFSET) |
| 431 | * V_PER_BIT_MUL_FACTOR / V_PER_BIT_DIV_FACTOR; |
| 432 | } |
| 433 | |
| 434 | #define VADC_CALIB_UV 625000 |
| 435 | #define VBATT_MUL_FACTOR 3 |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 436 | static int adjust_vbatt_reading(struct qpnp_bms_chip *chip, int reading_uv) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 437 | { |
| 438 | s64 numerator, denominator; |
| 439 | |
| 440 | if (reading_uv == 0) |
| 441 | return 0; |
| 442 | |
| 443 | /* don't adjust if not calibrated */ |
| 444 | if (chip->vadc_v0625 == 0 || chip->vadc_v1250 == 0) { |
| 445 | pr_debug("No cal yet return %d\n", |
| 446 | VBATT_MUL_FACTOR * reading_uv); |
| 447 | return VBATT_MUL_FACTOR * reading_uv; |
| 448 | } |
| 449 | |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 450 | numerator = ((s64)reading_uv - chip->vadc_v0625) * VADC_CALIB_UV; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 451 | denominator = (s64)chip->vadc_v1250 - chip->vadc_v0625; |
| 452 | if (denominator == 0) |
| 453 | return reading_uv * VBATT_MUL_FACTOR; |
| 454 | return (VADC_CALIB_UV + div_s64(numerator, denominator)) |
| 455 | * VBATT_MUL_FACTOR; |
| 456 | } |
| 457 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 458 | static int convert_vbatt_uv_to_raw(struct qpnp_bms_chip *chip, |
| 459 | int unadjusted_vbatt) |
| 460 | { |
| 461 | int scaled_vbatt = unadjusted_vbatt / VBATT_MUL_FACTOR; |
| 462 | |
| 463 | if (scaled_vbatt <= 0) |
| 464 | return VADC_INTRINSIC_OFFSET; |
| 465 | return ((scaled_vbatt * V_PER_BIT_DIV_FACTOR) / V_PER_BIT_MUL_FACTOR) |
| 466 | + VADC_INTRINSIC_OFFSET; |
| 467 | } |
| 468 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 469 | static inline int convert_vbatt_raw_to_uv(struct qpnp_bms_chip *chip, |
| 470 | uint16_t reading) |
| 471 | { |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 472 | int64_t uv; |
| 473 | int rc; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 474 | |
| 475 | uv = vadc_reading_to_uv(reading); |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 476 | pr_debug("%u raw converted into %lld uv\n", reading, uv); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 477 | uv = adjust_vbatt_reading(chip, uv); |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 478 | pr_debug("adjusted into %lld uv\n", uv); |
| 479 | rc = qpnp_vbat_sns_comp_result(&uv); |
| 480 | if (rc) |
| 481 | pr_debug("could not compensate vbatt\n"); |
| 482 | pr_debug("compensated into %lld uv\n", uv); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 483 | return uv; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | #define CC_READING_RESOLUTION_N 542535 |
| 487 | #define CC_READING_RESOLUTION_D 100000 |
Xiaozhe Shi | 8f5dd1b | 2013-04-30 10:27:58 -0700 | [diff] [blame] | 488 | static s64 cc_reading_to_uv(s64 reading) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 489 | { |
| 490 | return div_s64(reading * CC_READING_RESOLUTION_N, |
| 491 | CC_READING_RESOLUTION_D); |
| 492 | } |
| 493 | |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 494 | #define QPNP_ADC_GAIN_IDEAL 3291LL |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 495 | static s64 cc_adjust_for_gain(s64 uv, uint16_t gain) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 496 | { |
| 497 | s64 result_uv; |
| 498 | |
| 499 | pr_debug("adjusting_uv = %lld\n", uv); |
Xiaozhe Shi | 820a47a | 2012-11-27 13:23:27 -0800 | [diff] [blame] | 500 | if (gain == 0) { |
| 501 | pr_debug("gain is %d, not adjusting\n", gain); |
| 502 | return uv; |
| 503 | } |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 504 | pr_debug("adjusting by factor: %lld/%hu = %lld%%\n", |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 505 | QPNP_ADC_GAIN_IDEAL, gain, |
| 506 | div_s64(QPNP_ADC_GAIN_IDEAL * 100LL, (s64)gain)); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 507 | |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 508 | result_uv = div_s64(uv * QPNP_ADC_GAIN_IDEAL, (s64)gain); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 509 | pr_debug("result_uv = %lld\n", result_uv); |
| 510 | return result_uv; |
| 511 | } |
| 512 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 513 | static s64 cc_reverse_adjust_for_gain(s64 uv) |
| 514 | { |
| 515 | struct qpnp_iadc_calib calibration; |
| 516 | int gain; |
| 517 | s64 result_uv; |
| 518 | |
| 519 | qpnp_iadc_get_gain_and_offset(&calibration); |
| 520 | gain = (int)calibration.gain_raw - (int)calibration.offset_raw; |
| 521 | |
| 522 | pr_debug("reverse adjusting_uv = %lld\n", uv); |
| 523 | if (gain == 0) { |
| 524 | pr_debug("gain is %d, not adjusting\n", gain); |
| 525 | return uv; |
| 526 | } |
| 527 | pr_debug("adjusting by factor: %hu/%lld = %lld%%\n", |
| 528 | gain, QPNP_ADC_GAIN_IDEAL, |
| 529 | div64_s64((s64)gain * 100LL, |
| 530 | (s64)QPNP_ADC_GAIN_IDEAL)); |
| 531 | |
| 532 | result_uv = div64_s64(uv * (s64)gain, QPNP_ADC_GAIN_IDEAL); |
| 533 | pr_debug("result_uv = %lld\n", result_uv); |
| 534 | return result_uv; |
| 535 | } |
| 536 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 537 | static int convert_vsense_to_uv(struct qpnp_bms_chip *chip, |
| 538 | int16_t reading) |
| 539 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 540 | struct qpnp_iadc_calib calibration; |
| 541 | |
| 542 | qpnp_iadc_get_gain_and_offset(&calibration); |
| 543 | return cc_adjust_for_gain(cc_reading_to_uv(reading), |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 544 | calibration.gain_raw - calibration.offset_raw); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | static int read_vsense_avg(struct qpnp_bms_chip *chip, int *result_uv) |
| 548 | { |
| 549 | int rc; |
| 550 | int16_t reading; |
| 551 | |
| 552 | rc = qpnp_read_wrapper(chip, (u8 *)&reading, |
| 553 | chip->base + BMS1_VSENSE_AVG_DATA0, 2); |
| 554 | |
| 555 | if (rc) { |
| 556 | pr_err("fail to read VSENSE_AVG rc = %d\n", rc); |
| 557 | return rc; |
| 558 | } |
| 559 | |
| 560 | *result_uv = convert_vsense_to_uv(chip, reading); |
| 561 | return 0; |
| 562 | } |
| 563 | |
| 564 | static int get_battery_current(struct qpnp_bms_chip *chip, int *result_ua) |
| 565 | { |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 566 | int rc, vsense_uv = 0; |
| 567 | int64_t temp_current; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 568 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 569 | if (chip->r_sense_uohm == 0) { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 570 | pr_err("r_sense is zero\n"); |
| 571 | return -EINVAL; |
| 572 | } |
| 573 | |
| 574 | mutex_lock(&chip->bms_output_lock); |
| 575 | lock_output_data(chip); |
| 576 | read_vsense_avg(chip, &vsense_uv); |
| 577 | unlock_output_data(chip); |
| 578 | mutex_unlock(&chip->bms_output_lock); |
| 579 | |
| 580 | pr_debug("vsense_uv=%duV\n", vsense_uv); |
| 581 | /* cast for signed division */ |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 582 | temp_current = div_s64((vsense_uv * 1000000LL), |
| 583 | (int)chip->r_sense_uohm); |
| 584 | |
| 585 | rc = qpnp_iadc_comp_result(&temp_current); |
| 586 | if (rc) |
| 587 | pr_debug("error compensation failed: %d\n", rc); |
| 588 | |
| 589 | *result_ua = temp_current; |
| 590 | pr_debug("err compensated ibat=%duA\n", *result_ua); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 591 | return 0; |
| 592 | } |
| 593 | |
| 594 | static int get_battery_voltage(int *result_uv) |
| 595 | { |
| 596 | int rc; |
| 597 | struct qpnp_vadc_result adc_result; |
| 598 | |
| 599 | rc = qpnp_vadc_read(VBAT_SNS, &adc_result); |
| 600 | if (rc) { |
| 601 | pr_err("error reading adc channel = %d, rc = %d\n", |
| 602 | VBAT_SNS, rc); |
| 603 | return rc; |
| 604 | } |
| 605 | pr_debug("mvolts phy = %lld meas = 0x%llx\n", adc_result.physical, |
| 606 | adc_result.measurement); |
| 607 | *result_uv = (int)adc_result.physical; |
| 608 | return 0; |
| 609 | } |
| 610 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 611 | #define CC_36_BIT_MASK 0xFFFFFFFFFLL |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 612 | static uint64_t convert_s64_to_s36(int64_t raw64) |
| 613 | { |
| 614 | return (uint64_t) raw64 & CC_36_BIT_MASK; |
| 615 | } |
| 616 | |
| 617 | #define SIGN_EXTEND_36_TO_64_MASK (-1LL ^ CC_36_BIT_MASK) |
| 618 | static int64_t convert_s36_to_s64(uint64_t raw36) |
| 619 | { |
| 620 | raw36 = raw36 & CC_36_BIT_MASK; |
| 621 | /* convert 36 bit signed value into 64 signed value */ |
| 622 | return (raw36 >> 35) == 0LL ? |
| 623 | raw36 : (SIGN_EXTEND_36_TO_64_MASK | raw36); |
| 624 | } |
| 625 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 626 | static int read_cc_raw(struct qpnp_bms_chip *chip, int64_t *reading, |
| 627 | int cc_type) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 628 | { |
| 629 | int64_t raw_reading; |
| 630 | int rc; |
| 631 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 632 | if (cc_type == SHDW_CC) |
| 633 | rc = qpnp_read_wrapper(chip, (u8 *)&raw_reading, |
| 634 | chip->base + BMS1_SW_CC_DATA0, 5); |
| 635 | else |
| 636 | rc = qpnp_read_wrapper(chip, (u8 *)&raw_reading, |
| 637 | chip->base + BMS1_CC_DATA0, 5); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 638 | if (rc) { |
| 639 | pr_err("Error reading cc: rc = %d\n", rc); |
| 640 | return -ENXIO; |
| 641 | } |
| 642 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 643 | *reading = convert_s36_to_s64(raw_reading); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 644 | |
| 645 | return 0; |
| 646 | } |
| 647 | |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 648 | static int calib_vadc(struct qpnp_bms_chip *chip) |
| 649 | { |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 650 | int rc, raw_0625, raw_1250; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 651 | struct qpnp_vadc_result result; |
| 652 | |
| 653 | rc = qpnp_vadc_read(REF_625MV, &result); |
| 654 | if (rc) { |
| 655 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 656 | return rc; |
| 657 | } |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 658 | raw_0625 = result.adc_code; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 659 | |
| 660 | rc = qpnp_vadc_read(REF_125V, &result); |
| 661 | if (rc) { |
| 662 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 663 | return rc; |
| 664 | } |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 665 | raw_1250 = result.adc_code; |
| 666 | chip->vadc_v0625 = vadc_reading_to_uv(raw_0625); |
| 667 | chip->vadc_v1250 = vadc_reading_to_uv(raw_1250); |
| 668 | pr_debug("vadc calib: 0625 = %d raw (%d uv), 1250 = %d raw (%d uv)\n", |
| 669 | raw_0625, chip->vadc_v0625, |
| 670 | raw_1250, chip->vadc_v1250); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 671 | return 0; |
| 672 | } |
| 673 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 674 | static void convert_and_store_ocv(struct qpnp_bms_chip *chip, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 675 | struct raw_soc_params *raw, |
| 676 | int batt_temp) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 677 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 678 | int rc; |
| 679 | |
| 680 | pr_debug("prev_last_good_ocv_raw = %d, last_good_ocv_raw = %d\n", |
| 681 | chip->prev_last_good_ocv_raw, |
| 682 | raw->last_good_ocv_raw); |
| 683 | rc = calib_vadc(chip); |
| 684 | if (rc) |
| 685 | pr_err("Vadc reference voltage read failed, rc = %d\n", rc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 686 | chip->prev_last_good_ocv_raw = raw->last_good_ocv_raw; |
| 687 | raw->last_good_ocv_uv = convert_vbatt_raw_to_uv(chip, |
| 688 | raw->last_good_ocv_raw); |
| 689 | chip->last_ocv_uv = raw->last_good_ocv_uv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 690 | chip->last_ocv_temp = batt_temp; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 691 | chip->software_cc_uah = 0; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 692 | pr_debug("last_good_ocv_uv = %d\n", raw->last_good_ocv_uv); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 693 | } |
| 694 | |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 695 | #define CLEAR_CC BIT(7) |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 696 | #define CLEAR_SHDW_CC BIT(6) |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 697 | /** |
| 698 | * reset both cc and sw-cc. |
| 699 | * note: this should only be ever called from one thread |
| 700 | * or there may be a race condition where CC is never enabled |
| 701 | * again |
| 702 | */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 703 | static void reset_cc(struct qpnp_bms_chip *chip, u8 flags) |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 704 | { |
| 705 | int rc; |
| 706 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 707 | pr_debug("resetting cc manually with flags %hhu\n", flags); |
| 708 | mutex_lock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 709 | rc = qpnp_masked_write(chip, BMS1_CC_CLEAR_CTL, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 710 | flags, |
| 711 | flags); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 712 | if (rc) |
| 713 | pr_err("cc reset failed: %d\n", rc); |
| 714 | |
| 715 | /* wait for 100us for cc to reset */ |
| 716 | udelay(100); |
| 717 | |
| 718 | rc = qpnp_masked_write(chip, BMS1_CC_CLEAR_CTL, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 719 | flags, 0); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 720 | if (rc) |
| 721 | pr_err("cc reenable failed: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 722 | mutex_unlock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 723 | } |
| 724 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 725 | static int get_battery_status(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 726 | { |
| 727 | union power_supply_propval ret = {0,}; |
| 728 | |
| 729 | if (chip->batt_psy == NULL) |
| 730 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 731 | if (chip->batt_psy) { |
| 732 | /* if battery has been registered, use the status property */ |
| 733 | chip->batt_psy->get_property(chip->batt_psy, |
| 734 | POWER_SUPPLY_PROP_STATUS, &ret); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 735 | return ret.intval; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 736 | } |
| 737 | |
| 738 | /* Default to false if the battery power supply is not registered. */ |
| 739 | pr_debug("battery power supply is not registered\n"); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 740 | return POWER_SUPPLY_STATUS_UNKNOWN; |
| 741 | } |
| 742 | |
| 743 | static bool is_battery_charging(struct qpnp_bms_chip *chip) |
| 744 | { |
| 745 | return get_battery_status(chip) == POWER_SUPPLY_STATUS_CHARGING; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 746 | } |
| 747 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 748 | static bool is_battery_present(struct qpnp_bms_chip *chip) |
| 749 | { |
| 750 | union power_supply_propval ret = {0,}; |
| 751 | |
| 752 | if (chip->batt_psy == NULL) |
| 753 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 754 | if (chip->batt_psy) { |
| 755 | /* if battery has been registered, use the status property */ |
| 756 | chip->batt_psy->get_property(chip->batt_psy, |
| 757 | POWER_SUPPLY_PROP_PRESENT, &ret); |
| 758 | return ret.intval; |
| 759 | } |
| 760 | |
| 761 | /* Default to false if the battery power supply is not registered. */ |
| 762 | pr_debug("battery power supply is not registered\n"); |
| 763 | return false; |
| 764 | } |
| 765 | |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 766 | static bool is_battery_full(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 767 | { |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 768 | return get_battery_status(chip) == POWER_SUPPLY_STATUS_FULL; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | static int get_simultaneous_batt_v_and_i(struct qpnp_bms_chip *chip, |
| 772 | int *ibat_ua, int *vbat_uv) |
| 773 | { |
| 774 | struct qpnp_iadc_result i_result; |
| 775 | struct qpnp_vadc_result v_result; |
| 776 | enum qpnp_iadc_channels iadc_channel; |
| 777 | int rc; |
| 778 | |
| 779 | iadc_channel = chip->use_external_rsense ? |
| 780 | EXTERNAL_RSENSE : INTERNAL_RSENSE; |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 781 | if (is_battery_full(chip)) { |
| 782 | rc = get_battery_current(chip, ibat_ua); |
| 783 | if (rc) { |
| 784 | pr_err("bms current read failed with rc: %d\n", rc); |
| 785 | return rc; |
| 786 | } |
| 787 | rc = qpnp_vadc_read(VBAT_SNS, &v_result); |
| 788 | if (rc) { |
| 789 | pr_err("vadc read failed with rc: %d\n", rc); |
| 790 | return rc; |
| 791 | } |
| 792 | *vbat_uv = (int)v_result.physical; |
| 793 | } else { |
| 794 | rc = qpnp_iadc_vadc_sync_read(iadc_channel, &i_result, |
| 795 | VBAT_SNS, &v_result); |
| 796 | if (rc) { |
| 797 | pr_err("adc sync read failed with rc: %d\n", rc); |
| 798 | return rc; |
| 799 | } |
| 800 | /* |
| 801 | * reverse the current read by the iadc, since the bms uses |
| 802 | * flipped battery current polarity. |
| 803 | */ |
| 804 | *ibat_ua = -1 * (int)i_result.result_ua; |
| 805 | *vbat_uv = (int)v_result.physical; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 806 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 807 | |
| 808 | return 0; |
| 809 | } |
| 810 | |
| 811 | static int estimate_ocv(struct qpnp_bms_chip *chip) |
| 812 | { |
| 813 | int ibat_ua, vbat_uv, ocv_est_uv; |
| 814 | int rc; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 815 | int rbatt_mohm = chip->default_rbatt_mohm + chip->r_conn_mohm |
| 816 | + chip->rbatt_capacitive_mohm; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 817 | |
| 818 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 819 | if (rc) { |
| 820 | pr_err("simultaneous failed rc = %d\n", rc); |
| 821 | return rc; |
| 822 | } |
| 823 | |
| 824 | ocv_est_uv = vbat_uv + (ibat_ua * rbatt_mohm) / 1000; |
| 825 | pr_debug("estimated pon ocv = %d\n", ocv_est_uv); |
| 826 | return ocv_est_uv; |
| 827 | } |
| 828 | |
| 829 | static void reset_for_new_battery(struct qpnp_bms_chip *chip, int batt_temp) |
| 830 | { |
| 831 | chip->last_ocv_uv = estimate_ocv(chip); |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 832 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 833 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 834 | chip->last_soc_invalid = true; |
| 835 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 836 | chip->soc_at_cv = -EINVAL; |
| 837 | chip->shutdown_soc_invalid = true; |
| 838 | chip->shutdown_soc = 0; |
| 839 | chip->shutdown_iavg_ma = 0; |
| 840 | chip->prev_pc_unusable = -EINVAL; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 841 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 842 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 843 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 844 | chip->last_cc_uah = INT_MIN; |
| 845 | chip->last_ocv_temp = batt_temp; |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 846 | chip->prev_batt_terminal_uv = 0; |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 847 | if (chip->enable_fcc_learning) { |
| 848 | chip->adjusted_fcc_temp_lut = NULL; |
| 849 | chip->fcc_new_mah = -EINVAL; |
| 850 | /* reset the charge-cycle and charge-increase registers */ |
| 851 | chip->charge_increase = 0; |
| 852 | chip->charge_cycles = 0; |
| 853 | backup_charge_cycle(chip); |
| 854 | /* discard all the FCC learnt data and reset the local table */ |
| 855 | discard_backup_fcc_data(chip); |
| 856 | memset(chip->fcc_learning_samples, 0, |
| 857 | chip->min_fcc_learning_samples * |
| 858 | sizeof(struct fcc_sample)); |
| 859 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 860 | } |
| 861 | |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 862 | #define OCV_RAW_UNINITIALIZED 0xFFFF |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 863 | #define MIN_OCV_UV 2000000 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 864 | static int read_soc_params_raw(struct qpnp_bms_chip *chip, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 865 | struct raw_soc_params *raw, |
| 866 | int batt_temp) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 867 | { |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 868 | bool warm_reset = false; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 869 | int rc; |
| 870 | |
| 871 | mutex_lock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 872 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 873 | lock_output_data(chip); |
| 874 | |
| 875 | rc = qpnp_read_wrapper(chip, (u8 *)&raw->last_good_ocv_raw, |
| 876 | chip->base + BMS1_OCV_FOR_SOC_DATA0, 2); |
| 877 | if (rc) { |
| 878 | pr_err("Error reading ocv: rc = %d\n", rc); |
| 879 | return -ENXIO; |
| 880 | } |
| 881 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 882 | rc = read_cc_raw(chip, &raw->cc, CC); |
| 883 | rc = read_cc_raw(chip, &raw->shdw_cc, SHDW_CC); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 884 | if (rc) { |
| 885 | pr_err("Failed to read raw cc data, rc = %d\n", rc); |
| 886 | return rc; |
| 887 | } |
| 888 | |
| 889 | unlock_output_data(chip); |
| 890 | mutex_unlock(&chip->bms_output_lock); |
| 891 | |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 892 | if (chip->prev_last_good_ocv_raw == OCV_RAW_UNINITIALIZED) { |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 893 | convert_and_store_ocv(chip, raw, batt_temp); |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 894 | pr_debug("PON_OCV_UV = %d, cc = %llx\n", |
| 895 | chip->last_ocv_uv, raw->cc); |
| 896 | warm_reset = qpnp_pon_is_warm_reset(); |
| 897 | if (raw->last_good_ocv_uv < MIN_OCV_UV |
| 898 | || warm_reset > 0) { |
| 899 | pr_debug("OCV is stale or bad, estimating new OCV.\n"); |
| 900 | chip->last_ocv_uv = estimate_ocv(chip); |
| 901 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 902 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 903 | pr_debug("New PON_OCV_UV = %d, cc = %llx\n", |
| 904 | chip->last_ocv_uv, raw->cc); |
| 905 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 906 | } else if (chip->new_battery) { |
| 907 | /* if a new battery was inserted, estimate the ocv */ |
| 908 | reset_for_new_battery(chip, batt_temp); |
| 909 | raw->cc = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 910 | raw->shdw_cc = 0; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 911 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
| 912 | chip->new_battery = false; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 913 | } else if (chip->done_charging) { |
| 914 | chip->done_charging = false; |
| 915 | /* if we just finished charging, reset CC and fake 100% */ |
| 916 | chip->ocv_reading_at_100 = raw->last_good_ocv_raw; |
| 917 | chip->last_ocv_uv = chip->max_voltage_uv; |
| 918 | raw->last_good_ocv_uv = chip->max_voltage_uv; |
| 919 | raw->cc = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 920 | raw->shdw_cc = 0; |
| 921 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 922 | chip->last_ocv_temp = batt_temp; |
| 923 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 924 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 925 | chip->last_cc_uah = INT_MIN; |
| 926 | pr_debug("EOC Battery full ocv_reading = 0x%x\n", |
| 927 | chip->ocv_reading_at_100); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 928 | } else if (chip->prev_last_good_ocv_raw != raw->last_good_ocv_raw) { |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 929 | convert_and_store_ocv(chip, raw, batt_temp); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 930 | /* forget the old cc value upon ocv */ |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 931 | chip->last_cc_uah = INT_MIN; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 932 | } else { |
| 933 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
| 934 | } |
| 935 | |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 936 | /* stop faking a high OCV if we get a new OCV */ |
| 937 | if (chip->ocv_reading_at_100 != raw->last_good_ocv_raw) |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 938 | chip->ocv_reading_at_100 = OCV_RAW_UNINITIALIZED; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 939 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 940 | pr_debug("last_good_ocv_raw= 0x%x, last_good_ocv_uv= %duV\n", |
| 941 | raw->last_good_ocv_raw, raw->last_good_ocv_uv); |
| 942 | pr_debug("cc_raw= 0x%llx\n", raw->cc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 943 | return 0; |
| 944 | } |
| 945 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 946 | static int calculate_pc(struct qpnp_bms_chip *chip, int ocv_uv, |
| 947 | int batt_temp) |
| 948 | { |
| 949 | int pc; |
| 950 | |
| 951 | pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 952 | batt_temp / 10, ocv_uv / 1000); |
| 953 | pr_debug("pc = %u %% for ocv = %d uv batt_temp = %d\n", |
| 954 | pc, ocv_uv, batt_temp); |
| 955 | /* Multiply the initial FCC value by the scale factor. */ |
| 956 | return pc; |
| 957 | } |
| 958 | |
| 959 | static int calculate_fcc(struct qpnp_bms_chip *chip, int batt_temp) |
| 960 | { |
| 961 | int fcc_uah; |
| 962 | |
| 963 | if (chip->adjusted_fcc_temp_lut == NULL) { |
| 964 | /* interpolate_fcc returns a mv value. */ |
| 965 | fcc_uah = interpolate_fcc(chip->fcc_temp_lut, |
| 966 | batt_temp) * 1000; |
| 967 | pr_debug("fcc = %d uAh\n", fcc_uah); |
| 968 | return fcc_uah; |
| 969 | } else { |
| 970 | return 1000 * interpolate_fcc(chip->adjusted_fcc_temp_lut, |
| 971 | batt_temp); |
| 972 | } |
| 973 | } |
| 974 | |
| 975 | /* calculate remaining charge at the time of ocv */ |
| 976 | static int calculate_ocv_charge(struct qpnp_bms_chip *chip, |
| 977 | struct raw_soc_params *raw, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 978 | int fcc_uah) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 979 | { |
| 980 | int ocv_uv, pc; |
| 981 | |
| 982 | ocv_uv = raw->last_good_ocv_uv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 983 | pc = calculate_pc(chip, ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 984 | pr_debug("ocv_uv = %d pc = %d\n", ocv_uv, pc); |
| 985 | return (fcc_uah * pc) / 100; |
| 986 | } |
| 987 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 988 | #define CC_READING_TICKS 56 |
| 989 | #define SLEEP_CLK_HZ 32764 |
| 990 | #define SECONDS_PER_HOUR 3600 |
| 991 | |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 992 | static s64 cc_uv_to_pvh(s64 cc_uv) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 993 | { |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 994 | /* Note that it is necessary need to multiply by 1000000 to convert |
| 995 | * from uvh to pvh here. |
| 996 | * However, the maximum Coulomb Counter value is 2^35, which can cause |
| 997 | * an over flow. |
| 998 | * Multiply by 100000 first to perserve as much precision as possible |
| 999 | * then multiply by 10 after doing the division in order to avoid |
| 1000 | * overflow on the maximum Coulomb Counter value. |
| 1001 | */ |
| 1002 | return div_s64(cc_uv * CC_READING_TICKS * 100000, |
| 1003 | SLEEP_CLK_HZ * SECONDS_PER_HOUR) * 10; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | /** |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1007 | * calculate_cc() - converts a hardware coulomb counter reading into uah |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1008 | * @chip: the bms chip pointer |
| 1009 | * @cc: the cc reading from bms h/w |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1010 | * @cc_type: calcualte cc from regular or shadow coulomb counter |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1011 | * @clear_cc: whether this function should clear the hardware counter |
| 1012 | * after reading |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1013 | * |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1014 | * Converts the 64 bit hardware coulomb counter into microamp-hour by taking |
| 1015 | * into account hardware resolution and adc errors. |
| 1016 | * |
| 1017 | * Return: the coulomb counter based charge in uAh (micro-amp hour) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1018 | */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1019 | static int calculate_cc(struct qpnp_bms_chip *chip, int64_t cc, |
| 1020 | int cc_type, int clear_cc) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1021 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 1022 | struct qpnp_iadc_calib calibration; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1023 | struct qpnp_vadc_result result; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1024 | int64_t cc_voltage_uv, cc_pvh, cc_uah, *software_counter; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1025 | int rc; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1026 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1027 | software_counter = cc_type == SHDW_CC ? |
| 1028 | &chip->software_shdw_cc_uah : &chip->software_cc_uah; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1029 | rc = qpnp_vadc_read(DIE_TEMP, &result); |
| 1030 | if (rc) { |
| 1031 | pr_err("could not read pmic die temperature: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1032 | return *software_counter; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1033 | } |
| 1034 | |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 1035 | qpnp_iadc_get_gain_and_offset(&calibration); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1036 | pr_debug("%scc = %lld, die_temp = %lld\n", |
| 1037 | cc_type == SHDW_CC ? "shdw_" : "", |
| 1038 | cc, result.physical); |
Xiaozhe Shi | 8f5dd1b | 2013-04-30 10:27:58 -0700 | [diff] [blame] | 1039 | cc_voltage_uv = cc_reading_to_uv(cc); |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 1040 | cc_voltage_uv = cc_adjust_for_gain(cc_voltage_uv, |
| 1041 | calibration.gain_raw |
| 1042 | - calibration.offset_raw); |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1043 | cc_pvh = cc_uv_to_pvh(cc_voltage_uv); |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1044 | cc_uah = div_s64(cc_pvh, chip->r_sense_uohm); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1045 | rc = qpnp_iadc_comp_result(&cc_uah); |
| 1046 | if (rc) |
| 1047 | pr_debug("error compensation failed: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1048 | if (clear_cc == RESET) { |
| 1049 | pr_debug("software_%scc = %lld, added cc_uah = %lld\n", |
| 1050 | cc_type == SHDW_CC ? "sw_" : "", |
| 1051 | *software_counter, cc_uah); |
| 1052 | *software_counter += cc_uah; |
| 1053 | reset_cc(chip, cc_type == SHDW_CC ? CLEAR_SHDW_CC : CLEAR_CC); |
| 1054 | return (int)*software_counter; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1055 | } else { |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1056 | pr_debug("software_%scc = %lld, cc_uah = %lld, total = %lld\n", |
| 1057 | cc_type == SHDW_CC ? "shdw_" : "", |
| 1058 | *software_counter, cc_uah, |
| 1059 | *software_counter + cc_uah); |
| 1060 | return *software_counter + cc_uah; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1061 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1062 | } |
| 1063 | |
| 1064 | static int get_rbatt(struct qpnp_bms_chip *chip, |
| 1065 | int soc_rbatt_mohm, int batt_temp) |
| 1066 | { |
| 1067 | int rbatt_mohm, scalefactor; |
| 1068 | |
| 1069 | rbatt_mohm = chip->default_rbatt_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1070 | if (chip->rbatt_sf_lut == NULL) { |
| 1071 | pr_debug("RBATT = %d\n", rbatt_mohm); |
| 1072 | return rbatt_mohm; |
| 1073 | } |
| 1074 | /* Convert the batt_temp to DegC from deciDegC */ |
| 1075 | batt_temp = batt_temp / 10; |
| 1076 | scalefactor = interpolate_scalingfactor(chip->rbatt_sf_lut, |
| 1077 | batt_temp, soc_rbatt_mohm); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1078 | rbatt_mohm = (rbatt_mohm * scalefactor) / 100; |
| 1079 | |
| 1080 | rbatt_mohm += chip->r_conn_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 1081 | rbatt_mohm += chip->rbatt_capacitive_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1082 | return rbatt_mohm; |
| 1083 | } |
| 1084 | |
Xiaozhe Shi | 06b67cc | 2013-03-29 12:07:40 -0700 | [diff] [blame] | 1085 | #define IAVG_MINIMAL_TIME 2 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1086 | static void calculate_iavg(struct qpnp_bms_chip *chip, int cc_uah, |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1087 | int *iavg_ua, int delta_time_s) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1088 | { |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1089 | int delta_cc_uah = 0; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1090 | |
Xiaozhe Shi | 06b67cc | 2013-03-29 12:07:40 -0700 | [diff] [blame] | 1091 | /* |
| 1092 | * use the battery current if called too quickly |
| 1093 | */ |
| 1094 | if (delta_time_s < IAVG_MINIMAL_TIME |
| 1095 | || chip->last_cc_uah == INT_MIN) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1096 | get_battery_current(chip, iavg_ua); |
| 1097 | goto out; |
| 1098 | } |
| 1099 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1100 | delta_cc_uah = cc_uah - chip->last_cc_uah; |
| 1101 | |
| 1102 | *iavg_ua = div_s64((s64)delta_cc_uah * 3600, delta_time_s); |
| 1103 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1104 | out: |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1105 | pr_debug("delta_cc = %d iavg_ua = %d\n", delta_cc_uah, (int)*iavg_ua); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1106 | |
| 1107 | /* remember cc_uah */ |
| 1108 | chip->last_cc_uah = cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1109 | } |
| 1110 | |
| 1111 | static int calculate_termination_uuc(struct qpnp_bms_chip *chip, |
| 1112 | struct soc_params *params, |
| 1113 | int batt_temp, int uuc_iavg_ma, |
| 1114 | int *ret_pc_unusable) |
| 1115 | { |
| 1116 | int unusable_uv, pc_unusable, uuc_uah; |
| 1117 | int i = 0; |
| 1118 | int ocv_mv; |
| 1119 | int batt_temp_degc = batt_temp / 10; |
| 1120 | int rbatt_mohm; |
| 1121 | int delta_uv; |
| 1122 | int prev_delta_uv = 0; |
| 1123 | int prev_rbatt_mohm = 0; |
| 1124 | int uuc_rbatt_mohm; |
| 1125 | |
| 1126 | for (i = 0; i <= 100; i++) { |
| 1127 | ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut, |
| 1128 | batt_temp_degc, i); |
| 1129 | rbatt_mohm = get_rbatt(chip, i, batt_temp); |
| 1130 | unusable_uv = (rbatt_mohm * uuc_iavg_ma) |
| 1131 | + (chip->v_cutoff_uv); |
| 1132 | delta_uv = ocv_mv * 1000 - unusable_uv; |
| 1133 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1134 | if (delta_uv > 0) |
| 1135 | break; |
| 1136 | |
| 1137 | prev_delta_uv = delta_uv; |
| 1138 | prev_rbatt_mohm = rbatt_mohm; |
| 1139 | } |
| 1140 | |
| 1141 | uuc_rbatt_mohm = linear_interpolate(rbatt_mohm, delta_uv, |
| 1142 | prev_rbatt_mohm, prev_delta_uv, |
| 1143 | 0); |
| 1144 | |
| 1145 | unusable_uv = (uuc_rbatt_mohm * uuc_iavg_ma) + (chip->v_cutoff_uv); |
| 1146 | |
| 1147 | pc_unusable = calculate_pc(chip, unusable_uv, batt_temp); |
| 1148 | uuc_uah = (params->fcc_uah * pc_unusable) / 100; |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1149 | pr_debug("For uuc_iavg_ma = %d, unusable_rbatt = %d unusable_uv = %d unusable_pc = %d rbatt_pc = %d uuc = %d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1150 | uuc_iavg_ma, |
| 1151 | uuc_rbatt_mohm, unusable_uv, |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1152 | pc_unusable, i, uuc_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1153 | *ret_pc_unusable = pc_unusable; |
| 1154 | return uuc_uah; |
| 1155 | } |
| 1156 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1157 | #define TIME_PER_PERCENT_UUC 60 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1158 | static int adjust_uuc(struct qpnp_bms_chip *chip, |
| 1159 | struct soc_params *params, |
| 1160 | int new_pc_unusable, |
| 1161 | int new_uuc_uah, |
| 1162 | int batt_temp) |
| 1163 | { |
| 1164 | int new_unusable_mv, new_iavg_ma; |
| 1165 | int batt_temp_degc = batt_temp / 10; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1166 | int max_percent_change; |
| 1167 | |
| 1168 | max_percent_change = max(params->delta_time_s |
| 1169 | / TIME_PER_PERCENT_UUC, 1); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1170 | |
| 1171 | if (chip->prev_pc_unusable == -EINVAL |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1172 | || abs(chip->prev_pc_unusable - new_pc_unusable) |
| 1173 | <= max_percent_change) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1174 | chip->prev_pc_unusable = new_pc_unusable; |
| 1175 | return new_uuc_uah; |
| 1176 | } |
| 1177 | |
| 1178 | /* the uuc is trying to change more than 1% restrict it */ |
| 1179 | if (new_pc_unusable > chip->prev_pc_unusable) |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1180 | chip->prev_pc_unusable += max_percent_change; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1181 | else |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1182 | chip->prev_pc_unusable -= max_percent_change; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1183 | |
| 1184 | new_uuc_uah = (params->fcc_uah * chip->prev_pc_unusable) / 100; |
| 1185 | |
| 1186 | /* also find update the iavg_ma accordingly */ |
| 1187 | new_unusable_mv = interpolate_ocv(chip->pc_temp_ocv_lut, |
| 1188 | batt_temp_degc, chip->prev_pc_unusable); |
| 1189 | if (new_unusable_mv < chip->v_cutoff_uv/1000) |
| 1190 | new_unusable_mv = chip->v_cutoff_uv/1000; |
| 1191 | |
| 1192 | new_iavg_ma = (new_unusable_mv * 1000 - chip->v_cutoff_uv) |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 1193 | / params->rbatt_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1194 | if (new_iavg_ma == 0) |
| 1195 | new_iavg_ma = 1; |
| 1196 | chip->prev_uuc_iavg_ma = new_iavg_ma; |
| 1197 | pr_debug("Restricting UUC to %d (%d%%) unusable_mv = %d iavg_ma = %d\n", |
| 1198 | new_uuc_uah, chip->prev_pc_unusable, |
| 1199 | new_unusable_mv, new_iavg_ma); |
| 1200 | |
| 1201 | return new_uuc_uah; |
| 1202 | } |
| 1203 | |
Abhijeet Dharmapurikar | bdf8ba8 | 2012-12-20 18:33:56 -0800 | [diff] [blame] | 1204 | #define MIN_IAVG_MA 250 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1205 | #define MIN_SECONDS_FOR_VALID_SAMPLE 20 |
| 1206 | static int calculate_unusable_charge_uah(struct qpnp_bms_chip *chip, |
| 1207 | struct soc_params *params, |
| 1208 | int batt_temp) |
| 1209 | { |
| 1210 | int uuc_uah_iavg; |
| 1211 | int i; |
| 1212 | int uuc_iavg_ma = params->iavg_ua / 1000; |
| 1213 | int pc_unusable; |
| 1214 | |
| 1215 | /* |
| 1216 | * if called first time, fill all the samples with |
| 1217 | * the shutdown_iavg_ma |
| 1218 | */ |
| 1219 | if (chip->first_time_calc_uuc && chip->shutdown_iavg_ma != 0) { |
| 1220 | pr_debug("Using shutdown_iavg_ma = %d in all samples\n", |
| 1221 | chip->shutdown_iavg_ma); |
| 1222 | for (i = 0; i < IAVG_SAMPLES; i++) |
| 1223 | chip->iavg_samples_ma[i] = chip->shutdown_iavg_ma; |
| 1224 | |
| 1225 | chip->iavg_index = 0; |
| 1226 | chip->iavg_num_samples = IAVG_SAMPLES; |
| 1227 | } |
| 1228 | |
| 1229 | /* |
| 1230 | * if charging use a nominal avg current to keep |
| 1231 | * a reasonable UUC while charging |
| 1232 | */ |
Abhijeet Dharmapurikar | bdf8ba8 | 2012-12-20 18:33:56 -0800 | [diff] [blame] | 1233 | if (uuc_iavg_ma < MIN_IAVG_MA) |
| 1234 | uuc_iavg_ma = MIN_IAVG_MA; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1235 | chip->iavg_samples_ma[chip->iavg_index] = uuc_iavg_ma; |
| 1236 | chip->iavg_index = (chip->iavg_index + 1) % IAVG_SAMPLES; |
| 1237 | chip->iavg_num_samples++; |
| 1238 | if (chip->iavg_num_samples >= IAVG_SAMPLES) |
| 1239 | chip->iavg_num_samples = IAVG_SAMPLES; |
| 1240 | |
| 1241 | /* now that this sample is added calcualte the average */ |
| 1242 | uuc_iavg_ma = 0; |
| 1243 | if (chip->iavg_num_samples != 0) { |
| 1244 | for (i = 0; i < chip->iavg_num_samples; i++) { |
| 1245 | pr_debug("iavg_samples_ma[%d] = %d\n", i, |
| 1246 | chip->iavg_samples_ma[i]); |
| 1247 | uuc_iavg_ma += chip->iavg_samples_ma[i]; |
| 1248 | } |
| 1249 | |
| 1250 | uuc_iavg_ma = DIV_ROUND_CLOSEST(uuc_iavg_ma, |
| 1251 | chip->iavg_num_samples); |
| 1252 | } |
| 1253 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1254 | /* |
| 1255 | * if we're in bms reset mode, force uuc to be 3% of fcc |
| 1256 | */ |
| 1257 | if (bms_reset) |
| 1258 | return (params->fcc_uah * 3) / 100; |
| 1259 | |
Xiaozhe Shi | 75e5efe | 2013-02-07 09:51:43 -0800 | [diff] [blame] | 1260 | uuc_uah_iavg = calculate_termination_uuc(chip, params, batt_temp, |
| 1261 | uuc_iavg_ma, &pc_unusable); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1262 | pr_debug("uuc_iavg_ma = %d uuc with iavg = %d\n", |
| 1263 | uuc_iavg_ma, uuc_uah_iavg); |
| 1264 | |
| 1265 | chip->prev_uuc_iavg_ma = uuc_iavg_ma; |
| 1266 | /* restrict the uuc such that it can increase only by one percent */ |
| 1267 | uuc_uah_iavg = adjust_uuc(chip, params, pc_unusable, |
| 1268 | uuc_uah_iavg, batt_temp); |
| 1269 | |
| 1270 | chip->first_time_calc_uuc = 0; |
| 1271 | return uuc_uah_iavg; |
| 1272 | } |
| 1273 | |
| 1274 | static void find_ocv_for_soc(struct qpnp_bms_chip *chip, |
| 1275 | struct soc_params *params, |
| 1276 | int batt_temp, |
| 1277 | int shutdown_soc, |
| 1278 | int *ret_ocv_uv) |
| 1279 | { |
| 1280 | s64 ocv_charge_uah; |
| 1281 | int pc, new_pc; |
| 1282 | int batt_temp_degc = batt_temp / 10; |
| 1283 | int ocv_uv; |
| 1284 | |
| 1285 | ocv_charge_uah = (s64)shutdown_soc |
| 1286 | * (params->fcc_uah - params->uuc_uah); |
| 1287 | ocv_charge_uah = div_s64(ocv_charge_uah, 100) |
| 1288 | + params->cc_uah + params->uuc_uah; |
| 1289 | pc = DIV_ROUND_CLOSEST((int)ocv_charge_uah * 100, params->fcc_uah); |
| 1290 | pc = clamp(pc, 0, 100); |
| 1291 | |
| 1292 | ocv_uv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc); |
| 1293 | |
| 1294 | pr_debug("s_soc = %d, fcc = %d uuc = %d rc = %d, pc = %d, ocv mv = %d\n", |
| 1295 | shutdown_soc, params->fcc_uah, |
| 1296 | params->uuc_uah, (int)ocv_charge_uah, |
| 1297 | pc, ocv_uv); |
| 1298 | new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv_uv); |
| 1299 | pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv_uv); |
| 1300 | |
| 1301 | while (abs(new_pc - pc) > 1) { |
| 1302 | int delta_mv = 5; |
| 1303 | |
| 1304 | if (new_pc > pc) |
| 1305 | delta_mv = -1 * delta_mv; |
| 1306 | |
| 1307 | ocv_uv = ocv_uv + delta_mv; |
| 1308 | new_pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 1309 | batt_temp_degc, ocv_uv); |
| 1310 | pr_debug("test revlookup pc = %d for ocv = %d\n", |
| 1311 | new_pc, ocv_uv); |
| 1312 | } |
| 1313 | |
| 1314 | *ret_ocv_uv = ocv_uv * 1000; |
| 1315 | params->ocv_charge_uah = (int)ocv_charge_uah; |
| 1316 | } |
| 1317 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1318 | static int get_current_time(unsigned long *now_tm_sec) |
| 1319 | { |
| 1320 | struct rtc_time tm; |
| 1321 | struct rtc_device *rtc; |
| 1322 | int rc; |
| 1323 | |
| 1324 | rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE); |
| 1325 | if (rtc == NULL) { |
| 1326 | pr_err("%s: unable to open rtc device (%s)\n", |
| 1327 | __FILE__, CONFIG_RTC_HCTOSYS_DEVICE); |
Xiaozhe Shi | 0e01af6 | 2013-05-06 12:56:08 -0700 | [diff] [blame] | 1328 | return -EINVAL; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1329 | } |
| 1330 | |
| 1331 | rc = rtc_read_time(rtc, &tm); |
| 1332 | if (rc) { |
| 1333 | pr_err("Error reading rtc device (%s) : %d\n", |
| 1334 | CONFIG_RTC_HCTOSYS_DEVICE, rc); |
| 1335 | goto close_time; |
| 1336 | } |
| 1337 | |
| 1338 | rc = rtc_valid_tm(&tm); |
| 1339 | if (rc) { |
| 1340 | pr_err("Invalid RTC time (%s): %d\n", |
| 1341 | CONFIG_RTC_HCTOSYS_DEVICE, rc); |
| 1342 | goto close_time; |
| 1343 | } |
| 1344 | rtc_tm_to_time(&tm, now_tm_sec); |
| 1345 | |
| 1346 | close_time: |
| 1347 | rtc_class_close(rtc); |
| 1348 | return rc; |
| 1349 | } |
| 1350 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 1351 | /* Returns estimated battery resistance */ |
| 1352 | static int get_prop_bms_batt_resistance(struct qpnp_bms_chip *chip) |
| 1353 | { |
| 1354 | return chip->rbatt_mohm * 1000; |
| 1355 | } |
| 1356 | |
| 1357 | /* Returns instantaneous current in uA */ |
| 1358 | static int get_prop_bms_current_now(struct qpnp_bms_chip *chip) |
| 1359 | { |
| 1360 | int rc, result_ua; |
| 1361 | |
| 1362 | rc = get_battery_current(chip, &result_ua); |
| 1363 | if (rc) { |
| 1364 | pr_err("failed to get current: %d\n", rc); |
| 1365 | return rc; |
| 1366 | } |
| 1367 | return result_ua; |
| 1368 | } |
| 1369 | |
| 1370 | /* Returns coulomb counter in uAh */ |
| 1371 | static int get_prop_bms_charge_counter(struct qpnp_bms_chip *chip) |
| 1372 | { |
| 1373 | int64_t cc_raw; |
| 1374 | |
| 1375 | mutex_lock(&chip->bms_output_lock); |
| 1376 | lock_output_data(chip); |
| 1377 | read_cc_raw(chip, &cc_raw, false); |
| 1378 | unlock_output_data(chip); |
| 1379 | mutex_unlock(&chip->bms_output_lock); |
| 1380 | |
| 1381 | return calculate_cc(chip, cc_raw, CC, NORESET); |
| 1382 | } |
| 1383 | |
| 1384 | /* Returns shadow coulomb counter in uAh */ |
| 1385 | static int get_prop_bms_charge_counter_shadow(struct qpnp_bms_chip *chip) |
| 1386 | { |
| 1387 | int64_t cc_raw; |
| 1388 | |
| 1389 | mutex_lock(&chip->bms_output_lock); |
| 1390 | lock_output_data(chip); |
| 1391 | read_cc_raw(chip, &cc_raw, true); |
| 1392 | unlock_output_data(chip); |
| 1393 | mutex_unlock(&chip->bms_output_lock); |
| 1394 | |
| 1395 | return calculate_cc(chip, cc_raw, SHDW_CC, NORESET); |
| 1396 | } |
| 1397 | |
| 1398 | /* Returns full charge design in uAh */ |
| 1399 | static int get_prop_bms_charge_full_design(struct qpnp_bms_chip *chip) |
| 1400 | { |
| 1401 | return chip->fcc_mah * 1000; |
| 1402 | } |
| 1403 | |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 1404 | /* Returns the current full charge in uAh */ |
| 1405 | static int get_prop_bms_charge_full(struct qpnp_bms_chip *chip) |
| 1406 | { |
| 1407 | int rc; |
| 1408 | struct qpnp_vadc_result result; |
| 1409 | |
| 1410 | rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result); |
| 1411 | if (rc) { |
| 1412 | pr_err("Unable to read battery temperature\n"); |
| 1413 | return rc; |
| 1414 | } |
| 1415 | |
| 1416 | return calculate_fcc(chip, (int)result.physical); |
| 1417 | } |
| 1418 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1419 | static int calculate_delta_time(unsigned long *time_stamp, int *delta_time_s) |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1420 | { |
| 1421 | unsigned long now_tm_sec = 0; |
| 1422 | |
| 1423 | /* default to delta time = 0 if anything fails */ |
| 1424 | *delta_time_s = 0; |
| 1425 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1426 | if (get_current_time(&now_tm_sec)) { |
| 1427 | pr_err("RTC read failed\n"); |
| 1428 | return 0; |
| 1429 | } |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1430 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1431 | *delta_time_s = (now_tm_sec - *time_stamp); |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1432 | |
| 1433 | /* remember this time */ |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1434 | *time_stamp = now_tm_sec; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1435 | return 0; |
| 1436 | } |
| 1437 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1438 | static void calculate_soc_params(struct qpnp_bms_chip *chip, |
| 1439 | struct raw_soc_params *raw, |
| 1440 | struct soc_params *params, |
| 1441 | int batt_temp) |
| 1442 | { |
Xiaozhe Shi | 219cb22 | 2013-06-10 15:49:59 -0700 | [diff] [blame] | 1443 | int soc_rbatt, shdw_cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1444 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1445 | calculate_delta_time(&chip->tm_sec, ¶ms->delta_time_s); |
| 1446 | pr_debug("tm_sec = %ld, delta_s = %d\n", |
| 1447 | chip->tm_sec, params->delta_time_s); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1448 | params->fcc_uah = calculate_fcc(chip, batt_temp); |
| 1449 | pr_debug("FCC = %uuAh batt_temp = %d\n", params->fcc_uah, batt_temp); |
| 1450 | |
| 1451 | /* calculate remainging charge */ |
| 1452 | params->ocv_charge_uah = calculate_ocv_charge( |
| 1453 | chip, raw, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1454 | params->fcc_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1455 | pr_debug("ocv_charge_uah = %uuAh\n", params->ocv_charge_uah); |
| 1456 | |
| 1457 | /* calculate cc micro_volt_hour */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1458 | params->cc_uah = calculate_cc(chip, raw->cc, CC, RESET); |
Xiaozhe Shi | 219cb22 | 2013-06-10 15:49:59 -0700 | [diff] [blame] | 1459 | shdw_cc_uah = calculate_cc(chip, raw->shdw_cc, SHDW_CC, RESET); |
| 1460 | pr_debug("cc_uah = %duAh raw->cc = %llx, shdw_cc_uah = %duAh raw->shdw_cc = %llx\n", |
| 1461 | params->cc_uah, raw->cc, |
| 1462 | shdw_cc_uah, raw->shdw_cc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1463 | |
| 1464 | soc_rbatt = ((params->ocv_charge_uah - params->cc_uah) * 100) |
| 1465 | / params->fcc_uah; |
| 1466 | if (soc_rbatt < 0) |
| 1467 | soc_rbatt = 0; |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 1468 | params->rbatt_mohm = get_rbatt(chip, soc_rbatt, batt_temp); |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1469 | pr_debug("rbatt_mohm = %d\n", params->rbatt_mohm); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1470 | |
Xiaozhe Shi | 1e87cda | 2013-05-17 10:18:56 -0700 | [diff] [blame] | 1471 | if (params->rbatt_mohm != chip->rbatt_mohm) { |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 1472 | chip->rbatt_mohm = params->rbatt_mohm; |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 1473 | if (chip->bms_psy_registered) |
Xiaozhe Shi | 1e87cda | 2013-05-17 10:18:56 -0700 | [diff] [blame] | 1474 | power_supply_changed(&chip->bms_psy); |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 1475 | } |
| 1476 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1477 | calculate_iavg(chip, params->cc_uah, ¶ms->iavg_ua, |
| 1478 | params->delta_time_s); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1479 | |
| 1480 | params->uuc_uah = calculate_unusable_charge_uah(chip, params, |
| 1481 | batt_temp); |
| 1482 | pr_debug("UUC = %uuAh\n", params->uuc_uah); |
| 1483 | } |
| 1484 | |
| 1485 | static bool is_shutdown_soc_within_limits(struct qpnp_bms_chip *chip, int soc) |
| 1486 | { |
| 1487 | if (chip->shutdown_soc_invalid) { |
| 1488 | pr_debug("NOT forcing shutdown soc = %d\n", chip->shutdown_soc); |
| 1489 | return 0; |
| 1490 | } |
| 1491 | |
| 1492 | if (abs(chip->shutdown_soc - soc) > chip->shutdown_soc_valid_limit) { |
| 1493 | pr_debug("rejecting shutdown soc = %d, soc = %d limit = %d\n", |
| 1494 | chip->shutdown_soc, soc, |
| 1495 | chip->shutdown_soc_valid_limit); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 1496 | chip->shutdown_soc_invalid = true; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1497 | return 0; |
| 1498 | } |
| 1499 | |
| 1500 | return 1; |
| 1501 | } |
| 1502 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1503 | static int bound_soc(int soc) |
| 1504 | { |
| 1505 | soc = max(0, soc); |
| 1506 | soc = min(100, soc); |
| 1507 | return soc; |
| 1508 | } |
| 1509 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1510 | #define IBAT_TOL_MASK 0x0F |
| 1511 | #define OCV_TOL_MASK 0xF0 |
| 1512 | #define IBAT_TOL_DEFAULT 0x03 |
| 1513 | #define IBAT_TOL_NOCHG 0x0F |
| 1514 | #define OCV_TOL_DEFAULT 0x20 |
| 1515 | #define OCV_TOL_NO_OCV 0x00 |
| 1516 | static int stop_ocv_updates(struct qpnp_bms_chip *chip) |
| 1517 | { |
| 1518 | pr_debug("stopping ocv updates\n"); |
| 1519 | return qpnp_masked_write(chip, BMS1_TOL_CTL, |
| 1520 | OCV_TOL_MASK, OCV_TOL_NO_OCV); |
| 1521 | } |
| 1522 | |
| 1523 | static int reset_bms_for_test(struct qpnp_bms_chip *chip) |
| 1524 | { |
Xiaozhe Shi | 95da77f | 2013-02-20 13:40:06 -0800 | [diff] [blame] | 1525 | int ibat_ua = 0, vbat_uv = 0, rc; |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1526 | int ocv_est_uv; |
| 1527 | |
| 1528 | if (!chip) { |
| 1529 | pr_err("BMS driver has not been initialized yet!\n"); |
| 1530 | return -EINVAL; |
| 1531 | } |
| 1532 | |
| 1533 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 1534 | |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 1535 | /* |
| 1536 | * Don't include rbatt and rbatt_capacitative since we expect this to |
| 1537 | * be used with a fake battery which does not have internal resistances |
| 1538 | */ |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1539 | ocv_est_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000; |
| 1540 | pr_debug("forcing ocv to be %d due to bms reset mode\n", ocv_est_uv); |
| 1541 | chip->last_ocv_uv = ocv_est_uv; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1542 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1543 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 1544 | chip->last_soc_invalid = true; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1545 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1546 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1547 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1548 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1549 | chip->last_cc_uah = INT_MIN; |
| 1550 | stop_ocv_updates(chip); |
| 1551 | |
| 1552 | pr_debug("bms reset to ocv = %duv vbat_ua = %d ibat_ua = %d\n", |
| 1553 | chip->last_ocv_uv, vbat_uv, ibat_ua); |
| 1554 | |
| 1555 | return rc; |
| 1556 | } |
| 1557 | |
| 1558 | static int bms_reset_set(const char *val, const struct kernel_param *kp) |
| 1559 | { |
| 1560 | int rc; |
| 1561 | |
| 1562 | rc = param_set_bool(val, kp); |
| 1563 | if (rc) { |
| 1564 | pr_err("Unable to set bms_reset: %d\n", rc); |
| 1565 | return rc; |
| 1566 | } |
| 1567 | |
| 1568 | if (*(bool *)kp->arg) { |
| 1569 | struct power_supply *bms_psy = power_supply_get_by_name("bms"); |
| 1570 | struct qpnp_bms_chip *chip = container_of(bms_psy, |
| 1571 | struct qpnp_bms_chip, bms_psy); |
| 1572 | |
| 1573 | rc = reset_bms_for_test(chip); |
| 1574 | if (rc) { |
| 1575 | pr_err("Unable to modify bms_reset: %d\n", rc); |
| 1576 | return rc; |
| 1577 | } |
| 1578 | } |
| 1579 | return 0; |
| 1580 | } |
| 1581 | |
| 1582 | static struct kernel_param_ops bms_reset_ops = { |
| 1583 | .set = bms_reset_set, |
| 1584 | .get = param_get_bool, |
| 1585 | }; |
| 1586 | |
| 1587 | module_param_cb(bms_reset, &bms_reset_ops, &bms_reset, 0644); |
| 1588 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1589 | static void backup_soc_and_iavg(struct qpnp_bms_chip *chip, int batt_temp, |
| 1590 | int soc) |
| 1591 | { |
| 1592 | u8 temp; |
| 1593 | int rc; |
| 1594 | int iavg_ma = chip->prev_uuc_iavg_ma; |
| 1595 | |
| 1596 | if (iavg_ma > IAVG_START) |
| 1597 | temp = (iavg_ma - IAVG_START) / IAVG_STEP_SIZE_MA; |
| 1598 | else |
| 1599 | temp = 0; |
| 1600 | |
| 1601 | rc = qpnp_write_wrapper(chip, &temp, |
| 1602 | chip->base + IAVG_STORAGE_REG, 1); |
| 1603 | |
| 1604 | temp = soc; |
| 1605 | |
| 1606 | /* don't store soc if temperature is below 5degC */ |
| 1607 | if (batt_temp > IGNORE_SOC_TEMP_DECIDEG) |
| 1608 | rc = qpnp_write_wrapper(chip, &temp, |
| 1609 | chip->base + SOC_STORAGE_REG, 1); |
| 1610 | } |
| 1611 | |
| 1612 | static int scale_soc_while_chg(struct qpnp_bms_chip *chip, int chg_time_sec, |
| 1613 | int catch_up_sec, int new_soc, int prev_soc) |
| 1614 | { |
| 1615 | int scaled_soc; |
| 1616 | int numerator; |
| 1617 | |
| 1618 | /* |
| 1619 | * Don't report a high value immediately slowly scale the |
| 1620 | * value from prev_soc to the new soc based on a charge time |
| 1621 | * weighted average |
| 1622 | */ |
| 1623 | pr_debug("cts = %d catch_up_sec = %d\n", chg_time_sec, catch_up_sec); |
| 1624 | if (catch_up_sec == 0) |
| 1625 | return new_soc; |
| 1626 | |
| 1627 | if (chg_time_sec > catch_up_sec) |
| 1628 | return new_soc; |
| 1629 | |
| 1630 | numerator = (catch_up_sec - chg_time_sec) * prev_soc |
| 1631 | + chg_time_sec * new_soc; |
| 1632 | scaled_soc = numerator / catch_up_sec; |
| 1633 | |
| 1634 | pr_debug("cts = %d new_soc = %d prev_soc = %d scaled_soc = %d\n", |
| 1635 | chg_time_sec, new_soc, prev_soc, scaled_soc); |
| 1636 | |
| 1637 | return scaled_soc; |
| 1638 | } |
| 1639 | |
| 1640 | /* |
| 1641 | * bms_fake_battery is set in setups where a battery emulator is used instead |
| 1642 | * of a real battery. This makes the bms driver report a different/fake value |
| 1643 | * regardless of the calculated state of charge. |
| 1644 | */ |
| 1645 | static int bms_fake_battery = -EINVAL; |
| 1646 | module_param(bms_fake_battery, int, 0644); |
| 1647 | |
| 1648 | static int report_voltage_based_soc(struct qpnp_bms_chip *chip) |
| 1649 | { |
| 1650 | pr_debug("Reported voltage based soc = %d\n", |
| 1651 | chip->prev_voltage_based_soc); |
| 1652 | return chip->prev_voltage_based_soc; |
| 1653 | } |
| 1654 | |
| 1655 | #define SOC_CATCHUP_SEC_MAX 600 |
| 1656 | #define SOC_CATCHUP_SEC_PER_PERCENT 60 |
| 1657 | #define MAX_CATCHUP_SOC (SOC_CATCHUP_SEC_MAX / SOC_CATCHUP_SEC_PER_PERCENT) |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 1658 | #define SOC_CHANGE_PER_SEC 5 |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1659 | static int report_cc_based_soc(struct qpnp_bms_chip *chip) |
| 1660 | { |
| 1661 | int soc, soc_change; |
| 1662 | int time_since_last_change_sec, charge_time_sec = 0; |
| 1663 | unsigned long last_change_sec; |
| 1664 | struct timespec now; |
| 1665 | struct qpnp_vadc_result result; |
| 1666 | int batt_temp; |
| 1667 | int rc; |
| 1668 | bool charging, charging_since_last_report; |
| 1669 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1670 | rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result); |
| 1671 | |
| 1672 | if (rc) { |
| 1673 | pr_err("error reading adc channel = %d, rc = %d\n", |
| 1674 | LR_MUX1_BATT_THERM, rc); |
| 1675 | return rc; |
| 1676 | } |
| 1677 | pr_debug("batt_temp phy = %lld meas = 0x%llx\n", result.physical, |
| 1678 | result.measurement); |
| 1679 | batt_temp = (int)result.physical; |
| 1680 | |
| 1681 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | fa6ea69 | 2013-05-31 11:15:13 -0700 | [diff] [blame] | 1682 | soc = chip->calculated_soc; |
| 1683 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1684 | last_change_sec = chip->last_soc_change_sec; |
| 1685 | calculate_delta_time(&last_change_sec, &time_since_last_change_sec); |
| 1686 | |
| 1687 | charging = is_battery_charging(chip); |
| 1688 | charging_since_last_report = charging || (chip->last_soc_unbound |
| 1689 | && chip->was_charging_at_sleep); |
| 1690 | /* |
| 1691 | * account for charge time - limit it to SOC_CATCHUP_SEC to |
| 1692 | * avoid overflows when charging continues for extended periods |
| 1693 | */ |
| 1694 | if (charging) { |
| 1695 | if (chip->charge_start_tm_sec == 0) { |
| 1696 | /* |
| 1697 | * calculating soc for the first time |
| 1698 | * after start of chg. Initialize catchup time |
| 1699 | */ |
| 1700 | if (abs(soc - chip->last_soc) < MAX_CATCHUP_SOC) |
| 1701 | chip->catch_up_time_sec = |
| 1702 | (soc - chip->last_soc) |
| 1703 | * SOC_CATCHUP_SEC_PER_PERCENT; |
| 1704 | else |
| 1705 | chip->catch_up_time_sec = SOC_CATCHUP_SEC_MAX; |
| 1706 | |
| 1707 | if (chip->catch_up_time_sec < 0) |
| 1708 | chip->catch_up_time_sec = 0; |
| 1709 | chip->charge_start_tm_sec = last_change_sec; |
| 1710 | } |
| 1711 | |
| 1712 | charge_time_sec = min(SOC_CATCHUP_SEC_MAX, (int)last_change_sec |
| 1713 | - chip->charge_start_tm_sec); |
| 1714 | |
| 1715 | /* end catchup if calculated soc and last soc are same */ |
| 1716 | if (chip->last_soc == soc) |
| 1717 | chip->catch_up_time_sec = 0; |
| 1718 | } |
| 1719 | |
| 1720 | if (chip->last_soc != -EINVAL) { |
| 1721 | /* |
| 1722 | * last_soc < soc ... if we have not been charging at all |
| 1723 | * since the last time this was called, report previous SoC. |
| 1724 | * Otherwise, scale and catch up. |
| 1725 | */ |
| 1726 | if (chip->last_soc < soc && !charging_since_last_report) |
| 1727 | soc = chip->last_soc; |
| 1728 | else if (chip->last_soc < soc && soc != 100) |
| 1729 | soc = scale_soc_while_chg(chip, charge_time_sec, |
| 1730 | chip->catch_up_time_sec, |
| 1731 | soc, chip->last_soc); |
| 1732 | |
| 1733 | soc_change = min((int)abs(chip->last_soc - soc), |
| 1734 | time_since_last_change_sec / SOC_CHANGE_PER_SEC); |
| 1735 | if (chip->last_soc_unbound) { |
| 1736 | chip->last_soc_unbound = false; |
| 1737 | } else { |
| 1738 | /* |
| 1739 | * if soc have not been unbound by resume, |
| 1740 | * only change reported SoC by 1. |
| 1741 | */ |
| 1742 | soc_change = min(1, soc_change); |
| 1743 | } |
| 1744 | |
| 1745 | if (soc < chip->last_soc && soc != 0) |
| 1746 | soc = chip->last_soc - soc_change; |
| 1747 | if (soc > chip->last_soc && soc != 100) |
| 1748 | soc = chip->last_soc + soc_change; |
| 1749 | } |
| 1750 | |
Xiaozhe Shi | 208b8e5 | 2013-05-28 10:16:32 -0700 | [diff] [blame] | 1751 | if (chip->last_soc != soc && !chip->last_soc_unbound) |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1752 | chip->last_soc_change_sec = last_change_sec; |
| 1753 | |
| 1754 | pr_debug("last_soc = %d, calculated_soc = %d, soc = %d, time since last change = %d\n", |
| 1755 | chip->last_soc, chip->calculated_soc, |
| 1756 | soc, time_since_last_change_sec); |
| 1757 | chip->last_soc = bound_soc(soc); |
| 1758 | backup_soc_and_iavg(chip, batt_temp, chip->last_soc); |
| 1759 | pr_debug("Reported SOC = %d\n", chip->last_soc); |
| 1760 | chip->t_soc_queried = now; |
| 1761 | mutex_unlock(&chip->last_soc_mutex); |
| 1762 | |
| 1763 | return soc; |
| 1764 | } |
| 1765 | |
| 1766 | static int report_state_of_charge(struct qpnp_bms_chip *chip) |
| 1767 | { |
| 1768 | if (bms_fake_battery != -EINVAL) { |
| 1769 | pr_debug("Returning Fake SOC = %d%%\n", bms_fake_battery); |
| 1770 | return bms_fake_battery; |
| 1771 | } else if (chip->use_voltage_soc) |
| 1772 | return report_voltage_based_soc(chip); |
| 1773 | else |
| 1774 | return report_cc_based_soc(chip); |
| 1775 | } |
| 1776 | |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1777 | #define VDD_MAX_ERR 5000 |
| 1778 | #define VDD_STEP_SIZE 10000 |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1779 | static int charging_adjustments(struct qpnp_bms_chip *chip, |
| 1780 | struct soc_params *params, int soc, |
| 1781 | int vbat_uv, int ibat_ua, int batt_temp) |
| 1782 | { |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1783 | int chg_soc, soc_ibat, batt_terminal_uv, weight_ibat, weight_cc; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1784 | |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1785 | batt_terminal_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1786 | |
| 1787 | if (chip->soc_at_cv == -EINVAL) { |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1788 | if (batt_terminal_uv >= chip->max_voltage_uv - VDD_MAX_ERR) { |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1789 | chip->soc_at_cv = soc; |
| 1790 | chip->prev_chg_soc = soc; |
| 1791 | chip->ibat_at_cv_ua = ibat_ua; |
| 1792 | pr_debug("CC_TO_CV ibat_ua = %d CHG SOC %d\n", |
| 1793 | ibat_ua, soc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1794 | } else { |
| 1795 | /* In constant current charging return the calc soc */ |
| 1796 | pr_debug("CC CHG SOC %d\n", soc); |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1797 | } |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1798 | |
| 1799 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1800 | return soc; |
| 1801 | } |
| 1802 | |
| 1803 | /* |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1804 | * battery is in CV phase - begin linear interpolation of soc based on |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1805 | * battery charge current |
| 1806 | */ |
| 1807 | |
| 1808 | /* |
| 1809 | * if voltage lessened (possibly because of a system load) |
| 1810 | * keep reporting the prev chg soc |
| 1811 | */ |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1812 | if (batt_terminal_uv <= chip->prev_batt_terminal_uv - VDD_STEP_SIZE) { |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 1813 | pr_debug("batt_terminal_uv %d < (max = %d - 10000); CC CHG SOC %d\n", |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1814 | batt_terminal_uv, chip->prev_batt_terminal_uv, |
| 1815 | chip->prev_chg_soc); |
| 1816 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1817 | return chip->prev_chg_soc; |
| 1818 | } |
| 1819 | |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1820 | soc_ibat = bound_soc(linear_interpolate(chip->soc_at_cv, |
| 1821 | chip->ibat_at_cv_ua, |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 1822 | 100, -1 * chip->chg_term_ua, |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1823 | ibat_ua)); |
| 1824 | weight_ibat = bound_soc(linear_interpolate(1, chip->soc_at_cv, |
| 1825 | 100, 100, chip->prev_chg_soc)); |
| 1826 | weight_cc = 100 - weight_ibat; |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1827 | chg_soc = bound_soc(DIV_ROUND_CLOSEST(soc_ibat * weight_ibat |
| 1828 | + weight_cc * soc, 100)); |
| 1829 | |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1830 | pr_debug("weight_ibat = %d, weight_cc = %d, soc_ibat = %d, soc_cc = %d\n", |
| 1831 | weight_ibat, weight_cc, soc_ibat, soc); |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1832 | |
| 1833 | /* always report a higher soc */ |
| 1834 | if (chg_soc > chip->prev_chg_soc) { |
| 1835 | int new_ocv_uv; |
| 1836 | |
| 1837 | chip->prev_chg_soc = chg_soc; |
| 1838 | |
| 1839 | find_ocv_for_soc(chip, params, batt_temp, chg_soc, &new_ocv_uv); |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 1840 | chip->charging_adjusted_ocv = new_ocv_uv; |
| 1841 | pr_debug("CC CHG ADJ OCV = %d CHG SOC %d\n", new_ocv_uv, |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1842 | chip->prev_chg_soc); |
| 1843 | } |
| 1844 | |
| 1845 | pr_debug("Reporting CHG SOC %d\n", chip->prev_chg_soc); |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1846 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1847 | return chip->prev_chg_soc; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1848 | } |
| 1849 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1850 | static void very_low_voltage_check(struct qpnp_bms_chip *chip, int vbat_uv) |
| 1851 | { |
| 1852 | /* |
| 1853 | * if battery is very low (v_cutoff voltage + 20mv) hold |
| 1854 | * a wakelock untill soc = 0% |
| 1855 | */ |
| 1856 | if (vbat_uv <= chip->low_voltage_threshold |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1857 | && !wake_lock_active(&chip->low_voltage_wake_lock)) { |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1858 | pr_debug("voltage = %d low holding wakelock\n", vbat_uv); |
| 1859 | wake_lock(&chip->low_voltage_wake_lock); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1860 | } else if (vbat_uv > chip->low_voltage_threshold |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1861 | && wake_lock_active(&chip->low_voltage_wake_lock)) { |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1862 | pr_debug("voltage = %d releasing wakelock\n", vbat_uv); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1863 | wake_unlock(&chip->low_voltage_wake_lock); |
| 1864 | } |
| 1865 | } |
| 1866 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1867 | #define VBATT_ERROR_MARGIN 20000 |
| 1868 | static void cv_voltage_check(struct qpnp_bms_chip *chip, int vbat_uv) |
| 1869 | { |
| 1870 | /* |
| 1871 | * if battery is very low (v_cutoff voltage + 20mv) hold |
| 1872 | * a wakelock untill soc = 0% |
| 1873 | */ |
| 1874 | if (wake_lock_active(&chip->cv_wake_lock)) { |
| 1875 | if (chip->soc_at_cv != -EINVAL) { |
| 1876 | pr_debug("hit CV, releasing cv wakelock\n"); |
| 1877 | wake_unlock(&chip->cv_wake_lock); |
| 1878 | } else if (!is_battery_charging(chip)) { |
| 1879 | pr_debug("charging stopped, releasing cv wakelock\n"); |
| 1880 | wake_unlock(&chip->cv_wake_lock); |
| 1881 | } |
| 1882 | } else if (vbat_uv > chip->max_voltage_uv - VBATT_ERROR_MARGIN |
| 1883 | && chip->soc_at_cv == -EINVAL |
| 1884 | && is_battery_charging(chip) |
| 1885 | && !wake_lock_active(&chip->cv_wake_lock)) { |
| 1886 | pr_debug("voltage = %d holding cv wakelock\n", vbat_uv); |
| 1887 | wake_lock(&chip->cv_wake_lock); |
| 1888 | } |
| 1889 | } |
| 1890 | |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 1891 | #define NO_ADJUST_HIGH_SOC_THRESHOLD 90 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1892 | static int adjust_soc(struct qpnp_bms_chip *chip, struct soc_params *params, |
| 1893 | int soc, int batt_temp) |
| 1894 | { |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1895 | int ibat_ua = 0, vbat_uv = 0; |
| 1896 | int ocv_est_uv = 0, soc_est = 0, pc_est = 0, pc = 0; |
| 1897 | int delta_ocv_uv = 0; |
| 1898 | int n = 0; |
| 1899 | int rc_new_uah = 0; |
| 1900 | int pc_new = 0; |
| 1901 | int soc_new = 0; |
| 1902 | int slope = 0; |
| 1903 | int rc = 0; |
| 1904 | int delta_ocv_uv_limit = 0; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 1905 | int correction_limit_uv = 0; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1906 | |
| 1907 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 1908 | if (rc < 0) { |
| 1909 | pr_err("simultaneous vbat ibat failed err = %d\n", rc); |
| 1910 | goto out; |
| 1911 | } |
| 1912 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1913 | very_low_voltage_check(chip, vbat_uv); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1914 | cv_voltage_check(chip, vbat_uv); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1915 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1916 | delta_ocv_uv_limit = DIV_ROUND_CLOSEST(ibat_ua, 1000); |
| 1917 | |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 1918 | ocv_est_uv = vbat_uv + (ibat_ua * params->rbatt_mohm)/1000; |
| 1919 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1920 | pc_est = calculate_pc(chip, ocv_est_uv, batt_temp); |
| 1921 | soc_est = div_s64((s64)params->fcc_uah * pc_est - params->uuc_uah*100, |
| 1922 | (s64)params->fcc_uah - params->uuc_uah); |
| 1923 | soc_est = bound_soc(soc_est); |
| 1924 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1925 | /* never adjust during bms reset mode */ |
| 1926 | if (bms_reset) { |
| 1927 | pr_debug("bms reset mode, SOC adjustment skipped\n"); |
| 1928 | goto out; |
| 1929 | } |
| 1930 | |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 1931 | if (ibat_ua < 0 && !is_battery_full(chip)) { |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1932 | soc = charging_adjustments(chip, params, soc, vbat_uv, ibat_ua, |
| 1933 | batt_temp); |
| 1934 | goto out; |
| 1935 | } |
| 1936 | |
| 1937 | /* |
| 1938 | * do not adjust |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 1939 | * if soc_est is same as what bms calculated |
| 1940 | * OR if soc_est > adjust_soc_low_threshold |
| 1941 | * OR if soc is above 90 |
| 1942 | * because we might pull it low |
| 1943 | * and cause a bad user experience |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1944 | */ |
| 1945 | if (soc_est == soc |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 1946 | || soc_est > chip->adjust_soc_low_threshold |
| 1947 | || soc >= NO_ADJUST_HIGH_SOC_THRESHOLD) |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1948 | goto out; |
| 1949 | |
| 1950 | if (chip->last_soc_est == -EINVAL) |
| 1951 | chip->last_soc_est = soc; |
| 1952 | |
| 1953 | n = min(200, max(1 , soc + soc_est + chip->last_soc_est)); |
| 1954 | chip->last_soc_est = soc_est; |
| 1955 | |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1956 | pc = calculate_pc(chip, chip->last_ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1957 | if (pc > 0) { |
| 1958 | pc_new = calculate_pc(chip, |
| 1959 | chip->last_ocv_uv - (++slope * 1000), |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1960 | chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1961 | while (pc_new == pc) { |
| 1962 | /* start taking 10mV steps */ |
| 1963 | slope = slope + 10; |
| 1964 | pc_new = calculate_pc(chip, |
| 1965 | chip->last_ocv_uv - (slope * 1000), |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1966 | chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1967 | } |
| 1968 | } else { |
| 1969 | /* |
| 1970 | * pc is already at the lowest point, |
| 1971 | * assume 1 millivolt translates to 1% pc |
| 1972 | */ |
| 1973 | pc = 1; |
| 1974 | pc_new = 0; |
| 1975 | slope = 1; |
| 1976 | } |
| 1977 | |
| 1978 | delta_ocv_uv = div_s64((soc - soc_est) * (s64)slope * 1000, |
| 1979 | n * (pc - pc_new)); |
| 1980 | |
| 1981 | if (abs(delta_ocv_uv) > delta_ocv_uv_limit) { |
| 1982 | pr_debug("limiting delta ocv %d limit = %d\n", delta_ocv_uv, |
| 1983 | delta_ocv_uv_limit); |
| 1984 | |
| 1985 | if (delta_ocv_uv > 0) |
| 1986 | delta_ocv_uv = delta_ocv_uv_limit; |
| 1987 | else |
| 1988 | delta_ocv_uv = -1 * delta_ocv_uv_limit; |
| 1989 | pr_debug("new delta ocv = %d\n", delta_ocv_uv); |
| 1990 | } |
| 1991 | |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 1992 | if (chip->last_ocv_uv > chip->flat_ocv_threshold_uv) |
| 1993 | correction_limit_uv = chip->high_ocv_correction_limit_uv; |
| 1994 | else |
| 1995 | correction_limit_uv = chip->low_ocv_correction_limit_uv; |
| 1996 | |
| 1997 | if (abs(delta_ocv_uv) > correction_limit_uv) { |
| 1998 | pr_debug("limiting delta ocv %d limit = %d\n", |
| 1999 | delta_ocv_uv, correction_limit_uv); |
| 2000 | if (delta_ocv_uv > 0) |
| 2001 | delta_ocv_uv = correction_limit_uv; |
| 2002 | else |
| 2003 | delta_ocv_uv = -correction_limit_uv; |
| 2004 | pr_debug("new delta ocv = %d\n", delta_ocv_uv); |
| 2005 | } |
| 2006 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2007 | chip->last_ocv_uv -= delta_ocv_uv; |
| 2008 | |
| 2009 | if (chip->last_ocv_uv >= chip->max_voltage_uv) |
| 2010 | chip->last_ocv_uv = chip->max_voltage_uv; |
| 2011 | |
| 2012 | /* calculate the soc based on this new ocv */ |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 2013 | pc_new = calculate_pc(chip, chip->last_ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2014 | rc_new_uah = (params->fcc_uah * pc_new) / 100; |
| 2015 | soc_new = (rc_new_uah - params->cc_uah - params->uuc_uah)*100 |
| 2016 | / (params->fcc_uah - params->uuc_uah); |
| 2017 | soc_new = bound_soc(soc_new); |
| 2018 | |
| 2019 | /* |
| 2020 | * if soc_new is ZERO force it higher so that phone doesnt report soc=0 |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2021 | * soc = 0 should happen only when soc_est is above a set value |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2022 | */ |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2023 | if (soc_new == 0 && soc_est >= chip->hold_soc_est) |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2024 | soc_new = 1; |
| 2025 | |
| 2026 | soc = soc_new; |
| 2027 | |
| 2028 | out: |
| 2029 | pr_debug("ibat_ua = %d, vbat_uv = %d, ocv_est_uv = %d, pc_est = %d, soc_est = %d, n = %d, delta_ocv_uv = %d, last_ocv_uv = %d, pc_new = %d, soc_new = %d, rbatt = %d, slope = %d\n", |
| 2030 | ibat_ua, vbat_uv, ocv_est_uv, pc_est, |
| 2031 | soc_est, n, delta_ocv_uv, chip->last_ocv_uv, |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 2032 | pc_new, soc_new, params->rbatt_mohm, slope); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2033 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2034 | return soc; |
| 2035 | } |
| 2036 | |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2037 | static int clamp_soc_based_on_voltage(struct qpnp_bms_chip *chip, int soc) |
| 2038 | { |
| 2039 | int rc, vbat_uv; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2040 | |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2041 | rc = get_battery_voltage(&vbat_uv); |
| 2042 | if (rc < 0) { |
| 2043 | pr_err("adc vbat failed err = %d\n", rc); |
| 2044 | return soc; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2045 | } |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2046 | if (soc == 0 && vbat_uv > chip->v_cutoff_uv) { |
| 2047 | pr_debug("clamping soc to 1, vbat (%d) > cutoff (%d)\n", |
| 2048 | vbat_uv, chip->v_cutoff_uv); |
| 2049 | return 1; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2050 | } else { |
| 2051 | pr_debug("not clamping, using soc = %d, vbat = %d and cutoff = %d\n", |
| 2052 | soc, vbat_uv, chip->v_cutoff_uv); |
| 2053 | return soc; |
| 2054 | } |
| 2055 | } |
| 2056 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2057 | static int64_t convert_cc_uah_to_raw(struct qpnp_bms_chip *chip, int64_t cc_uah) |
| 2058 | { |
| 2059 | int64_t cc_uv, cc_pvh, cc_raw; |
| 2060 | |
| 2061 | cc_pvh = cc_uah * chip->r_sense_uohm; |
| 2062 | cc_uv = div_s64(cc_pvh * SLEEP_CLK_HZ * SECONDS_PER_HOUR, |
| 2063 | CC_READING_TICKS * 1000000LL); |
| 2064 | cc_raw = div_s64(cc_uv * CC_READING_RESOLUTION_D, |
| 2065 | CC_READING_RESOLUTION_N); |
| 2066 | return cc_raw; |
| 2067 | } |
| 2068 | |
| 2069 | #define CC_STEP_INCREMENT_UAH 1500 |
| 2070 | #define OCV_STEP_INCREMENT 0x10 |
| 2071 | static void configure_soc_wakeup(struct qpnp_bms_chip *chip, |
| 2072 | struct soc_params *params, |
| 2073 | int batt_temp, int target_soc) |
| 2074 | { |
| 2075 | int target_ocv_uv; |
| 2076 | int64_t target_cc_uah, cc_raw_64, current_shdw_cc_raw_64; |
| 2077 | int64_t current_shdw_cc_uah, iadc_comp_factor; |
| 2078 | uint64_t cc_raw, current_shdw_cc_raw; |
| 2079 | int16_t ocv_raw, current_ocv_raw; |
| 2080 | |
| 2081 | current_shdw_cc_raw = 0; |
| 2082 | mutex_lock(&chip->bms_output_lock); |
| 2083 | lock_output_data(chip); |
| 2084 | qpnp_read_wrapper(chip, (u8 *)¤t_ocv_raw, |
| 2085 | chip->base + BMS1_OCV_FOR_SOC_DATA0, 2); |
| 2086 | unlock_output_data(chip); |
| 2087 | mutex_unlock(&chip->bms_output_lock); |
| 2088 | current_shdw_cc_uah = get_prop_bms_charge_counter_shadow(chip); |
| 2089 | current_shdw_cc_raw_64 = convert_cc_uah_to_raw(chip, |
| 2090 | current_shdw_cc_uah); |
| 2091 | |
| 2092 | /* |
| 2093 | * Calculate the target shadow coulomb counter threshold for when |
| 2094 | * the SoC changes. |
| 2095 | * |
| 2096 | * Since the BMS driver resets the shadow coulomb counter every |
| 2097 | * 20 seconds when the device is awake, calculate the threshold as |
| 2098 | * a delta from the current shadow coulomb count. |
| 2099 | */ |
| 2100 | target_cc_uah = (100 - target_soc) |
| 2101 | * (params->fcc_uah - params->uuc_uah) |
| 2102 | / 100 - current_shdw_cc_uah; |
| 2103 | if (target_cc_uah < 0) { |
| 2104 | /* |
| 2105 | * If the target cc is below 0, that means we have already |
| 2106 | * passed the point where SoC should have fallen. |
| 2107 | * Set a wakeup in a few more mAh and check back again |
| 2108 | */ |
| 2109 | target_cc_uah = CC_STEP_INCREMENT_UAH; |
| 2110 | } |
| 2111 | iadc_comp_factor = 100000; |
| 2112 | qpnp_iadc_comp_result(&iadc_comp_factor); |
| 2113 | target_cc_uah = div64_s64(target_cc_uah * 100000, iadc_comp_factor); |
| 2114 | target_cc_uah = cc_reverse_adjust_for_gain(target_cc_uah); |
| 2115 | cc_raw_64 = convert_cc_uah_to_raw(chip, target_cc_uah); |
| 2116 | cc_raw = convert_s64_to_s36(cc_raw_64); |
| 2117 | |
| 2118 | find_ocv_for_soc(chip, params, batt_temp, target_soc, &target_ocv_uv); |
| 2119 | ocv_raw = convert_vbatt_uv_to_raw(chip, target_ocv_uv); |
| 2120 | |
| 2121 | /* |
| 2122 | * If the current_ocv_raw was updated since reaching 100% and is lower |
| 2123 | * than the calculated target ocv threshold, set the new target |
| 2124 | * threshold 1.5mAh lower in order to check if the SoC changed yet. |
| 2125 | */ |
| 2126 | if (current_ocv_raw != chip->ocv_reading_at_100 |
| 2127 | && current_ocv_raw < ocv_raw) |
| 2128 | ocv_raw = current_ocv_raw - OCV_STEP_INCREMENT; |
| 2129 | |
| 2130 | qpnp_write_wrapper(chip, (u8 *)&cc_raw, |
| 2131 | chip->base + BMS1_SW_CC_THR0, 5); |
| 2132 | qpnp_write_wrapper(chip, (u8 *)&ocv_raw, |
| 2133 | chip->base + BMS1_OCV_THR0, 2); |
| 2134 | |
| 2135 | pr_debug("current sw_cc_raw = 0x%llx, current ocv = 0x%hx\n", |
| 2136 | current_shdw_cc_raw, (uint16_t)current_ocv_raw); |
| 2137 | pr_debug("target_cc_uah = %lld, raw64 = 0x%llx, raw 36 = 0x%llx, ocv_raw = 0x%hx\n", |
| 2138 | target_cc_uah, |
| 2139 | (uint64_t)cc_raw_64, cc_raw, |
| 2140 | (uint16_t)ocv_raw); |
| 2141 | } |
| 2142 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2143 | #define SLEEP_RECALC_INTERVAL 3 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2144 | static int calculate_state_of_charge(struct qpnp_bms_chip *chip, |
| 2145 | struct raw_soc_params *raw, |
| 2146 | int batt_temp) |
| 2147 | { |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 2148 | int soc, new_ocv_uv, previous_soc; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2149 | int shutdown_soc, new_calculated_soc, remaining_usable_charge_uah; |
| 2150 | struct soc_params params; |
| 2151 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2152 | if (!is_battery_present(chip)) { |
Xiaozhe Shi | 026fa9b | 2013-03-22 17:00:50 -0700 | [diff] [blame] | 2153 | pr_debug("battery gone, reporting 100\n"); |
| 2154 | new_calculated_soc = 100; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 2155 | goto done_calculating; |
| 2156 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2157 | calculate_soc_params(chip, raw, ¶ms, batt_temp); |
| 2158 | /* calculate remaining usable charge */ |
| 2159 | remaining_usable_charge_uah = params.ocv_charge_uah |
| 2160 | - params.cc_uah |
| 2161 | - params.uuc_uah; |
| 2162 | |
| 2163 | pr_debug("RUC = %duAh\n", remaining_usable_charge_uah); |
| 2164 | if (params.fcc_uah - params.uuc_uah <= 0) { |
Xiaozhe Shi | cb386a2 | 2012-11-29 12:11:42 -0800 | [diff] [blame] | 2165 | pr_debug("FCC = %duAh, UUC = %duAh forcing soc = 0\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2166 | params.fcc_uah, |
| 2167 | params.uuc_uah); |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2168 | new_calculated_soc = 0; |
| 2169 | goto done_calculating; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2170 | } |
| 2171 | |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2172 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
| 2173 | (params.fcc_uah - params.uuc_uah)); |
| 2174 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2175 | if (chip->first_time_calc_soc && soc < 0) { |
| 2176 | /* |
| 2177 | * first time calcualtion and the pon ocv is too low resulting |
| 2178 | * in a bad soc. Adjust ocv to get 0 soc |
| 2179 | */ |
| 2180 | pr_debug("soc is %d, adjusting pon ocv to make it 0\n", soc); |
| 2181 | find_ocv_for_soc(chip, ¶ms, batt_temp, 0, &new_ocv_uv); |
| 2182 | chip->last_ocv_uv = new_ocv_uv; |
| 2183 | |
| 2184 | remaining_usable_charge_uah = params.ocv_charge_uah |
| 2185 | - params.cc_uah |
| 2186 | - params.uuc_uah; |
| 2187 | |
| 2188 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
| 2189 | (params.fcc_uah |
| 2190 | - params.uuc_uah)); |
| 2191 | pr_debug("DONE for O soc is %d, pon ocv adjusted to %duV\n", |
| 2192 | soc, chip->last_ocv_uv); |
| 2193 | } |
| 2194 | |
| 2195 | if (soc > 100) |
| 2196 | soc = 100; |
| 2197 | |
| 2198 | if (soc < 0) { |
Xiaozhe Shi | cb386a2 | 2012-11-29 12:11:42 -0800 | [diff] [blame] | 2199 | pr_debug("bad rem_usb_chg = %d rem_chg %d, cc_uah %d, unusb_chg %d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2200 | remaining_usable_charge_uah, |
| 2201 | params.ocv_charge_uah, |
| 2202 | params.cc_uah, params.uuc_uah); |
| 2203 | |
Xiaozhe Shi | cb386a2 | 2012-11-29 12:11:42 -0800 | [diff] [blame] | 2204 | pr_debug("for bad rem_usb_chg last_ocv_uv = %d batt_temp = %d fcc = %d soc =%d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2205 | chip->last_ocv_uv, batt_temp, |
| 2206 | params.fcc_uah, soc); |
| 2207 | soc = 0; |
| 2208 | } |
| 2209 | |
| 2210 | mutex_lock(&chip->soc_invalidation_mutex); |
| 2211 | shutdown_soc = chip->shutdown_soc; |
| 2212 | |
| 2213 | if (chip->first_time_calc_soc && soc != shutdown_soc |
| 2214 | && is_shutdown_soc_within_limits(chip, soc)) { |
| 2215 | /* |
| 2216 | * soc for the first time - use shutdown soc |
| 2217 | * to adjust pon ocv since it is a small percent away from |
| 2218 | * the real soc |
| 2219 | */ |
| 2220 | pr_debug("soc = %d before forcing shutdown_soc = %d\n", |
| 2221 | soc, shutdown_soc); |
| 2222 | find_ocv_for_soc(chip, ¶ms, batt_temp, |
| 2223 | shutdown_soc, &new_ocv_uv); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2224 | chip->last_ocv_uv = new_ocv_uv; |
| 2225 | |
| 2226 | remaining_usable_charge_uah = params.ocv_charge_uah |
| 2227 | - params.cc_uah |
| 2228 | - params.uuc_uah; |
| 2229 | |
| 2230 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
| 2231 | (params.fcc_uah |
| 2232 | - params.uuc_uah)); |
| 2233 | |
| 2234 | pr_debug("DONE for shutdown_soc = %d soc is %d, adjusted ocv to %duV\n", |
| 2235 | shutdown_soc, soc, chip->last_ocv_uv); |
| 2236 | } |
| 2237 | mutex_unlock(&chip->soc_invalidation_mutex); |
| 2238 | |
| 2239 | pr_debug("SOC before adjustment = %d\n", soc); |
| 2240 | new_calculated_soc = adjust_soc(chip, ¶ms, soc, batt_temp); |
| 2241 | |
Xiaozhe Shi | 445d249 | 2013-03-27 18:10:18 -0700 | [diff] [blame] | 2242 | /* always clamp soc due to BMS hw/sw immaturities */ |
| 2243 | new_calculated_soc = clamp_soc_based_on_voltage(chip, |
| 2244 | new_calculated_soc); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2245 | /* |
| 2246 | * If the battery is full, configure the cc threshold so the system |
| 2247 | * wakes up after SoC changes |
| 2248 | */ |
| 2249 | if (is_battery_full(chip)) |
| 2250 | configure_soc_wakeup(chip, ¶ms, |
| 2251 | batt_temp, bound_soc(new_calculated_soc - 1)); |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2252 | done_calculating: |
Xiaozhe Shi | fa6ea69 | 2013-05-31 11:15:13 -0700 | [diff] [blame] | 2253 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 2254 | previous_soc = chip->calculated_soc; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2255 | chip->calculated_soc = new_calculated_soc; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2256 | pr_debug("CC based calculated SOC = %d\n", chip->calculated_soc); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 2257 | if (chip->last_soc_invalid) { |
| 2258 | chip->last_soc_invalid = false; |
| 2259 | chip->last_soc = -EINVAL; |
| 2260 | } |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2261 | /* |
| 2262 | * Check if more than a long time has passed since the last |
| 2263 | * calculation (more than n times compared to the soc recalculation |
| 2264 | * rate, where n is defined by SLEEP_RECALC_INTERVAL). If this is true, |
| 2265 | * then the system must have gone through a long sleep, and SoC can be |
| 2266 | * allowed to become unbounded by the last reported SoC |
| 2267 | */ |
| 2268 | if (params.delta_time_s * 1000 > |
| 2269 | chip->calculate_soc_ms * SLEEP_RECALC_INTERVAL |
| 2270 | && !chip->first_time_calc_soc) { |
| 2271 | chip->last_soc_unbound = true; |
| 2272 | chip->last_soc_change_sec = chip->last_recalc_time; |
| 2273 | pr_debug("last_soc unbound because elapsed time = %d\n", |
| 2274 | params.delta_time_s); |
| 2275 | } |
| 2276 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2277 | |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2278 | if (new_calculated_soc != previous_soc && chip->bms_psy_registered) { |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2279 | power_supply_changed(&chip->bms_psy); |
| 2280 | pr_debug("power supply changed\n"); |
| 2281 | } else { |
| 2282 | /* |
| 2283 | * Call report state of charge anyways to periodically update |
| 2284 | * reported SoC. This prevents reported SoC from being stuck |
| 2285 | * when calculated soc doesn't change. |
| 2286 | */ |
| 2287 | report_state_of_charge(chip); |
| 2288 | } |
| 2289 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2290 | get_current_time(&chip->last_recalc_time); |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2291 | chip->first_time_calc_soc = 0; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2292 | return chip->calculated_soc; |
| 2293 | } |
| 2294 | |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2295 | static int calculate_soc_from_voltage(struct qpnp_bms_chip *chip) |
| 2296 | { |
| 2297 | int voltage_range_uv, voltage_remaining_uv, voltage_based_soc; |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2298 | int rc, vbat_uv; |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2299 | |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2300 | rc = get_battery_voltage(&vbat_uv); |
| 2301 | if (rc < 0) { |
| 2302 | pr_err("adc vbat failed err = %d\n", rc); |
| 2303 | return rc; |
| 2304 | } |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2305 | voltage_range_uv = chip->max_voltage_uv - chip->v_cutoff_uv; |
| 2306 | voltage_remaining_uv = vbat_uv - chip->v_cutoff_uv; |
| 2307 | voltage_based_soc = voltage_remaining_uv * 100 / voltage_range_uv; |
| 2308 | |
| 2309 | voltage_based_soc = clamp(voltage_based_soc, 0, 100); |
| 2310 | |
| 2311 | if (chip->prev_voltage_based_soc != voltage_based_soc |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2312 | && chip->bms_psy_registered) { |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2313 | power_supply_changed(&chip->bms_psy); |
| 2314 | pr_debug("power supply changed\n"); |
| 2315 | } |
| 2316 | chip->prev_voltage_based_soc = voltage_based_soc; |
| 2317 | |
| 2318 | pr_debug("vbat used = %duv\n", vbat_uv); |
| 2319 | pr_debug("Calculated voltage based soc = %d\n", voltage_based_soc); |
| 2320 | return voltage_based_soc; |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 2321 | } |
| 2322 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2323 | static int recalculate_soc(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2324 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2325 | int batt_temp, rc, soc; |
| 2326 | struct qpnp_vadc_result result; |
| 2327 | struct raw_soc_params raw; |
| 2328 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2329 | bms_stay_awake(&chip->soc_wake_source); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2330 | mutex_lock(&chip->vbat_monitor_mutex); |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2331 | if (chip->vbat_monitor_params.state_request != |
| 2332 | ADC_TM_HIGH_LOW_THR_DISABLE) |
| 2333 | qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2334 | mutex_unlock(&chip->vbat_monitor_mutex); |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2335 | if (chip->use_voltage_soc) { |
| 2336 | soc = calculate_soc_from_voltage(chip); |
| 2337 | } else { |
Abhijeet Dharmapurikar | 0ef9b5c | 2013-07-15 18:24:38 -0700 | [diff] [blame] | 2338 | qpnp_iadc_calibrate_for_trim(true); |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2339 | rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result); |
| 2340 | if (rc) { |
| 2341 | pr_err("error reading vadc LR_MUX1_BATT_THERM = %d, rc = %d\n", |
| 2342 | LR_MUX1_BATT_THERM, rc); |
Abhijeet Dharmapurikar | 713b60a | 2012-12-26 21:30:05 -0800 | [diff] [blame] | 2343 | soc = chip->calculated_soc; |
| 2344 | } else { |
| 2345 | pr_debug("batt_temp phy = %lld meas = 0x%llx\n", |
| 2346 | result.physical, |
| 2347 | result.measurement); |
| 2348 | batt_temp = (int)result.physical; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2349 | |
Abhijeet Dharmapurikar | 713b60a | 2012-12-26 21:30:05 -0800 | [diff] [blame] | 2350 | mutex_lock(&chip->last_ocv_uv_mutex); |
| 2351 | read_soc_params_raw(chip, &raw, batt_temp); |
| 2352 | soc = calculate_state_of_charge(chip, &raw, batt_temp); |
| 2353 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 2354 | } |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2355 | } |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2356 | bms_relax(&chip->soc_wake_source); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2357 | return soc; |
| 2358 | } |
| 2359 | |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 2360 | static void recalculate_work(struct work_struct *work) |
| 2361 | { |
| 2362 | struct qpnp_bms_chip *chip = container_of(work, |
| 2363 | struct qpnp_bms_chip, |
| 2364 | recalc_work); |
| 2365 | |
| 2366 | recalculate_soc(chip); |
| 2367 | } |
| 2368 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2369 | static void calculate_soc_work(struct work_struct *work) |
| 2370 | { |
| 2371 | struct qpnp_bms_chip *chip = container_of(work, |
| 2372 | struct qpnp_bms_chip, |
| 2373 | calculate_soc_delayed_work.work); |
| 2374 | int soc = recalculate_soc(chip); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2375 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2376 | if (soc < chip->low_soc_calc_threshold |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2377 | || wake_lock_active(&chip->low_voltage_wake_lock)) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2378 | schedule_delayed_work(&chip->calculate_soc_delayed_work, |
| 2379 | round_jiffies_relative(msecs_to_jiffies |
| 2380 | (chip->low_soc_calculate_soc_ms))); |
| 2381 | else |
| 2382 | schedule_delayed_work(&chip->calculate_soc_delayed_work, |
| 2383 | round_jiffies_relative(msecs_to_jiffies |
| 2384 | (chip->calculate_soc_ms))); |
| 2385 | } |
| 2386 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2387 | static void configure_vbat_monitor_low(struct qpnp_bms_chip *chip) |
| 2388 | { |
| 2389 | mutex_lock(&chip->vbat_monitor_mutex); |
| 2390 | if (chip->vbat_monitor_params.state_request |
| 2391 | == ADC_TM_HIGH_LOW_THR_ENABLE) { |
| 2392 | /* |
| 2393 | * Battery is now around or below v_cutoff |
| 2394 | */ |
| 2395 | pr_debug("battery entered cutoff range\n"); |
| 2396 | if (!wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2397 | pr_debug("voltage low, holding wakelock\n"); |
| 2398 | wake_lock(&chip->low_voltage_wake_lock); |
| 2399 | cancel_delayed_work_sync( |
| 2400 | &chip->calculate_soc_delayed_work); |
| 2401 | schedule_delayed_work( |
| 2402 | &chip->calculate_soc_delayed_work, 0); |
| 2403 | } |
| 2404 | chip->vbat_monitor_params.state_request = |
| 2405 | ADC_TM_HIGH_THR_ENABLE; |
| 2406 | chip->vbat_monitor_params.high_thr = |
| 2407 | (chip->low_voltage_threshold + VBATT_ERROR_MARGIN); |
| 2408 | pr_debug("set low thr to %d and high to %d\n", |
| 2409 | chip->vbat_monitor_params.low_thr, |
| 2410 | chip->vbat_monitor_params.high_thr); |
| 2411 | chip->vbat_monitor_params.low_thr = 0; |
| 2412 | } else if (chip->vbat_monitor_params.state_request |
| 2413 | == ADC_TM_LOW_THR_ENABLE) { |
| 2414 | /* |
| 2415 | * Battery is in normal operation range. |
| 2416 | */ |
| 2417 | pr_debug("battery entered normal range\n"); |
| 2418 | if (wake_lock_active(&chip->cv_wake_lock)) { |
| 2419 | wake_unlock(&chip->cv_wake_lock); |
| 2420 | pr_debug("releasing cv wake lock\n"); |
| 2421 | } |
| 2422 | chip->in_cv_range = false; |
| 2423 | chip->vbat_monitor_params.state_request = |
| 2424 | ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2425 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv |
| 2426 | - VBATT_ERROR_MARGIN; |
| 2427 | chip->vbat_monitor_params.low_thr = |
| 2428 | chip->low_voltage_threshold; |
| 2429 | pr_debug("set low thr to %d and high to %d\n", |
| 2430 | chip->vbat_monitor_params.low_thr, |
| 2431 | chip->vbat_monitor_params.high_thr); |
| 2432 | } |
| 2433 | qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params); |
| 2434 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 2435 | } |
| 2436 | |
| 2437 | #define CV_LOW_THRESHOLD_HYST_UV 100000 |
| 2438 | static void configure_vbat_monitor_high(struct qpnp_bms_chip *chip) |
| 2439 | { |
| 2440 | mutex_lock(&chip->vbat_monitor_mutex); |
| 2441 | if (chip->vbat_monitor_params.state_request |
| 2442 | == ADC_TM_HIGH_LOW_THR_ENABLE) { |
| 2443 | /* |
| 2444 | * Battery is around vddmax |
| 2445 | */ |
| 2446 | pr_debug("battery entered vddmax range\n"); |
| 2447 | chip->in_cv_range = true; |
| 2448 | if (!wake_lock_active(&chip->cv_wake_lock)) { |
| 2449 | wake_lock(&chip->cv_wake_lock); |
| 2450 | pr_debug("holding cv wake lock\n"); |
| 2451 | } |
| 2452 | schedule_work(&chip->recalc_work); |
| 2453 | chip->vbat_monitor_params.state_request = |
| 2454 | ADC_TM_LOW_THR_ENABLE; |
| 2455 | chip->vbat_monitor_params.low_thr = |
| 2456 | (chip->max_voltage_uv - CV_LOW_THRESHOLD_HYST_UV); |
| 2457 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv * 2; |
| 2458 | pr_debug("set low thr to %d and high to %d\n", |
| 2459 | chip->vbat_monitor_params.low_thr, |
| 2460 | chip->vbat_monitor_params.high_thr); |
| 2461 | } else if (chip->vbat_monitor_params.state_request |
| 2462 | == ADC_TM_HIGH_THR_ENABLE) { |
| 2463 | /* |
| 2464 | * Battery is in normal operation range. |
| 2465 | */ |
| 2466 | pr_debug("battery entered normal range\n"); |
| 2467 | if (wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2468 | pr_debug("voltage high, releasing wakelock\n"); |
| 2469 | wake_unlock(&chip->low_voltage_wake_lock); |
| 2470 | } |
| 2471 | chip->vbat_monitor_params.state_request = |
| 2472 | ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2473 | chip->vbat_monitor_params.high_thr = |
| 2474 | chip->max_voltage_uv - VBATT_ERROR_MARGIN; |
| 2475 | chip->vbat_monitor_params.low_thr = |
| 2476 | chip->low_voltage_threshold; |
| 2477 | pr_debug("set low thr to %d and high to %d\n", |
| 2478 | chip->vbat_monitor_params.low_thr, |
| 2479 | chip->vbat_monitor_params.high_thr); |
| 2480 | } |
| 2481 | qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params); |
| 2482 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 2483 | } |
| 2484 | |
| 2485 | static void btm_notify_vbat(enum qpnp_tm_state state, void *ctx) |
| 2486 | { |
| 2487 | struct qpnp_bms_chip *chip = ctx; |
| 2488 | int vbat_uv; |
| 2489 | struct qpnp_vadc_result result; |
| 2490 | int rc; |
| 2491 | |
| 2492 | rc = qpnp_vadc_read(VBAT_SNS, &result); |
| 2493 | pr_debug("vbat = %lld, raw = 0x%x\n", result.physical, result.adc_code); |
| 2494 | |
| 2495 | get_battery_voltage(&vbat_uv); |
| 2496 | pr_debug("vbat is at %d, state is at %d\n", vbat_uv, state); |
| 2497 | |
| 2498 | if (state == ADC_TM_LOW_STATE) { |
| 2499 | pr_debug("low voltage btm notification triggered\n"); |
| 2500 | if (vbat_uv - VBATT_ERROR_MARGIN |
| 2501 | < chip->vbat_monitor_params.low_thr) { |
| 2502 | configure_vbat_monitor_low(chip); |
| 2503 | } else { |
| 2504 | pr_debug("faulty btm trigger, discarding\n"); |
| 2505 | qpnp_adc_tm_channel_measure( |
| 2506 | &chip->vbat_monitor_params); |
| 2507 | } |
| 2508 | } else if (state == ADC_TM_HIGH_STATE) { |
| 2509 | pr_debug("high voltage btm notification triggered\n"); |
| 2510 | if (vbat_uv + VBATT_ERROR_MARGIN |
| 2511 | > chip->vbat_monitor_params.high_thr) { |
| 2512 | configure_vbat_monitor_high(chip); |
| 2513 | } else { |
| 2514 | pr_debug("faulty btm trigger, discarding\n"); |
| 2515 | qpnp_adc_tm_channel_measure( |
| 2516 | &chip->vbat_monitor_params); |
| 2517 | } |
| 2518 | } else { |
| 2519 | pr_debug("unknown voltage notification state: %d\n", state); |
| 2520 | } |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2521 | if (chip->bms_psy_registered) |
Xiaozhe Shi | fa120db | 2013-06-06 15:57:19 -0700 | [diff] [blame] | 2522 | power_supply_changed(&chip->bms_psy); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2523 | } |
| 2524 | |
| 2525 | static int reset_vbat_monitoring(struct qpnp_bms_chip *chip) |
| 2526 | { |
| 2527 | int rc; |
| 2528 | |
| 2529 | chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_DISABLE; |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2530 | |
| 2531 | rc = qpnp_adc_tm_disable_chan_meas(&chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2532 | if (rc) { |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2533 | pr_err("tm disable failed: %d\n", rc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2534 | return rc; |
| 2535 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2536 | if (wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2537 | pr_debug("battery removed, releasing wakelock\n"); |
| 2538 | wake_unlock(&chip->low_voltage_wake_lock); |
| 2539 | } |
| 2540 | if (chip->in_cv_range) { |
| 2541 | pr_debug("battery removed, removing in_cv_range state\n"); |
| 2542 | chip->in_cv_range = false; |
| 2543 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2544 | return 0; |
| 2545 | } |
| 2546 | |
| 2547 | static int setup_vbat_monitoring(struct qpnp_bms_chip *chip) |
| 2548 | { |
| 2549 | int rc; |
| 2550 | |
| 2551 | rc = qpnp_adc_tm_is_ready(); |
| 2552 | if (rc) { |
| 2553 | pr_info("adc tm is not ready yet: %d, defer probe\n", rc); |
| 2554 | return -EPROBE_DEFER; |
| 2555 | } |
| 2556 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2557 | chip->vbat_monitor_params.low_thr = chip->low_voltage_threshold; |
| 2558 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv |
| 2559 | - VBATT_ERROR_MARGIN; |
| 2560 | chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2561 | chip->vbat_monitor_params.channel = VBAT_SNS; |
| 2562 | chip->vbat_monitor_params.btm_ctx = (void *)chip; |
| 2563 | chip->vbat_monitor_params.timer_interval = ADC_MEAS1_INTERVAL_1S; |
| 2564 | chip->vbat_monitor_params.threshold_notification = &btm_notify_vbat; |
| 2565 | pr_debug("set low thr to %d and high to %d\n", |
| 2566 | chip->vbat_monitor_params.low_thr, |
| 2567 | chip->vbat_monitor_params.high_thr); |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2568 | |
| 2569 | if (!is_battery_present(chip)) { |
| 2570 | pr_debug("no battery inserted, do not enable vbat monitoring\n"); |
| 2571 | chip->vbat_monitor_params.state_request = |
| 2572 | ADC_TM_HIGH_LOW_THR_DISABLE; |
| 2573 | } else { |
| 2574 | rc = qpnp_adc_tm_channel_measure(&chip->vbat_monitor_params); |
| 2575 | if (rc) { |
| 2576 | pr_err("tm setup failed: %d\n", rc); |
| 2577 | return rc; |
| 2578 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2579 | } |
| 2580 | pr_debug("setup complete\n"); |
| 2581 | return 0; |
| 2582 | } |
| 2583 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2584 | static void readjust_fcc_table(struct qpnp_bms_chip *chip) |
| 2585 | { |
| 2586 | struct single_row_lut *temp, *old; |
| 2587 | int i, fcc, ratio; |
| 2588 | |
| 2589 | if (!chip->enable_fcc_learning) |
| 2590 | return; |
| 2591 | |
| 2592 | if (!chip->fcc_temp_lut) { |
| 2593 | pr_err("The static fcc lut table is NULL\n"); |
| 2594 | return; |
| 2595 | } |
| 2596 | |
| 2597 | temp = kzalloc(sizeof(struct single_row_lut), GFP_KERNEL); |
| 2598 | if (!temp) { |
| 2599 | pr_err("Cannot allocate memory for adjusted fcc table\n"); |
| 2600 | return; |
| 2601 | } |
| 2602 | |
| 2603 | fcc = interpolate_fcc(chip->fcc_temp_lut, chip->fcc_new_batt_temp); |
| 2604 | |
| 2605 | temp->cols = chip->fcc_temp_lut->cols; |
| 2606 | for (i = 0; i < chip->fcc_temp_lut->cols; i++) { |
| 2607 | temp->x[i] = chip->fcc_temp_lut->x[i]; |
| 2608 | ratio = div_u64(chip->fcc_temp_lut->y[i] * 1000, fcc); |
| 2609 | temp->y[i] = (ratio * chip->fcc_new_mah); |
| 2610 | temp->y[i] /= 1000; |
| 2611 | } |
| 2612 | |
| 2613 | old = chip->adjusted_fcc_temp_lut; |
| 2614 | chip->adjusted_fcc_temp_lut = temp; |
| 2615 | kfree(old); |
| 2616 | } |
| 2617 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2618 | static int read_fcc_data_from_backup(struct qpnp_bms_chip *chip) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2619 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2620 | int rc, i; |
| 2621 | u8 fcc = 0, chgcyl = 0; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2622 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2623 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2624 | rc = qpnp_read_wrapper(chip, &fcc, |
| 2625 | chip->base + BMS_FCC_BASE_REG + i, 1); |
| 2626 | rc |= qpnp_read_wrapper(chip, &chgcyl, |
| 2627 | chip->base + BMS_CHGCYL_BASE_REG + i, 1); |
| 2628 | if (rc) { |
| 2629 | pr_err("Unable to read FCC data\n"); |
| 2630 | return rc; |
| 2631 | } |
| 2632 | if (fcc == 0 || (fcc == 0xFF && chgcyl == 0xFF)) { |
| 2633 | /* FCC invalid/not present */ |
| 2634 | chip->fcc_learning_samples[i].fcc_new = 0; |
| 2635 | chip->fcc_learning_samples[i].chargecycles = 0; |
| 2636 | } else { |
| 2637 | /* valid FCC data */ |
| 2638 | chip->fcc_sample_count++; |
| 2639 | chip->fcc_learning_samples[i].fcc_new = |
| 2640 | fcc * chip->fcc_resolution; |
| 2641 | chip->fcc_learning_samples[i].chargecycles = |
| 2642 | chgcyl * CHGCYL_RESOLUTION; |
| 2643 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2644 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2645 | |
| 2646 | return 0; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2647 | } |
| 2648 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2649 | static int discard_backup_fcc_data(struct qpnp_bms_chip *chip) |
| 2650 | { |
| 2651 | int rc = 0, i; |
| 2652 | u8 temp_u8 = 0; |
| 2653 | |
| 2654 | chip->fcc_sample_count = 0; |
| 2655 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2656 | rc = qpnp_write_wrapper(chip, &temp_u8, |
| 2657 | chip->base + BMS_FCC_BASE_REG + i, 1); |
| 2658 | rc |= qpnp_write_wrapper(chip, &temp_u8, |
| 2659 | chip->base + BMS_CHGCYL_BASE_REG + i, 1); |
| 2660 | if (rc) { |
| 2661 | pr_err("Unable to clear FCC data\n"); |
| 2662 | return rc; |
| 2663 | } |
| 2664 | } |
| 2665 | |
| 2666 | return 0; |
| 2667 | } |
| 2668 | |
| 2669 | static void |
| 2670 | average_fcc_samples_and_readjust_fcc_table(struct qpnp_bms_chip *chip) |
| 2671 | { |
| 2672 | int i, temp_fcc_avg = 0, temp_fcc_delta = 0, new_fcc_avg = 0; |
| 2673 | struct fcc_sample *ft; |
| 2674 | |
| 2675 | for (i = 0; i < chip->min_fcc_learning_samples; i++) |
| 2676 | temp_fcc_avg += chip->fcc_learning_samples[i].fcc_new; |
| 2677 | |
| 2678 | temp_fcc_avg /= chip->min_fcc_learning_samples; |
| 2679 | temp_fcc_delta = div_u64(temp_fcc_avg * DELTA_FCC_PERCENT, 100); |
| 2680 | |
| 2681 | /* fix the fcc if its an outlier i.e. > 5% of the average */ |
| 2682 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2683 | ft = &chip->fcc_learning_samples[i]; |
| 2684 | if (abs(ft->fcc_new - temp_fcc_avg) > temp_fcc_delta) |
| 2685 | new_fcc_avg += temp_fcc_avg; |
| 2686 | else |
| 2687 | new_fcc_avg += ft->fcc_new; |
| 2688 | } |
| 2689 | new_fcc_avg /= chip->min_fcc_learning_samples; |
| 2690 | |
| 2691 | chip->fcc_new_mah = new_fcc_avg; |
| 2692 | chip->fcc_new_batt_temp = FCC_DEFAULT_TEMP; |
| 2693 | pr_info("FCC update: New fcc_mah=%d, fcc_batt_temp=%d\n", |
| 2694 | new_fcc_avg, FCC_DEFAULT_TEMP); |
| 2695 | readjust_fcc_table(chip); |
| 2696 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2697 | |
| 2698 | static void backup_charge_cycle(struct qpnp_bms_chip *chip) |
| 2699 | { |
| 2700 | int rc = 0; |
| 2701 | |
| 2702 | if (chip->charge_increase >= 0) { |
| 2703 | rc = qpnp_write_wrapper(chip, &chip->charge_increase, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2704 | chip->base + CHARGE_INCREASE_STORAGE, 1); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2705 | if (rc) |
| 2706 | pr_err("Unable to backup charge_increase\n"); |
| 2707 | } |
| 2708 | |
| 2709 | if (chip->charge_cycles >= 0) { |
| 2710 | rc = qpnp_write_wrapper(chip, (u8 *)&chip->charge_cycles, |
| 2711 | chip->base + CHARGE_CYCLE_STORAGE_LSB, 2); |
| 2712 | if (rc) |
| 2713 | pr_err("Unable to backup charge_cycles\n"); |
| 2714 | } |
| 2715 | } |
| 2716 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2717 | static bool chargecycles_in_range(struct qpnp_bms_chip *chip) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2718 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2719 | int i, min_cycle, max_cycle, valid_range; |
| 2720 | |
| 2721 | /* find the smallest and largest charge cycle */ |
| 2722 | max_cycle = min_cycle = chip->fcc_learning_samples[0].chargecycles; |
| 2723 | for (i = 1; i < chip->min_fcc_learning_samples; i++) { |
| 2724 | if (min_cycle > chip->fcc_learning_samples[i].chargecycles) |
| 2725 | min_cycle = chip->fcc_learning_samples[i].chargecycles; |
| 2726 | if (max_cycle < chip->fcc_learning_samples[i].chargecycles) |
| 2727 | max_cycle = chip->fcc_learning_samples[i].chargecycles; |
| 2728 | } |
| 2729 | |
| 2730 | /* check if chargecyles are in range to continue with FCC update */ |
| 2731 | valid_range = DIV_ROUND_UP(VALID_FCC_CHGCYL_RANGE, |
| 2732 | CHGCYL_RESOLUTION) * CHGCYL_RESOLUTION; |
| 2733 | if (abs(max_cycle - min_cycle) > valid_range) |
| 2734 | return false; |
| 2735 | |
| 2736 | return true; |
| 2737 | } |
| 2738 | |
| 2739 | static int read_chgcycle_data_from_backup(struct qpnp_bms_chip *chip) |
| 2740 | { |
| 2741 | int rc; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2742 | uint16_t temp_u16 = 0; |
| 2743 | u8 temp_u8 = 0; |
| 2744 | |
| 2745 | rc = qpnp_read_wrapper(chip, &temp_u8, |
| 2746 | chip->base + CHARGE_INCREASE_STORAGE, 1); |
| 2747 | if (!rc && temp_u8 != 0xFF) |
| 2748 | chip->charge_increase = temp_u8; |
| 2749 | |
| 2750 | rc = qpnp_read_wrapper(chip, (u8 *)&temp_u16, |
| 2751 | chip->base + CHARGE_CYCLE_STORAGE_LSB, 2); |
| 2752 | if (!rc && temp_u16 != 0xFFFF) |
| 2753 | chip->charge_cycles = temp_u16; |
| 2754 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2755 | return rc; |
| 2756 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2757 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2758 | static void |
| 2759 | attempt_learning_new_fcc(struct qpnp_bms_chip *chip) |
| 2760 | { |
| 2761 | pr_debug("Total FCC sample count=%d\n", chip->fcc_sample_count); |
| 2762 | |
| 2763 | /* update FCC if we have the required samples */ |
| 2764 | if ((chip->fcc_sample_count == chip->min_fcc_learning_samples) && |
| 2765 | chargecycles_in_range(chip)) |
| 2766 | average_fcc_samples_and_readjust_fcc_table(chip); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2767 | } |
| 2768 | |
| 2769 | static int calculate_real_soc(struct qpnp_bms_chip *chip, |
| 2770 | int batt_temp, struct raw_soc_params *raw, int cc_uah) |
| 2771 | { |
| 2772 | int fcc_uah, rc_uah; |
| 2773 | |
| 2774 | fcc_uah = calculate_fcc(chip, batt_temp); |
| 2775 | rc_uah = calculate_ocv_charge(chip, raw, fcc_uah); |
| 2776 | |
| 2777 | return ((rc_uah - cc_uah) * 100) / fcc_uah; |
| 2778 | } |
| 2779 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2780 | #define MAX_U8_VALUE ((u8)(~0U)) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2781 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2782 | static int backup_new_fcc(struct qpnp_bms_chip *chip, int fcc_mah, |
| 2783 | int chargecycles) |
| 2784 | { |
| 2785 | int rc, min_cycle, i; |
| 2786 | u8 fcc_new, chgcyl, pos = 0; |
| 2787 | struct fcc_sample *ft; |
| 2788 | |
| 2789 | if ((fcc_mah > (chip->fcc_resolution * MAX_U8_VALUE)) || |
| 2790 | (chargecycles > (CHGCYL_RESOLUTION * MAX_U8_VALUE))) { |
| 2791 | pr_warn("FCC/Chgcyl beyond storage limit. FCC=%d, chgcyl=%d\n", |
| 2792 | fcc_mah, chargecycles); |
| 2793 | return -EINVAL; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2794 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2795 | |
| 2796 | if (chip->fcc_sample_count == chip->min_fcc_learning_samples) { |
| 2797 | /* search best location - oldest entry */ |
| 2798 | min_cycle = chip->fcc_learning_samples[0].chargecycles; |
| 2799 | for (i = 1; i < chip->min_fcc_learning_samples; i++) { |
| 2800 | if (min_cycle > |
| 2801 | chip->fcc_learning_samples[i].chargecycles) |
| 2802 | pos = i; |
| 2803 | } |
| 2804 | } else { |
| 2805 | /* find an empty location */ |
| 2806 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2807 | ft = &chip->fcc_learning_samples[i]; |
| 2808 | if (ft->fcc_new == 0 || (ft->fcc_new == 0xFF && |
| 2809 | ft->chargecycles == 0xFF)) { |
| 2810 | pos = i; |
| 2811 | break; |
| 2812 | } |
| 2813 | } |
| 2814 | chip->fcc_sample_count++; |
| 2815 | } |
| 2816 | chip->fcc_learning_samples[pos].fcc_new = fcc_mah; |
| 2817 | chip->fcc_learning_samples[pos].chargecycles = chargecycles; |
| 2818 | |
| 2819 | fcc_new = DIV_ROUND_UP(fcc_mah, chip->fcc_resolution); |
| 2820 | rc = qpnp_write_wrapper(chip, (u8 *)&fcc_new, |
| 2821 | chip->base + BMS_FCC_BASE_REG + pos, 1); |
| 2822 | if (rc) |
| 2823 | return rc; |
| 2824 | |
| 2825 | chgcyl = DIV_ROUND_UP(chargecycles, CHGCYL_RESOLUTION); |
| 2826 | rc = qpnp_write_wrapper(chip, (u8 *)&chgcyl, |
| 2827 | chip->base + BMS_CHGCYL_BASE_REG + pos, 1); |
| 2828 | if (rc) |
| 2829 | return rc; |
| 2830 | |
| 2831 | pr_debug("Backup new FCC: fcc_new=%d, chargecycle=%d, pos=%d\n", |
| 2832 | fcc_new, chgcyl, pos); |
| 2833 | |
| 2834 | return rc; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2835 | } |
| 2836 | |
| 2837 | static void update_fcc_learning_table(struct qpnp_bms_chip *chip, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2838 | int new_fcc_uah, int chargecycles, int batt_temp) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2839 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2840 | int rc, fcc_default, fcc_temp; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2841 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2842 | /* convert the fcc at batt_temp to new fcc at FCC_DEFAULT_TEMP */ |
| 2843 | fcc_default = calculate_fcc(chip, FCC_DEFAULT_TEMP) / 1000; |
| 2844 | fcc_temp = calculate_fcc(chip, batt_temp) / 1000; |
| 2845 | new_fcc_uah = (new_fcc_uah / fcc_temp) * fcc_default; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2846 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2847 | rc = backup_new_fcc(chip, new_fcc_uah / 1000, chargecycles); |
| 2848 | if (rc) { |
| 2849 | pr_err("Unable to backup new FCC\n"); |
| 2850 | return; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2851 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2852 | /* check if FCC can be updated */ |
| 2853 | attempt_learning_new_fcc(chip); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2854 | } |
| 2855 | |
| 2856 | static bool is_new_fcc_valid(int new_fcc_uah, int fcc_uah) |
| 2857 | { |
| 2858 | if ((new_fcc_uah >= (fcc_uah / 2)) && |
| 2859 | ((new_fcc_uah * 100) <= (fcc_uah * 105))) |
| 2860 | return true; |
| 2861 | |
| 2862 | pr_debug("FCC rejected - not within valid limit\n"); |
| 2863 | return false; |
| 2864 | } |
| 2865 | |
| 2866 | static void fcc_learning_config(struct qpnp_bms_chip *chip, bool start) |
| 2867 | { |
| 2868 | int rc, batt_temp; |
| 2869 | struct raw_soc_params raw; |
| 2870 | struct qpnp_vadc_result result; |
| 2871 | int fcc_uah, new_fcc_uah, delta_cc_uah, delta_soc; |
| 2872 | |
| 2873 | rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result); |
| 2874 | if (rc) { |
| 2875 | pr_err("Unable to read batt_temp\n"); |
| 2876 | return; |
| 2877 | } else { |
| 2878 | batt_temp = (int)result.physical; |
| 2879 | } |
| 2880 | |
| 2881 | rc = read_soc_params_raw(chip, &raw, batt_temp); |
| 2882 | if (rc) { |
| 2883 | pr_err("Unable to read CC, cannot update FCC\n"); |
| 2884 | return; |
| 2885 | } |
| 2886 | |
| 2887 | if (start) { |
| 2888 | chip->start_pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 2889 | batt_temp / 10, raw.last_good_ocv_uv / 1000); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 2890 | chip->start_cc_uah = calculate_cc(chip, raw.cc, CC, NORESET); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2891 | chip->start_real_soc = calculate_real_soc(chip, |
| 2892 | batt_temp, &raw, chip->start_cc_uah); |
| 2893 | pr_debug("start_pc=%d, start_cc=%d, start_soc=%d real_soc=%d\n", |
| 2894 | chip->start_pc, chip->start_cc_uah, |
| 2895 | chip->start_soc, chip->start_real_soc); |
| 2896 | } else { |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 2897 | chip->end_cc_uah = calculate_cc(chip, raw.cc, CC, NORESET); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2898 | delta_soc = 100 - chip->start_real_soc; |
| 2899 | delta_cc_uah = abs(chip->end_cc_uah - chip->start_cc_uah); |
| 2900 | new_fcc_uah = div_u64(delta_cc_uah * 100, delta_soc); |
| 2901 | fcc_uah = calculate_fcc(chip, batt_temp); |
| 2902 | pr_debug("start_soc=%d, start_pc=%d, start_real_soc=%d, start_cc=%d, end_cc=%d, new_fcc=%d\n", |
| 2903 | chip->start_soc, chip->start_pc, chip->start_real_soc, |
| 2904 | chip->start_cc_uah, chip->end_cc_uah, new_fcc_uah); |
| 2905 | |
| 2906 | if (is_new_fcc_valid(new_fcc_uah, fcc_uah)) |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2907 | update_fcc_learning_table(chip, new_fcc_uah, |
| 2908 | chip->charge_cycles, batt_temp); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2909 | } |
| 2910 | } |
| 2911 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2912 | static void charging_began(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2913 | { |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2914 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2915 | mutex_lock(&chip->last_soc_mutex); |
| 2916 | chip->charge_start_tm_sec = 0; |
| 2917 | chip->catch_up_time_sec = 0; |
| 2918 | mutex_unlock(&chip->last_soc_mutex); |
| 2919 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2920 | chip->start_soc = report_state_of_charge(chip); |
| 2921 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2922 | mutex_lock(&chip->last_ocv_uv_mutex); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2923 | if (chip->enable_fcc_learning) |
| 2924 | fcc_learning_config(chip, true); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2925 | chip->soc_at_cv = -EINVAL; |
| 2926 | chip->prev_chg_soc = -EINVAL; |
| 2927 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 2928 | } |
| 2929 | |
| 2930 | static void charging_ended(struct qpnp_bms_chip *chip) |
| 2931 | { |
| 2932 | mutex_lock(&chip->last_soc_mutex); |
| 2933 | chip->charge_start_tm_sec = 0; |
| 2934 | chip->catch_up_time_sec = 0; |
| 2935 | mutex_unlock(&chip->last_soc_mutex); |
| 2936 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2937 | chip->end_soc = report_state_of_charge(chip); |
| 2938 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2939 | mutex_lock(&chip->last_ocv_uv_mutex); |
| 2940 | chip->soc_at_cv = -EINVAL; |
| 2941 | chip->prev_chg_soc = -EINVAL; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2942 | |
| 2943 | /* update the chargecycles */ |
| 2944 | if (chip->end_soc > chip->start_soc) { |
| 2945 | chip->charge_increase += (chip->end_soc - chip->start_soc); |
| 2946 | if (chip->charge_increase > 100) { |
| 2947 | chip->charge_cycles++; |
| 2948 | chip->charge_increase = chip->charge_increase % 100; |
| 2949 | } |
| 2950 | if (chip->enable_fcc_learning) |
| 2951 | backup_charge_cycle(chip); |
| 2952 | } |
| 2953 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2954 | if (get_battery_status(chip) == POWER_SUPPLY_STATUS_FULL) { |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2955 | if (chip->enable_fcc_learning && |
| 2956 | (chip->start_soc <= chip->min_fcc_learning_soc) && |
| 2957 | (chip->start_pc <= chip->min_fcc_ocv_pc)) |
| 2958 | fcc_learning_config(chip, false); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2959 | chip->done_charging = true; |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2960 | chip->last_soc_invalid = true; |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 2961 | } else if (chip->charging_adjusted_ocv > 0) { |
| 2962 | pr_debug("Charging stopped before full, adjusted OCV = %d\n", |
| 2963 | chip->charging_adjusted_ocv); |
| 2964 | chip->last_ocv_uv = chip->charging_adjusted_ocv; |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2965 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2966 | |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 2967 | chip->charging_adjusted_ocv = -EINVAL; |
| 2968 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2969 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 2970 | } |
| 2971 | |
| 2972 | static void battery_status_check(struct qpnp_bms_chip *chip) |
| 2973 | { |
| 2974 | int status = get_battery_status(chip); |
| 2975 | |
| 2976 | if (chip->battery_status != status) { |
| 2977 | if (status == POWER_SUPPLY_STATUS_CHARGING) { |
| 2978 | pr_debug("charging started\n"); |
| 2979 | charging_began(chip); |
| 2980 | } else if (chip->battery_status |
| 2981 | == POWER_SUPPLY_STATUS_CHARGING) { |
| 2982 | pr_debug("charging ended\n"); |
| 2983 | charging_ended(chip); |
| 2984 | } |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2985 | |
| 2986 | if (status == POWER_SUPPLY_STATUS_FULL) { |
| 2987 | pr_debug("battery full\n"); |
| 2988 | enable_bms_irq(&chip->ocv_thr_irq); |
| 2989 | enable_bms_irq(&chip->sw_cc_thr_irq); |
| 2990 | } else if (chip->battery_status |
| 2991 | == POWER_SUPPLY_STATUS_FULL) { |
| 2992 | pr_debug("battery not full any more\n"); |
| 2993 | disable_bms_irq(&chip->ocv_thr_irq); |
| 2994 | disable_bms_irq(&chip->sw_cc_thr_irq); |
| 2995 | } |
| 2996 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2997 | chip->battery_status = status; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2998 | /* battery charge status has changed, so force a soc |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 2999 | * recalculation to update the SoC */ |
| 3000 | schedule_work(&chip->recalc_work); |
| 3001 | } |
| 3002 | } |
| 3003 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3004 | #define CALIB_WRKARND_DIG_MAJOR_MAX 0x03 |
| 3005 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3006 | static void battery_insertion_check(struct qpnp_bms_chip *chip) |
| 3007 | { |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3008 | bool present = is_battery_present(chip); |
| 3009 | |
| 3010 | mutex_lock(&chip->vbat_monitor_mutex); |
| 3011 | if (chip->battery_present != present) { |
| 3012 | if (chip->battery_present != -EINVAL) { |
| 3013 | if (present) { |
| 3014 | setup_vbat_monitoring(chip); |
| 3015 | chip->new_battery = true; |
| 3016 | } else { |
| 3017 | reset_vbat_monitoring(chip); |
| 3018 | } |
| 3019 | } |
| 3020 | chip->battery_present = present; |
| 3021 | /* a new battery was inserted or removed, so force a soc |
| 3022 | * recalculation to update the SoC */ |
| 3023 | schedule_work(&chip->recalc_work); |
| 3024 | } |
| 3025 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 3026 | } |
| 3027 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3028 | /* Returns capacity as a SoC percentage between 0 and 100 */ |
| 3029 | static int get_prop_bms_capacity(struct qpnp_bms_chip *chip) |
| 3030 | { |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 3031 | return report_state_of_charge(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3032 | } |
| 3033 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3034 | static void qpnp_bms_external_power_changed(struct power_supply *psy) |
| 3035 | { |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3036 | struct qpnp_bms_chip *chip = container_of(psy, struct qpnp_bms_chip, |
| 3037 | bms_psy); |
| 3038 | |
| 3039 | battery_insertion_check(chip); |
| 3040 | battery_status_check(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3041 | } |
| 3042 | |
| 3043 | static int qpnp_bms_power_get_property(struct power_supply *psy, |
| 3044 | enum power_supply_property psp, |
| 3045 | union power_supply_propval *val) |
| 3046 | { |
| 3047 | struct qpnp_bms_chip *chip = container_of(psy, struct qpnp_bms_chip, |
| 3048 | bms_psy); |
| 3049 | |
| 3050 | switch (psp) { |
| 3051 | case POWER_SUPPLY_PROP_CAPACITY: |
| 3052 | val->intval = get_prop_bms_capacity(chip); |
| 3053 | break; |
| 3054 | case POWER_SUPPLY_PROP_CURRENT_NOW: |
| 3055 | val->intval = get_prop_bms_current_now(chip); |
| 3056 | break; |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 3057 | case POWER_SUPPLY_PROP_RESISTANCE: |
| 3058 | val->intval = get_prop_bms_batt_resistance(chip); |
| 3059 | break; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 3060 | case POWER_SUPPLY_PROP_CHARGE_COUNTER: |
| 3061 | val->intval = get_prop_bms_charge_counter(chip); |
| 3062 | break; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3063 | case POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW: |
| 3064 | val->intval = get_prop_bms_charge_counter_shadow(chip); |
| 3065 | break; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3066 | case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: |
| 3067 | val->intval = get_prop_bms_charge_full_design(chip); |
| 3068 | break; |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 3069 | case POWER_SUPPLY_PROP_CHARGE_FULL: |
| 3070 | val->intval = get_prop_bms_charge_full(chip); |
| 3071 | break; |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 3072 | case POWER_SUPPLY_PROP_CYCLE_COUNT: |
| 3073 | val->intval = chip->charge_cycles; |
| 3074 | break; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3075 | default: |
| 3076 | return -EINVAL; |
| 3077 | } |
| 3078 | return 0; |
| 3079 | } |
| 3080 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3081 | #define OCV_USE_LIMIT_EN BIT(7) |
| 3082 | static int set_ocv_voltage_thresholds(struct qpnp_bms_chip *chip, |
| 3083 | int low_voltage_threshold, |
| 3084 | int high_voltage_threshold) |
| 3085 | { |
| 3086 | uint16_t low_voltage_raw, high_voltage_raw; |
| 3087 | int rc; |
| 3088 | |
| 3089 | low_voltage_raw = convert_vbatt_uv_to_raw(chip, |
| 3090 | low_voltage_threshold); |
| 3091 | high_voltage_raw = convert_vbatt_uv_to_raw(chip, |
| 3092 | high_voltage_threshold); |
| 3093 | rc = qpnp_write_wrapper(chip, (u8 *)&low_voltage_raw, |
| 3094 | chip->base + BMS1_OCV_USE_LOW_LIMIT_THR0, 2); |
| 3095 | if (rc) { |
| 3096 | pr_err("Failed to set ocv low voltage threshold: %d\n", rc); |
| 3097 | return rc; |
| 3098 | } |
| 3099 | rc = qpnp_write_wrapper(chip, (u8 *)&high_voltage_raw, |
| 3100 | chip->base + BMS1_OCV_USE_HIGH_LIMIT_THR0, 2); |
| 3101 | if (rc) { |
| 3102 | pr_err("Failed to set ocv high voltage threshold: %d\n", rc); |
| 3103 | return rc; |
| 3104 | } |
| 3105 | rc = qpnp_masked_write(chip, BMS1_OCV_USE_LIMIT_CTL, |
| 3106 | OCV_USE_LIMIT_EN, OCV_USE_LIMIT_EN); |
| 3107 | if (rc) { |
| 3108 | pr_err("Failed to enabled ocv voltage thresholds: %d\n", rc); |
| 3109 | return rc; |
| 3110 | } |
| 3111 | pr_debug("ocv low threshold set to %d uv or 0x%x raw\n", |
| 3112 | low_voltage_threshold, low_voltage_raw); |
| 3113 | pr_debug("ocv high threshold set to %d uv or 0x%x raw\n", |
| 3114 | high_voltage_threshold, high_voltage_raw); |
| 3115 | return 0; |
| 3116 | } |
| 3117 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3118 | static void read_shutdown_soc_and_iavg(struct qpnp_bms_chip *chip) |
| 3119 | { |
| 3120 | int rc; |
| 3121 | u8 temp; |
| 3122 | |
| 3123 | if (chip->ignore_shutdown_soc) { |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 3124 | chip->shutdown_soc_invalid = true; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3125 | chip->shutdown_soc = 0; |
| 3126 | chip->shutdown_iavg_ma = 0; |
| 3127 | } else { |
| 3128 | rc = qpnp_read_wrapper(chip, &temp, |
| 3129 | chip->base + IAVG_STORAGE_REG, 1); |
| 3130 | if (rc) { |
| 3131 | pr_err("failed to read addr = %d %d assuming %d\n", |
| 3132 | chip->base + IAVG_STORAGE_REG, rc, |
| 3133 | IAVG_START); |
| 3134 | chip->shutdown_iavg_ma = IAVG_START; |
Xiaozhe Shi | f5f966d | 2013-02-19 14:23:11 -0800 | [diff] [blame] | 3135 | } else if (temp == IAVG_INVALID) { |
| 3136 | pr_err("invalid iavg read from BMS1_DATA_REG_1, using %d\n", |
| 3137 | IAVG_START); |
| 3138 | chip->shutdown_iavg_ma = IAVG_START; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3139 | } else { |
| 3140 | if (temp == 0) { |
| 3141 | chip->shutdown_iavg_ma = IAVG_START; |
| 3142 | } else { |
| 3143 | chip->shutdown_iavg_ma = IAVG_START |
| 3144 | + IAVG_STEP_SIZE_MA * (temp + 1); |
| 3145 | } |
| 3146 | } |
| 3147 | |
| 3148 | rc = qpnp_read_wrapper(chip, &temp, |
| 3149 | chip->base + SOC_STORAGE_REG, 1); |
| 3150 | if (rc) { |
| 3151 | pr_err("failed to read addr = %d %d\n", |
| 3152 | chip->base + SOC_STORAGE_REG, rc); |
| 3153 | } else { |
| 3154 | chip->shutdown_soc = temp; |
| 3155 | |
Xiaozhe Shi | c7cbd05 | 2013-03-29 12:03:11 -0700 | [diff] [blame] | 3156 | if (chip->shutdown_soc == SOC_INVALID) { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3157 | pr_debug("No shutdown soc available\n"); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 3158 | chip->shutdown_soc_invalid = true; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3159 | chip->shutdown_iavg_ma = 0; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3160 | } |
| 3161 | } |
| 3162 | } |
| 3163 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3164 | /* read the SOC storage to determine if there was a battery removal */ |
| 3165 | rc = qpnp_read_wrapper(chip, &temp, chip->base + SOC_STORAGE_REG, 1); |
| 3166 | if (!rc) { |
| 3167 | if (temp == SOC_INVALID) |
| 3168 | chip->battery_removed = true; |
| 3169 | } |
| 3170 | |
| 3171 | |
| 3172 | pr_debug("shutdown_soc = %d shutdown_iavg = %d shutdown_soc_invalid = %d, battery_removed = %d\n", |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3173 | chip->shutdown_soc, |
| 3174 | chip->shutdown_iavg_ma, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3175 | chip->shutdown_soc_invalid, |
| 3176 | chip->battery_removed); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3177 | } |
| 3178 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3179 | static irqreturn_t bms_ocv_thr_irq_handler(int irq, void *_chip) |
| 3180 | { |
| 3181 | struct qpnp_bms_chip *chip = _chip; |
| 3182 | |
| 3183 | pr_debug("ocv_thr irq triggered\n"); |
| 3184 | bms_stay_awake(&chip->soc_wake_source); |
| 3185 | schedule_work(&chip->recalc_work); |
| 3186 | return IRQ_HANDLED; |
| 3187 | } |
| 3188 | |
| 3189 | static irqreturn_t bms_sw_cc_thr_irq_handler(int irq, void *_chip) |
| 3190 | { |
| 3191 | struct qpnp_bms_chip *chip = _chip; |
| 3192 | |
| 3193 | pr_debug("sw_cc_thr irq triggered\n"); |
| 3194 | bms_stay_awake(&chip->soc_wake_source); |
| 3195 | schedule_work(&chip->recalc_work); |
| 3196 | return IRQ_HANDLED; |
| 3197 | } |
| 3198 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3199 | static int64_t read_battery_id(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3200 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3201 | int rc; |
| 3202 | struct qpnp_vadc_result result; |
| 3203 | |
| 3204 | rc = qpnp_vadc_read(LR_MUX2_BAT_ID, &result); |
| 3205 | if (rc) { |
| 3206 | pr_err("error reading batt id channel = %d, rc = %d\n", |
| 3207 | LR_MUX2_BAT_ID, rc); |
| 3208 | return rc; |
| 3209 | } |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3210 | |
| 3211 | return result.physical; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3212 | } |
| 3213 | |
| 3214 | static int set_battery_data(struct qpnp_bms_chip *chip) |
| 3215 | { |
| 3216 | int64_t battery_id; |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3217 | int rc; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3218 | struct bms_battery_data *batt_data; |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3219 | struct device_node *node; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3220 | |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3221 | if (chip->batt_type == BATT_DESAY) { |
| 3222 | batt_data = &desay_5200_data; |
| 3223 | } else if (chip->batt_type == BATT_PALLADIUM) { |
| 3224 | batt_data = &palladium_1500_data; |
| 3225 | } else if (chip->batt_type == BATT_OEM) { |
| 3226 | batt_data = &oem_batt_data; |
Wu Fenglin | 2ac88aa | 2013-04-25 12:43:40 +0800 | [diff] [blame] | 3227 | } else if (chip->batt_type == BATT_QRD_4V35_2000MAH) { |
| 3228 | batt_data = &QRD_4v35_2000mAh_data; |
tingting | f50326f | 2013-06-05 15:07:24 +0800 | [diff] [blame] | 3229 | } else if (chip->batt_type == BATT_QRD_4V2_1300MAH) { |
| 3230 | batt_data = &qrd_4v2_1300mah_data; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3231 | } else { |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3232 | battery_id = read_battery_id(chip); |
| 3233 | if (battery_id < 0) { |
| 3234 | pr_err("cannot read battery id err = %lld\n", |
| 3235 | battery_id); |
| 3236 | return battery_id; |
| 3237 | } |
| 3238 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3239 | node = of_find_node_by_name(chip->spmi->dev.of_node, |
| 3240 | "qcom,battery-data"); |
| 3241 | if (node) { |
| 3242 | batt_data = kzalloc(sizeof(struct bms_battery_data), |
| 3243 | GFP_KERNEL); |
| 3244 | batt_data->fcc_temp_lut = kzalloc( |
| 3245 | sizeof(struct single_row_lut), |
| 3246 | GFP_KERNEL); |
| 3247 | batt_data->pc_temp_ocv_lut = kzalloc( |
| 3248 | sizeof(struct pc_temp_ocv_lut), |
| 3249 | GFP_KERNEL); |
| 3250 | batt_data->rbatt_sf_lut = kzalloc( |
| 3251 | sizeof(struct sf_lut), GFP_KERNEL); |
| 3252 | |
| 3253 | rc = of_batterydata_read_data(node, |
| 3254 | batt_data, battery_id); |
| 3255 | if (rc) { |
| 3256 | pr_err("battery data load failed, using palladium 1500\n"); |
| 3257 | kfree(batt_data->fcc_temp_lut); |
| 3258 | kfree(batt_data->pc_temp_ocv_lut); |
| 3259 | kfree(batt_data->rbatt_sf_lut); |
| 3260 | kfree(batt_data); |
| 3261 | batt_data = &palladium_1500_data; |
| 3262 | } |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3263 | } else { |
| 3264 | pr_warn("invalid battid, palladium 1500 assumed batt_id %llx\n", |
| 3265 | battery_id); |
| 3266 | batt_data = &palladium_1500_data; |
| 3267 | } |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3268 | } |
| 3269 | |
Xiaozhe Shi | 976618f | 2013-04-30 10:49:30 -0700 | [diff] [blame] | 3270 | chip->fcc_mah = batt_data->fcc; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3271 | chip->fcc_temp_lut = batt_data->fcc_temp_lut; |
| 3272 | chip->fcc_sf_lut = batt_data->fcc_sf_lut; |
| 3273 | chip->pc_temp_ocv_lut = batt_data->pc_temp_ocv_lut; |
| 3274 | chip->pc_sf_lut = batt_data->pc_sf_lut; |
| 3275 | chip->rbatt_sf_lut = batt_data->rbatt_sf_lut; |
| 3276 | chip->default_rbatt_mohm = batt_data->default_rbatt_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 3277 | chip->rbatt_capacitive_mohm = batt_data->rbatt_capacitive_mohm; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 3278 | chip->flat_ocv_threshold_uv = batt_data->flat_ocv_threshold_uv; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3279 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3280 | /* Override battery properties if specified in the battery profile */ |
| 3281 | if (batt_data->max_voltage_uv >= 0) |
| 3282 | chip->max_voltage_uv = batt_data->max_voltage_uv; |
| 3283 | if (batt_data->cutoff_uv >= 0) |
| 3284 | chip->v_cutoff_uv = batt_data->cutoff_uv; |
| 3285 | if (batt_data->iterm_ua >= 0) |
| 3286 | chip->chg_term_ua = batt_data->iterm_ua; |
| 3287 | |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3288 | if (chip->pc_temp_ocv_lut == NULL) { |
| 3289 | pr_err("temp ocv lut table is NULL\n"); |
| 3290 | return -EINVAL; |
| 3291 | } |
| 3292 | return 0; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3293 | } |
| 3294 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3295 | #define SPMI_PROP_READ(chip_prop, qpnp_spmi_property, retval) \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3296 | do { \ |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3297 | retval = of_property_read_u32(chip->spmi->dev.of_node, \ |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3298 | "qcom," qpnp_spmi_property, \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3299 | &chip->chip_prop); \ |
| 3300 | if (retval) { \ |
| 3301 | pr_err("Error reading " #qpnp_spmi_property \ |
| 3302 | " property %d\n", rc); \ |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3303 | return -EINVAL; \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3304 | } \ |
| 3305 | } while (0) |
| 3306 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3307 | #define SPMI_PROP_READ_BOOL(chip_prop, qpnp_spmi_property) \ |
| 3308 | do { \ |
| 3309 | chip->chip_prop = of_property_read_bool(chip->spmi->dev.of_node,\ |
| 3310 | "qcom," qpnp_spmi_property); \ |
| 3311 | } while (0) |
| 3312 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3313 | static inline int bms_read_properties(struct qpnp_bms_chip *chip) |
| 3314 | { |
| 3315 | int rc; |
| 3316 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 3317 | SPMI_PROP_READ(r_sense_uohm, "r-sense-uohm", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3318 | SPMI_PROP_READ(v_cutoff_uv, "v-cutoff-uv", rc); |
| 3319 | SPMI_PROP_READ(max_voltage_uv, "max-voltage-uv", rc); |
| 3320 | SPMI_PROP_READ(r_conn_mohm, "r-conn-mohm", rc); |
| 3321 | SPMI_PROP_READ(chg_term_ua, "chg-term-ua", rc); |
| 3322 | SPMI_PROP_READ(shutdown_soc_valid_limit, |
| 3323 | "shutdown-soc-valid-limit", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3324 | SPMI_PROP_READ(adjust_soc_low_threshold, |
| 3325 | "adjust-soc-low-threshold", rc); |
| 3326 | SPMI_PROP_READ(batt_type, "batt-type", rc); |
| 3327 | SPMI_PROP_READ(low_soc_calc_threshold, |
| 3328 | "low-soc-calculate-soc-threshold", rc); |
| 3329 | SPMI_PROP_READ(low_soc_calculate_soc_ms, |
| 3330 | "low-soc-calculate-soc-ms", rc); |
| 3331 | SPMI_PROP_READ(calculate_soc_ms, "calculate-soc-ms", rc); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3332 | chip->use_external_rsense = of_property_read_bool( |
| 3333 | chip->spmi->dev.of_node, |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3334 | "qcom,use-external-rsense"); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3335 | chip->ignore_shutdown_soc = of_property_read_bool( |
| 3336 | chip->spmi->dev.of_node, |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3337 | "qcom,ignore-shutdown-soc"); |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 3338 | chip->use_voltage_soc = of_property_read_bool(chip->spmi->dev.of_node, |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3339 | "qcom,use-voltage-soc"); |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3340 | chip->use_ocv_thresholds = of_property_read_bool( |
| 3341 | chip->spmi->dev.of_node, |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3342 | "qcom,use-ocv-thresholds"); |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 3343 | SPMI_PROP_READ(high_ocv_correction_limit_uv, |
| 3344 | "high-ocv-correction-limit-uv", rc); |
| 3345 | SPMI_PROP_READ(low_ocv_correction_limit_uv, |
| 3346 | "low-ocv-correction-limit-uv", rc); |
| 3347 | SPMI_PROP_READ(hold_soc_est, |
| 3348 | "hold-soc-est", rc); |
| 3349 | SPMI_PROP_READ(ocv_high_threshold_uv, |
| 3350 | "ocv-voltage-high-threshold-uv", rc); |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3351 | SPMI_PROP_READ(ocv_low_threshold_uv, |
| 3352 | "ocv-voltage-low-threshold-uv", rc); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 3353 | SPMI_PROP_READ(low_voltage_threshold, "low-voltage-threshold", rc); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 3354 | SPMI_PROP_READ(temperature_margin, "tm-temp-margin", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3355 | |
| 3356 | if (chip->adjust_soc_low_threshold >= 45) |
| 3357 | chip->adjust_soc_low_threshold = 45; |
| 3358 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3359 | SPMI_PROP_READ_BOOL(enable_fcc_learning, "enable-fcc-learning"); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3360 | if (chip->enable_fcc_learning) { |
| 3361 | SPMI_PROP_READ(min_fcc_learning_soc, |
| 3362 | "min-fcc-learning-soc", rc); |
| 3363 | SPMI_PROP_READ(min_fcc_ocv_pc, |
| 3364 | "min-fcc-ocv-pc", rc); |
| 3365 | SPMI_PROP_READ(min_fcc_learning_samples, |
| 3366 | "min-fcc-learning-samples", rc); |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3367 | SPMI_PROP_READ(fcc_resolution, |
| 3368 | "fcc-resolution", rc); |
| 3369 | if (chip->min_fcc_learning_samples > MAX_FCC_CYCLES) |
| 3370 | chip->min_fcc_learning_samples = MAX_FCC_CYCLES; |
| 3371 | chip->fcc_learning_samples = devm_kzalloc(&chip->spmi->dev, |
| 3372 | (sizeof(struct fcc_sample) * |
| 3373 | chip->min_fcc_learning_samples), GFP_KERNEL); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3374 | pr_debug("min-fcc-soc=%d, min-fcc-pc=%d, min-fcc-cycles=%d\n", |
| 3375 | chip->min_fcc_learning_soc, chip->min_fcc_ocv_pc, |
| 3376 | chip->min_fcc_learning_samples); |
| 3377 | } |
| 3378 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 3379 | pr_debug("dts data: r_sense_uohm:%d, v_cutoff_uv:%d, max_v:%d\n", |
| 3380 | chip->r_sense_uohm, chip->v_cutoff_uv, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3381 | chip->max_voltage_uv); |
| 3382 | pr_debug("r_conn:%d, shutdown_soc: %d, adjust_soc_low:%d\n", |
| 3383 | chip->r_conn_mohm, chip->shutdown_soc_valid_limit, |
| 3384 | chip->adjust_soc_low_threshold); |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 3385 | pr_debug("chg_term_ua:%d, batt_type:%d\n", |
| 3386 | chip->chg_term_ua, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3387 | chip->batt_type); |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 3388 | pr_debug("ignore_shutdown_soc:%d, use_voltage_soc:%d\n", |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 3389 | chip->ignore_shutdown_soc, chip->use_voltage_soc); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3390 | pr_debug("use external rsense: %d\n", chip->use_external_rsense); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3391 | return 0; |
| 3392 | } |
| 3393 | |
| 3394 | static inline void bms_initialize_constants(struct qpnp_bms_chip *chip) |
| 3395 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3396 | chip->prev_pc_unusable = -EINVAL; |
| 3397 | chip->soc_at_cv = -EINVAL; |
| 3398 | chip->calculated_soc = -EINVAL; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 3399 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 3400 | chip->last_soc_est = -EINVAL; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3401 | chip->battery_present = -EINVAL; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3402 | chip->battery_status = POWER_SUPPLY_STATUS_UNKNOWN; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 3403 | chip->last_cc_uah = INT_MIN; |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 3404 | chip->ocv_reading_at_100 = OCV_RAW_UNINITIALIZED; |
| 3405 | chip->prev_last_good_ocv_raw = OCV_RAW_UNINITIALIZED; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 3406 | chip->first_time_calc_soc = 1; |
| 3407 | chip->first_time_calc_uuc = 1; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3408 | } |
| 3409 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3410 | #define SPMI_FIND_IRQ(chip, irq_name) \ |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3411 | do { \ |
| 3412 | chip->irq_name##_irq.irq = spmi_get_irq_byname(chip->spmi, \ |
| 3413 | resource, #irq_name); \ |
| 3414 | if (chip->irq_name##_irq.irq < 0) { \ |
| 3415 | pr_err("Unable to get " #irq_name " irq\n"); \ |
| 3416 | return -ENXIO; \ |
| 3417 | } \ |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3418 | } while (0) |
| 3419 | |
| 3420 | static int bms_find_irqs(struct qpnp_bms_chip *chip, |
| 3421 | struct spmi_resource *resource) |
| 3422 | { |
| 3423 | SPMI_FIND_IRQ(chip, sw_cc_thr); |
| 3424 | SPMI_FIND_IRQ(chip, ocv_thr); |
| 3425 | return 0; |
| 3426 | } |
| 3427 | |
| 3428 | #define SPMI_REQUEST_IRQ(chip, rc, irq_name) \ |
| 3429 | do { \ |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3430 | rc = devm_request_irq(chip->dev, chip->irq_name##_irq.irq, \ |
| 3431 | bms_##irq_name##_irq_handler, \ |
| 3432 | IRQF_TRIGGER_RISING, #irq_name, chip); \ |
| 3433 | if (rc < 0) { \ |
| 3434 | pr_err("Unable to request " #irq_name " irq: %d\n", rc);\ |
| 3435 | return -ENXIO; \ |
| 3436 | } \ |
| 3437 | } while (0) |
| 3438 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3439 | static int bms_request_irqs(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3440 | { |
| 3441 | int rc; |
| 3442 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3443 | SPMI_REQUEST_IRQ(chip, rc, sw_cc_thr); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3444 | enable_irq_wake(chip->sw_cc_thr_irq.irq); |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3445 | SPMI_REQUEST_IRQ(chip, rc, ocv_thr); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3446 | enable_irq_wake(chip->ocv_thr_irq.irq); |
| 3447 | return 0; |
| 3448 | } |
| 3449 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3450 | #define REG_OFFSET_PERP_TYPE 0x04 |
| 3451 | #define REG_OFFSET_PERP_SUBTYPE 0x05 |
| 3452 | #define BMS_BMS_TYPE 0xD |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3453 | #define BMS_BMS1_SUBTYPE 0x1 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3454 | #define BMS_IADC_TYPE 0x8 |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3455 | #define BMS_IADC1_SUBTYPE 0x3 |
| 3456 | #define BMS_IADC2_SUBTYPE 0x5 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3457 | |
| 3458 | static int register_spmi(struct qpnp_bms_chip *chip, struct spmi_device *spmi) |
| 3459 | { |
| 3460 | struct spmi_resource *spmi_resource; |
| 3461 | struct resource *resource; |
| 3462 | int rc; |
| 3463 | u8 type, subtype; |
| 3464 | |
| 3465 | chip->dev = &(spmi->dev); |
| 3466 | chip->spmi = spmi; |
| 3467 | |
| 3468 | spmi_for_each_container_dev(spmi_resource, spmi) { |
| 3469 | if (!spmi_resource) { |
| 3470 | pr_err("qpnp_bms: spmi resource absent\n"); |
| 3471 | return -ENXIO; |
| 3472 | } |
| 3473 | |
| 3474 | resource = spmi_get_resource(spmi, spmi_resource, |
| 3475 | IORESOURCE_MEM, 0); |
| 3476 | if (!(resource && resource->start)) { |
| 3477 | pr_err("node %s IO resource absent!\n", |
| 3478 | spmi->dev.of_node->full_name); |
| 3479 | return -ENXIO; |
| 3480 | } |
| 3481 | |
| 3482 | rc = qpnp_read_wrapper(chip, &type, |
| 3483 | resource->start + REG_OFFSET_PERP_TYPE, 1); |
| 3484 | if (rc) { |
| 3485 | pr_err("Peripheral type read failed rc=%d\n", rc); |
| 3486 | return rc; |
| 3487 | } |
| 3488 | rc = qpnp_read_wrapper(chip, &subtype, |
| 3489 | resource->start + REG_OFFSET_PERP_SUBTYPE, 1); |
| 3490 | if (rc) { |
| 3491 | pr_err("Peripheral subtype read failed rc=%d\n", rc); |
| 3492 | return rc; |
| 3493 | } |
| 3494 | |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3495 | if (type == BMS_BMS_TYPE && subtype == BMS_BMS1_SUBTYPE) { |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3496 | chip->base = resource->start; |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3497 | rc = bms_find_irqs(chip, spmi_resource); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3498 | if (rc) { |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3499 | pr_err("Could not find irqs\n"); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3500 | return rc; |
| 3501 | } |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3502 | } else if (type == BMS_IADC_TYPE |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3503 | && (subtype == BMS_IADC1_SUBTYPE |
| 3504 | || subtype == BMS_IADC2_SUBTYPE)) { |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3505 | chip->iadc_base = resource->start; |
| 3506 | } else { |
| 3507 | pr_err("Invalid peripheral start=0x%x type=0x%x, subtype=0x%x\n", |
| 3508 | resource->start, type, subtype); |
| 3509 | } |
| 3510 | } |
| 3511 | |
| 3512 | if (chip->base == 0) { |
| 3513 | dev_err(&spmi->dev, "BMS peripheral was not registered\n"); |
| 3514 | return -EINVAL; |
| 3515 | } |
| 3516 | if (chip->iadc_base == 0) { |
| 3517 | dev_err(&spmi->dev, "BMS_IADC peripheral was not registered\n"); |
| 3518 | return -EINVAL; |
| 3519 | } |
| 3520 | |
| 3521 | return 0; |
| 3522 | } |
| 3523 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3524 | #define ADC_CH_SEL_MASK 0x7 |
| 3525 | #define ADC_INT_RSNSN_CTL_MASK 0x3 |
| 3526 | #define ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE 0x2 |
| 3527 | #define FAST_AVG_EN_MASK 0x80 |
| 3528 | #define FAST_AVG_EN_VALUE_EXT_RSENSE 0x80 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3529 | static int read_iadc_channel_select(struct qpnp_bms_chip *chip) |
| 3530 | { |
| 3531 | u8 iadc_channel_select; |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 3532 | int32_t rds_rsense_nohm; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3533 | int rc; |
| 3534 | |
| 3535 | rc = qpnp_read_wrapper(chip, &iadc_channel_select, |
| 3536 | chip->iadc_base + IADC1_BMS_ADC_CH_SEL_CTL, 1); |
| 3537 | if (rc) { |
| 3538 | pr_err("Error reading bms_iadc channel register %d\n", rc); |
| 3539 | return rc; |
| 3540 | } |
| 3541 | |
| 3542 | iadc_channel_select &= ADC_CH_SEL_MASK; |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 3543 | if (iadc_channel_select != EXTERNAL_RSENSE |
| 3544 | && iadc_channel_select != INTERNAL_RSENSE) { |
| 3545 | pr_err("IADC1_BMS_IADC configured incorrectly. Selected channel = %d\n", |
| 3546 | iadc_channel_select); |
| 3547 | return -EINVAL; |
| 3548 | } |
| 3549 | |
| 3550 | if (chip->use_external_rsense) { |
| 3551 | pr_debug("External rsense selected\n"); |
| 3552 | if (iadc_channel_select == INTERNAL_RSENSE) { |
| 3553 | pr_debug("Internal rsense detected; Changing rsense to external\n"); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3554 | rc = qpnp_masked_write_iadc(chip, |
| 3555 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 3556 | ADC_CH_SEL_MASK, |
| 3557 | EXTERNAL_RSENSE); |
| 3558 | if (rc) { |
| 3559 | pr_err("Unable to set IADC1_BMS channel %x to %x: %d\n", |
| 3560 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 3561 | EXTERNAL_RSENSE, rc); |
| 3562 | return rc; |
| 3563 | } |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3564 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 3565 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3566 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3567 | } |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 3568 | } else { |
| 3569 | pr_debug("Internal rsense selected\n"); |
| 3570 | if (iadc_channel_select == EXTERNAL_RSENSE) { |
| 3571 | pr_debug("External rsense detected; Changing rsense to internal\n"); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3572 | rc = qpnp_masked_write_iadc(chip, |
| 3573 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 3574 | ADC_CH_SEL_MASK, |
| 3575 | INTERNAL_RSENSE); |
| 3576 | if (rc) { |
| 3577 | pr_err("Unable to set IADC1_BMS channel %x to %x: %d\n", |
| 3578 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 3579 | INTERNAL_RSENSE, rc); |
| 3580 | return rc; |
| 3581 | } |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3582 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
| 3583 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3584 | } |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 3585 | |
| 3586 | rc = qpnp_iadc_get_rsense(&rds_rsense_nohm); |
| 3587 | if (rc) { |
| 3588 | pr_err("Unable to read RDS resistance value from IADC; rc = %d\n", |
| 3589 | rc); |
| 3590 | return rc; |
| 3591 | } |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 3592 | chip->r_sense_uohm = rds_rsense_nohm/1000; |
| 3593 | pr_debug("rds_rsense = %d nOhm, saved as %d uOhm\n", |
| 3594 | rds_rsense_nohm, chip->r_sense_uohm); |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3595 | } |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3596 | /* prevent shorting of leads by IADC_BMS when external Rsense is used */ |
| 3597 | if (chip->use_external_rsense) { |
| 3598 | if (chip->iadc_bms_revision2 > CALIB_WRKARND_DIG_MAJOR_MAX) { |
| 3599 | rc = qpnp_masked_write_iadc(chip, |
| 3600 | IADC1_BMS_ADC_INT_RSNSN_CTL, |
| 3601 | ADC_INT_RSNSN_CTL_MASK, |
| 3602 | ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE); |
| 3603 | if (rc) { |
| 3604 | pr_err("Unable to set batfet config %x to %x: %d\n", |
| 3605 | IADC1_BMS_ADC_INT_RSNSN_CTL, |
| 3606 | ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE, rc); |
| 3607 | return rc; |
| 3608 | } |
| 3609 | } else { |
| 3610 | /* In older PMICS use FAST_AVG_EN register bit 7 */ |
| 3611 | rc = qpnp_masked_write_iadc(chip, |
| 3612 | IADC1_BMS_FAST_AVG_EN, |
| 3613 | FAST_AVG_EN_MASK, |
| 3614 | FAST_AVG_EN_VALUE_EXT_RSENSE); |
| 3615 | if (rc) { |
| 3616 | pr_err("Unable to set batfet config %x to %x: %d\n", |
| 3617 | IADC1_BMS_FAST_AVG_EN, |
| 3618 | FAST_AVG_EN_VALUE_EXT_RSENSE, rc); |
| 3619 | return rc; |
| 3620 | } |
| 3621 | } |
| 3622 | } |
| 3623 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3624 | return 0; |
| 3625 | } |
| 3626 | |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 3627 | static int refresh_die_temp_monitor(struct qpnp_bms_chip *chip) |
| 3628 | { |
| 3629 | struct qpnp_vadc_result result; |
| 3630 | int rc; |
| 3631 | |
| 3632 | rc = qpnp_vadc_read(DIE_TEMP, &result); |
| 3633 | |
| 3634 | pr_debug("low = %lld, high = %lld\n", |
| 3635 | result.physical - chip->temperature_margin, |
| 3636 | result.physical + chip->temperature_margin); |
| 3637 | chip->die_temp_monitor_params.high_temp = result.physical |
| 3638 | + chip->temperature_margin; |
| 3639 | chip->die_temp_monitor_params.low_temp = result.physical |
| 3640 | - chip->temperature_margin; |
| 3641 | chip->die_temp_monitor_params.state_request = |
| 3642 | ADC_TM_HIGH_LOW_THR_ENABLE; |
| 3643 | return qpnp_adc_tm_channel_measure(&chip->die_temp_monitor_params); |
| 3644 | } |
| 3645 | |
| 3646 | static void btm_notify_die_temp(enum qpnp_tm_state state, void *ctx) |
| 3647 | { |
| 3648 | struct qpnp_bms_chip *chip = ctx; |
| 3649 | struct qpnp_vadc_result result; |
| 3650 | int rc; |
| 3651 | |
| 3652 | rc = qpnp_vadc_read(DIE_TEMP, &result); |
| 3653 | |
| 3654 | if (state == ADC_TM_LOW_STATE) |
| 3655 | pr_debug("low state triggered\n"); |
| 3656 | else if (state == ADC_TM_HIGH_STATE) |
| 3657 | pr_debug("high state triggered\n"); |
| 3658 | pr_debug("die temp = %lld, raw = 0x%x\n", |
| 3659 | result.physical, result.adc_code); |
| 3660 | schedule_work(&chip->recalc_work); |
| 3661 | refresh_die_temp_monitor(chip); |
| 3662 | } |
| 3663 | |
| 3664 | static int setup_die_temp_monitoring(struct qpnp_bms_chip *chip) |
| 3665 | { |
| 3666 | int rc = qpnp_adc_tm_is_ready(); |
| 3667 | if (rc) { |
| 3668 | pr_info("adc tm is not ready yet: %d, defer probe\n", rc); |
| 3669 | return -EPROBE_DEFER; |
| 3670 | } |
| 3671 | chip->die_temp_monitor_params.channel = DIE_TEMP; |
| 3672 | chip->die_temp_monitor_params.btm_ctx = (void *)chip; |
| 3673 | chip->die_temp_monitor_params.timer_interval = ADC_MEAS1_INTERVAL_1S; |
| 3674 | chip->die_temp_monitor_params.threshold_notification = |
| 3675 | &btm_notify_die_temp; |
| 3676 | refresh_die_temp_monitor(chip); |
| 3677 | if (rc) { |
| 3678 | pr_err("tm setup failed: %d\n", rc); |
| 3679 | return rc; |
| 3680 | } |
| 3681 | pr_debug("setup complete\n"); |
| 3682 | return 0; |
| 3683 | } |
| 3684 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3685 | static int __devinit qpnp_bms_probe(struct spmi_device *spmi) |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3686 | { |
| 3687 | struct qpnp_bms_chip *chip; |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 3688 | bool warm_reset; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3689 | int rc, vbatt; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3690 | |
| 3691 | chip = kzalloc(sizeof *chip, GFP_KERNEL); |
| 3692 | |
| 3693 | if (chip == NULL) { |
| 3694 | pr_err("kzalloc() failed.\n"); |
| 3695 | return -ENOMEM; |
| 3696 | } |
| 3697 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3698 | rc = qpnp_vadc_is_ready(); |
| 3699 | if (rc) { |
| 3700 | pr_info("vadc not ready: %d, deferring probe\n", rc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3701 | rc = -EPROBE_DEFER; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3702 | goto error_read; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3703 | } |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3704 | |
| 3705 | rc = qpnp_iadc_is_ready(); |
| 3706 | if (rc) { |
| 3707 | pr_info("iadc not ready: %d, deferring probe\n", rc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3708 | rc = -EPROBE_DEFER; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3709 | goto error_read; |
| 3710 | } |
| 3711 | |
Xiaozhe Shi | 3eaf0b6 | 2013-07-11 09:48:08 -0700 | [diff] [blame] | 3712 | mutex_init(&chip->bms_output_lock); |
| 3713 | mutex_init(&chip->last_ocv_uv_mutex); |
| 3714 | mutex_init(&chip->vbat_monitor_mutex); |
| 3715 | mutex_init(&chip->soc_invalidation_mutex); |
| 3716 | mutex_init(&chip->last_soc_mutex); |
| 3717 | |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 3718 | warm_reset = qpnp_pon_is_warm_reset(); |
| 3719 | rc = warm_reset; |
| 3720 | if (rc < 0) |
| 3721 | goto error_read; |
| 3722 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3723 | rc = register_spmi(chip, spmi); |
| 3724 | if (rc) { |
| 3725 | pr_err("error registering spmi resource %d\n", rc); |
| 3726 | goto error_resource; |
| 3727 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3728 | |
| 3729 | rc = qpnp_read_wrapper(chip, &chip->revision1, |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3730 | chip->base + REVISION1, 1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3731 | if (rc) { |
| 3732 | pr_err("error reading version register %d\n", rc); |
| 3733 | goto error_read; |
| 3734 | } |
| 3735 | |
| 3736 | rc = qpnp_read_wrapper(chip, &chip->revision2, |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3737 | chip->base + REVISION2, 1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3738 | if (rc) { |
| 3739 | pr_err("Error reading version register %d\n", rc); |
| 3740 | goto error_read; |
| 3741 | } |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 3742 | pr_debug("BMS version: %hhu.%hhu\n", chip->revision2, chip->revision1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3743 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3744 | rc = qpnp_read_wrapper(chip, &chip->iadc_bms_revision2, |
| 3745 | chip->iadc_base + REVISION2, 1); |
| 3746 | if (rc) { |
| 3747 | pr_err("Error reading version register %d\n", rc); |
| 3748 | goto error_read; |
| 3749 | } |
| 3750 | |
| 3751 | rc = qpnp_read_wrapper(chip, &chip->iadc_bms_revision1, |
| 3752 | chip->iadc_base + REVISION1, 1); |
| 3753 | if (rc) { |
| 3754 | pr_err("Error reading version register %d\n", rc); |
| 3755 | goto error_read; |
| 3756 | } |
| 3757 | pr_debug("IADC_BMS version: %hhu.%hhu\n", |
| 3758 | chip->iadc_bms_revision2, chip->iadc_bms_revision1); |
| 3759 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3760 | rc = bms_read_properties(chip); |
| 3761 | if (rc) { |
| 3762 | pr_err("Unable to read all bms properties, rc = %d\n", rc); |
| 3763 | goto error_read; |
| 3764 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3765 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3766 | rc = read_iadc_channel_select(chip); |
| 3767 | if (rc) { |
| 3768 | pr_err("Unable to get iadc selected channel = %d\n", rc); |
| 3769 | goto error_read; |
| 3770 | } |
| 3771 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3772 | if (chip->use_ocv_thresholds) { |
| 3773 | rc = set_ocv_voltage_thresholds(chip, |
| 3774 | chip->ocv_low_threshold_uv, |
| 3775 | chip->ocv_high_threshold_uv); |
| 3776 | if (rc) { |
| 3777 | pr_err("Could not set ocv voltage thresholds: %d\n", |
| 3778 | rc); |
| 3779 | goto error_read; |
| 3780 | } |
| 3781 | } |
| 3782 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3783 | rc = set_battery_data(chip); |
| 3784 | if (rc) { |
| 3785 | pr_err("Bad battery data %d\n", rc); |
| 3786 | goto error_read; |
| 3787 | } |
| 3788 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3789 | bms_initialize_constants(chip); |
| 3790 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3791 | wakeup_source_init(&chip->soc_wake_source.source, "qpnp_soc_wake"); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 3792 | wake_lock_init(&chip->low_voltage_wake_lock, WAKE_LOCK_SUSPEND, |
| 3793 | "qpnp_low_voltage_lock"); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3794 | wake_lock_init(&chip->cv_wake_lock, WAKE_LOCK_SUSPEND, |
| 3795 | "qpnp_cv_lock"); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3796 | INIT_DELAYED_WORK(&chip->calculate_soc_delayed_work, |
| 3797 | calculate_soc_work); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 3798 | INIT_WORK(&chip->recalc_work, recalculate_work); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3799 | |
| 3800 | read_shutdown_soc_and_iavg(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3801 | |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 3802 | if (chip->enable_fcc_learning) { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3803 | if (chip->battery_removed) { |
| 3804 | rc = discard_backup_fcc_data(chip); |
| 3805 | if (rc) |
| 3806 | pr_err("Could not discard backed-up FCC data\n"); |
| 3807 | } else { |
| 3808 | rc = read_chgcycle_data_from_backup(chip); |
| 3809 | if (rc) |
| 3810 | pr_err("Unable to restore charge-cycle data\n"); |
| 3811 | |
| 3812 | rc = read_fcc_data_from_backup(chip); |
| 3813 | if (rc) |
| 3814 | pr_err("Unable to restore FCC-learning data\n"); |
| 3815 | else |
| 3816 | attempt_learning_new_fcc(chip); |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 3817 | } |
| 3818 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3819 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3820 | dev_set_drvdata(&spmi->dev, chip); |
| 3821 | device_init_wakeup(&spmi->dev, 1); |
| 3822 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3823 | rc = setup_vbat_monitoring(chip); |
| 3824 | if (rc < 0) { |
| 3825 | pr_err("failed to set up voltage notifications: %d\n", rc); |
| 3826 | goto error_setup; |
Xiaozhe Shi | d5d2141 | 2013-02-06 17:14:41 -0800 | [diff] [blame] | 3827 | } |
| 3828 | |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 3829 | rc = setup_die_temp_monitoring(chip); |
| 3830 | if (rc < 0) { |
| 3831 | pr_err("failed to set up die temp notifications: %d\n", rc); |
| 3832 | goto error_setup; |
| 3833 | } |
| 3834 | |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 3835 | battery_insertion_check(chip); |
| 3836 | battery_status_check(chip); |
| 3837 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3838 | calculate_soc_work(&(chip->calculate_soc_delayed_work.work)); |
| 3839 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3840 | /* setup & register the battery power supply */ |
| 3841 | chip->bms_psy.name = "bms"; |
| 3842 | chip->bms_psy.type = POWER_SUPPLY_TYPE_BMS; |
| 3843 | chip->bms_psy.properties = msm_bms_power_props; |
| 3844 | chip->bms_psy.num_properties = ARRAY_SIZE(msm_bms_power_props); |
| 3845 | chip->bms_psy.get_property = qpnp_bms_power_get_property; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3846 | chip->bms_psy.external_power_changed = |
| 3847 | qpnp_bms_external_power_changed; |
| 3848 | chip->bms_psy.supplied_to = qpnp_bms_supplicants; |
| 3849 | chip->bms_psy.num_supplicants = ARRAY_SIZE(qpnp_bms_supplicants); |
| 3850 | |
| 3851 | rc = power_supply_register(chip->dev, &chip->bms_psy); |
| 3852 | |
| 3853 | if (rc < 0) { |
| 3854 | pr_err("power_supply_register bms failed rc = %d\n", rc); |
| 3855 | goto unregister_dc; |
| 3856 | } |
| 3857 | |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 3858 | chip->bms_psy_registered = true; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3859 | vbatt = 0; |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 3860 | rc = get_battery_voltage(&vbatt); |
| 3861 | if (rc) { |
| 3862 | pr_err("error reading vbat_sns adc channel = %d, rc = %d\n", |
| 3863 | VBAT_SNS, rc); |
| 3864 | goto unregister_dc; |
| 3865 | } |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3866 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3867 | rc = bms_request_irqs(chip); |
| 3868 | if (rc) { |
| 3869 | pr_err("error requesting bms irqs, rc = %d\n", rc); |
| 3870 | goto unregister_dc; |
| 3871 | } |
| 3872 | |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 3873 | pr_info("probe success: soc =%d vbatt = %d ocv = %d r_sense_uohm = %u warm_reset = %d\n", |
| 3874 | get_prop_bms_capacity(chip), vbatt, chip->last_ocv_uv, |
| 3875 | chip->r_sense_uohm, warm_reset); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3876 | return 0; |
| 3877 | |
| 3878 | unregister_dc: |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 3879 | chip->bms_psy_registered = false; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3880 | power_supply_unregister(&chip->bms_psy); |
| 3881 | error_setup: |
| 3882 | dev_set_drvdata(&spmi->dev, NULL); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3883 | wakeup_source_trash(&chip->soc_wake_source.source); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 3884 | wake_lock_destroy(&chip->low_voltage_wake_lock); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3885 | wake_lock_destroy(&chip->cv_wake_lock); |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3886 | error_resource: |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3887 | error_read: |
| 3888 | kfree(chip); |
| 3889 | return rc; |
| 3890 | } |
| 3891 | |
| 3892 | static int __devexit |
| 3893 | qpnp_bms_remove(struct spmi_device *spmi) |
| 3894 | { |
| 3895 | struct qpnp_bms_chip *chip = dev_get_drvdata(&spmi->dev); |
| 3896 | |
| 3897 | dev_set_drvdata(&spmi->dev, NULL); |
| 3898 | kfree(chip); |
| 3899 | return 0; |
| 3900 | } |
| 3901 | |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 3902 | static int bms_suspend(struct device *dev) |
| 3903 | { |
| 3904 | struct qpnp_bms_chip *chip = dev_get_drvdata(dev); |
| 3905 | |
| 3906 | cancel_delayed_work_sync(&chip->calculate_soc_delayed_work); |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 3907 | chip->was_charging_at_sleep = is_battery_charging(chip); |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 3908 | return 0; |
| 3909 | } |
| 3910 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3911 | static int bms_resume(struct device *dev) |
| 3912 | { |
| 3913 | int rc; |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 3914 | int soc_calc_period; |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 3915 | int time_until_next_recalc = 0; |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3916 | unsigned long time_since_last_recalc; |
| 3917 | unsigned long tm_now_sec; |
| 3918 | struct qpnp_bms_chip *chip = dev_get_drvdata(dev); |
| 3919 | |
| 3920 | rc = get_current_time(&tm_now_sec); |
| 3921 | if (rc) { |
| 3922 | pr_err("Could not read current time: %d\n", rc); |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 3923 | } else { |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3924 | if (chip->calculated_soc < chip->low_soc_calc_threshold) |
| 3925 | soc_calc_period = chip->low_soc_calculate_soc_ms; |
| 3926 | else |
| 3927 | soc_calc_period = chip->calculate_soc_ms; |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 3928 | time_since_last_recalc = tm_now_sec - chip->last_recalc_time; |
| 3929 | pr_debug("Time since last recalc: %lu\n", |
| 3930 | time_since_last_recalc); |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 3931 | time_until_next_recalc = max(0, soc_calc_period |
| 3932 | - (int)(time_since_last_recalc * 1000)); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3933 | } |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 3934 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3935 | if (time_until_next_recalc == 0) |
| 3936 | bms_stay_awake(&chip->soc_wake_source); |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 3937 | schedule_delayed_work(&chip->calculate_soc_delayed_work, |
| 3938 | round_jiffies_relative(msecs_to_jiffies |
| 3939 | (time_until_next_recalc))); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3940 | return 0; |
| 3941 | } |
| 3942 | |
| 3943 | static const struct dev_pm_ops qpnp_bms_pm_ops = { |
| 3944 | .resume = bms_resume, |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 3945 | .suspend = bms_suspend, |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3946 | }; |
| 3947 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3948 | static struct spmi_driver qpnp_bms_driver = { |
| 3949 | .probe = qpnp_bms_probe, |
| 3950 | .remove = __devexit_p(qpnp_bms_remove), |
| 3951 | .driver = { |
| 3952 | .name = QPNP_BMS_DEV_NAME, |
| 3953 | .owner = THIS_MODULE, |
| 3954 | .of_match_table = qpnp_bms_match_table, |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 3955 | .pm = &qpnp_bms_pm_ops, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3956 | }, |
| 3957 | }; |
| 3958 | |
| 3959 | static int __init qpnp_bms_init(void) |
| 3960 | { |
| 3961 | pr_info("QPNP BMS INIT\n"); |
| 3962 | return spmi_driver_register(&qpnp_bms_driver); |
| 3963 | } |
| 3964 | |
| 3965 | static void __exit qpnp_bms_exit(void) |
| 3966 | { |
| 3967 | pr_info("QPNP BMS EXIT\n"); |
| 3968 | return spmi_driver_unregister(&qpnp_bms_driver); |
| 3969 | } |
| 3970 | |
| 3971 | module_init(qpnp_bms_init); |
| 3972 | module_exit(qpnp_bms_exit); |
| 3973 | |
| 3974 | MODULE_DESCRIPTION("QPNP BMS Driver"); |
| 3975 | MODULE_LICENSE("GPL v2"); |
| 3976 | MODULE_ALIAS("platform:" QPNP_BMS_DEV_NAME); |