blob: 2663599a7c02fb041f7e1ac0485164af6ee706f4 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME "pata_hpt366"
Alanaa54ab12006-11-27 16:24:15 +000030#define DRV_VERSION "0.5.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040031
32struct hpt_clock {
33 u8 xfer_speed;
34 u32 timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
66
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
70
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
77};
78
79static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
85
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
89
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
96};
97
98static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
104
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
108
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
115};
116
117static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
126};
127
128static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
145};
146
147static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
154 unsigned char model_num[40];
155 char *s;
156 unsigned int len;
157 int i = 0;
158
159 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
160 s = &model_num[0];
161 len = strnlen(s, sizeof(model_num));
162
163 /* ATAPI specifies that empty space is blank-filled; remove blanks */
164 while ((len > 0) && (s[len - 1] == ' ')) {
165 len--;
166 s[len] = 0;
167 }
168
169 while(list[i] != NULL) {
170 if (!strncmp(list[i], s, len)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400171 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 modestr, list[i]);
173 return 1;
174 }
175 i++;
176 }
177 return 0;
178}
179
180/**
181 * hpt366_filter - mode selection filter
182 * @ap: ATA interface
183 * @adev: ATA device
184 *
185 * Block UDMA on devices that cause trouble with this controller.
186 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400187
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
189{
190 if (adev->class == ATA_DEV_ATA) {
191 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
192 mask &= ~ATA_MASK_UDMA;
193 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
194 mask &= ~(0x07 << ATA_SHIFT_UDMA);
195 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
196 mask &= ~(0x0F << ATA_SHIFT_UDMA);
197 }
198 return ata_pci_default_filter(ap, adev, mask);
199}
200
201/**
202 * hpt36x_find_mode - reset the hpt36x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400209
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400222
Jeff Garzik669a5db2006-08-29 18:12:40 -0400223static int hpt36x_pre_reset(struct ata_port *ap)
224{
Alan54083f12006-11-15 16:17:13 +0000225 static const struct pci_bits hpt36x_enable_bits[] = {
226 { 0x50, 1, 0x04, 0x04 },
227 { 0x54, 1, 0x04, 0x04 }
228 };
229
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230 u8 ata66;
231 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400232
Alan54083f12006-11-15 16:17:13 +0000233 if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no]))
234 return -ENOENT;
235
Jeff Garzik669a5db2006-08-29 18:12:40 -0400236 pci_read_config_byte(pdev, 0x5A, &ata66);
237 if (ata66 & (1 << ap->port_no))
238 ap->cbl = ATA_CBL_PATA40;
239 else
240 ap->cbl = ATA_CBL_PATA80;
241 return ata_std_prereset(ap);
242}
243
244/**
245 * hpt36x_error_handler - reset the hpt36x bus
246 * @ap: ATA port to reset
247 *
248 * Perform the reset handling for the 366/368
249 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400250
Jeff Garzik669a5db2006-08-29 18:12:40 -0400251static void hpt36x_error_handler(struct ata_port *ap)
252{
253 ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
254}
255
256/**
257 * hpt366_set_piomode - PIO setup
258 * @ap: ATA interface
259 * @adev: device on the interface
260 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400261 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400262 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400263
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
265{
266 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
267 u32 addr1, addr2;
268 u32 reg;
269 u32 mode;
270 u8 fast;
271
272 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
273 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400274
Jeff Garzik669a5db2006-08-29 18:12:40 -0400275 /* Fast interrupt prediction disable, hold off interrupt disable */
276 pci_read_config_byte(pdev, addr2, &fast);
277 if (fast & 0x80) {
278 fast &= ~0x80;
279 pci_write_config_byte(pdev, addr2, fast);
280 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400281
Jeff Garzik669a5db2006-08-29 18:12:40 -0400282 pci_read_config_dword(pdev, addr1, &reg);
283 mode = hpt36x_find_mode(ap, adev->pio_mode);
284 mode &= ~0x8000000; /* No FIFO in PIO */
285 mode &= ~0x30070000; /* Leave config bits alone */
286 reg &= 0x30070000; /* Strip timing bits */
287 pci_write_config_dword(pdev, addr1, reg | mode);
288}
289
290/**
291 * hpt366_set_dmamode - DMA timing setup
292 * @ap: ATA interface
293 * @adev: Device being configured
294 *
295 * Set up the channel for MWDMA or UDMA modes. Much the same as with
296 * PIO, load the mode number and then set MWDMA or UDMA flag.
297 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400298
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
300{
301 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
302 u32 addr1, addr2;
303 u32 reg;
304 u32 mode;
305 u8 fast;
306
307 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
308 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400309
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310 /* Fast interrupt prediction disable, hold off interrupt disable */
311 pci_read_config_byte(pdev, addr2, &fast);
312 if (fast & 0x80) {
313 fast &= ~0x80;
314 pci_write_config_byte(pdev, addr2, fast);
315 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400316
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317 pci_read_config_dword(pdev, addr1, &reg);
318 mode = hpt36x_find_mode(ap, adev->dma_mode);
319 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
320 mode &= ~0xC0000000; /* Leave config bits alone */
321 reg &= 0xC0000000; /* Strip timing bits */
322 pci_write_config_dword(pdev, addr1, reg | mode);
323}
324
325static struct scsi_host_template hpt36x_sht = {
326 .module = THIS_MODULE,
327 .name = DRV_NAME,
328 .ioctl = ata_scsi_ioctl,
329 .queuecommand = ata_scsi_queuecmd,
330 .can_queue = ATA_DEF_QUEUE,
331 .this_id = ATA_SHT_THIS_ID,
332 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400333 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
334 .emulated = ATA_SHT_EMULATED,
335 .use_clustering = ATA_SHT_USE_CLUSTERING,
336 .proc_name = DRV_NAME,
337 .dma_boundary = ATA_DMA_BOUNDARY,
338 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900339 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400340 .bios_param = ata_std_bios_param,
Alanaa54ab12006-11-27 16:24:15 +0000341 .resume = ata_scsi_device_resume,
342 .suspend = ata_scsi_device_suspend,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400343};
344
345/*
346 * Configuration for HPT366/68
347 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400348
Jeff Garzik669a5db2006-08-29 18:12:40 -0400349static struct ata_port_operations hpt366_port_ops = {
350 .port_disable = ata_port_disable,
351 .set_piomode = hpt366_set_piomode,
352 .set_dmamode = hpt366_set_dmamode,
353 .mode_filter = hpt366_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400354
Jeff Garzik669a5db2006-08-29 18:12:40 -0400355 .tf_load = ata_tf_load,
356 .tf_read = ata_tf_read,
357 .check_status = ata_check_status,
358 .exec_command = ata_exec_command,
359 .dev_select = ata_std_dev_select,
360
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
363 .error_handler = hpt36x_error_handler,
364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
365
366 .bmdma_setup = ata_bmdma_setup,
367 .bmdma_start = ata_bmdma_start,
368 .bmdma_stop = ata_bmdma_stop,
369 .bmdma_status = ata_bmdma_status,
370
371 .qc_prep = ata_qc_prep,
372 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400373
Jeff Garzik669a5db2006-08-29 18:12:40 -0400374 .data_xfer = ata_pio_data_xfer,
375
376 .irq_handler = ata_interrupt,
377 .irq_clear = ata_bmdma_irq_clear,
378
379 .port_start = ata_port_start,
380 .port_stop = ata_port_stop,
381 .host_stop = ata_host_stop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400382};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400383
384/**
Alanaa54ab12006-11-27 16:24:15 +0000385 * hpt36x_init_chipset - common chip setup
386 * @dev: PCI device
387 *
388 * Perform the chip setup work that must be done at both init and
389 * resume time
390 */
391
392static void hpt36x_init_chipset(struct pci_dev *dev)
393{
394 u8 drive_fast;
395 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
396 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
397 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
398 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
399
400 pci_read_config_byte(dev, 0x51, &drive_fast);
401 if (drive_fast & 0x80)
402 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
403}
404
405/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406 * hpt36x_init_one - Initialise an HPT366/368
407 * @dev: PCI device
408 * @id: Entry in match table
409 *
410 * Initialise an HPT36x device. There are some interesting complications
411 * here. Firstly the chip may report 366 and be one of several variants.
412 * Secondly all the timings depend on the clock for the chip which we must
413 * detect and look up
414 *
415 * This is the known chip mappings. It may be missing a couple of later
416 * releases.
417 *
418 * Chip version PCI Rev Notes
419 * HPT366 4 (HPT366) 0 UDMA66
420 * HPT366 4 (HPT366) 1 UDMA66
421 * HPT368 4 (HPT366) 2 UDMA66
422 * HPT37x/30x 4 (HPT366) 3+ Other driver
423 *
424 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400425
Jeff Garzik669a5db2006-08-29 18:12:40 -0400426static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
427{
428 static struct ata_port_info info_hpt366 = {
429 .sht = &hpt36x_sht,
430 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
431 .pio_mask = 0x1f,
432 .mwdma_mask = 0x07,
433 .udma_mask = 0x1f,
434 .port_ops = &hpt366_port_ops
435 };
436 struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
437
438 u32 class_rev;
439 u32 reg1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400440
441 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
442 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400443
Jeff Garzik669a5db2006-08-29 18:12:40 -0400444 /* May be a later chip in disguise. Check */
445 /* Newer chips are not in the HPT36x driver. Ignore them */
446 if (class_rev > 2)
447 return -ENODEV;
448
Alanaa54ab12006-11-27 16:24:15 +0000449 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400450
451 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400452
Jeff Garzik669a5db2006-08-29 18:12:40 -0400453 /* PCI clocking determines the ATA timing values to use */
454 /* info_hpt366 is safe against re-entry so we can scribble on it */
OGAWA Hirofumi2c136ef2006-10-03 01:14:03 -0700455 switch((reg1 & 0x700) >> 8) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400456 case 5:
457 info_hpt366.private_data = &hpt366_40;
458 break;
459 case 9:
460 info_hpt366.private_data = &hpt366_25;
461 break;
462 default:
463 info_hpt366.private_data = &hpt366_33;
464 break;
465 }
466 /* Now kick off ATA set up */
467 return ata_pci_init_one(dev, port_info, 2);
468}
469
Alanaa54ab12006-11-27 16:24:15 +0000470static int hpt36x_reinit_one(struct pci_dev *dev)
471{
472 hpt36x_init_chipset(dev);
473 return ata_pci_device_resume(dev);
474}
475
476
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400477static const struct pci_device_id hpt36x[] = {
478 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400479 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400480};
481
482static struct pci_driver hpt36x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400483 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400484 .id_table = hpt36x,
485 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000486 .remove = ata_pci_remove_one,
487 .suspend = ata_pci_device_suspend,
488 .resume = hpt36x_reinit_one,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400489};
490
491static int __init hpt36x_init(void)
492{
493 return pci_register_driver(&hpt36x_pci_driver);
494}
495
Jeff Garzik669a5db2006-08-29 18:12:40 -0400496static void __exit hpt36x_exit(void)
497{
498 pci_unregister_driver(&hpt36x_pci_driver);
499}
500
Jeff Garzik669a5db2006-08-29 18:12:40 -0400501MODULE_AUTHOR("Alan Cox");
502MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
503MODULE_LICENSE("GPL");
504MODULE_DEVICE_TABLE(pci, hpt36x);
505MODULE_VERSION(DRV_VERSION);
506
507module_init(hpt36x_init);
508module_exit(hpt36x_exit);