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David Gibson2ff2ae72005-11-02 13:58:22 +11001#ifndef _ASM_POWERPC_FUTEX_H
2#define _ASM_POWERPC_FUTEX_H
Jakub Jelinek4732efb2005-09-06 15:16:25 -07003
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
Jeff Dike730f4122008-04-30 00:54:49 -07007#include <linux/uaccess.h>
Jakub Jelinek4732efb2005-09-06 15:16:25 -07008#include <asm/errno.h>
Becky Brucefeaf7cf2005-09-22 14:20:04 -05009#include <asm/synch.h>
David Gibson3ddfbcf2005-11-10 12:56:55 +110010#include <asm/asm-compat.h>
Jakub Jelinek4732efb2005-09-06 15:16:25 -070011
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
David Gibson2ff2ae72005-11-02 13:58:22 +110013 __asm__ __volatile ( \
Anton Blanchard144b9c12006-01-13 15:37:17 +110014 LWSYNC_ON_SMP \
David Gibson2ff2ae72005-11-02 13:58:22 +110015"1: lwarx %0,0,%2\n" \
16 insn \
David Gibson3ddfbcf2005-11-10 12:56:55 +110017 PPC405_ERR77(0, %2) \
David Gibson2ff2ae72005-11-02 13:58:22 +110018"2: stwcx. %1,0,%2\n" \
19 "bne- 1b\n" \
20 "li %1,0\n" \
21"3: .section .fixup,\"ax\"\n" \
22"4: li %1,%3\n" \
23 "b 3b\n" \
24 ".previous\n" \
25 ".section __ex_table,\"a\"\n" \
26 ".align 3\n" \
David Gibson3ddfbcf2005-11-10 12:56:55 +110027 PPC_LONG "1b,4b,2b,4b\n" \
David Gibson2ff2ae72005-11-02 13:58:22 +110028 ".previous" \
29 : "=&r" (oldval), "=&r" (ret) \
Paul Mackerras306a8282009-04-13 14:09:09 +000030 : "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
Jakub Jelinek4732efb2005-09-06 15:16:25 -070031 : "cr0", "memory")
32
David Gibson2ff2ae72005-11-02 13:58:22 +110033static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
Jakub Jelinek4732efb2005-09-06 15:16:25 -070034{
35 int op = (encoded_op >> 28) & 7;
36 int cmp = (encoded_op >> 24) & 15;
37 int oparg = (encoded_op << 8) >> 20;
38 int cmparg = (encoded_op << 20) >> 20;
39 int oldval = 0, ret;
40 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
41 oparg = 1 << oparg;
42
43 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
44 return -EFAULT;
45
Peter Zijlstraa8663742006-12-06 20:32:20 -080046 pagefault_disable();
Jakub Jelinek4732efb2005-09-06 15:16:25 -070047
48 switch (op) {
49 case FUTEX_OP_SET:
Paul Mackerras306a8282009-04-13 14:09:09 +000050 __futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
Jakub Jelinek4732efb2005-09-06 15:16:25 -070051 break;
52 case FUTEX_OP_ADD:
Paul Mackerras306a8282009-04-13 14:09:09 +000053 __futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
Jakub Jelinek4732efb2005-09-06 15:16:25 -070054 break;
55 case FUTEX_OP_OR:
Paul Mackerras306a8282009-04-13 14:09:09 +000056 __futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
Jakub Jelinek4732efb2005-09-06 15:16:25 -070057 break;
58 case FUTEX_OP_ANDN:
Paul Mackerras306a8282009-04-13 14:09:09 +000059 __futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
Jakub Jelinek4732efb2005-09-06 15:16:25 -070060 break;
61 case FUTEX_OP_XOR:
Paul Mackerras306a8282009-04-13 14:09:09 +000062 __futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
Jakub Jelinek4732efb2005-09-06 15:16:25 -070063 break;
64 default:
65 ret = -ENOSYS;
66 }
67
Peter Zijlstraa8663742006-12-06 20:32:20 -080068 pagefault_enable();
Jakub Jelinek4732efb2005-09-06 15:16:25 -070069
70 if (!ret) {
71 switch (cmp) {
72 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
73 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
74 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
75 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
76 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
77 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
78 default: ret = -ENOSYS;
79 }
80 }
81 return ret;
82}
83
Ingo Molnare9056f12006-03-27 01:16:21 -080084static inline int
Ingo Molnar8f17d3a2006-03-27 01:16:27 -080085futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
Ingo Molnare9056f12006-03-27 01:16:21 -080086{
David Woodhouse69588292006-09-04 21:53:14 -070087 int prev;
88
89 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
90 return -EFAULT;
91
92 __asm__ __volatile__ (
93 LWSYNC_ON_SMP
94"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\
95 cmpw 0,%0,%3\n\
96 bne- 3f\n"
97 PPC405_ERR77(0,%2)
98"2: stwcx. %4,0,%2\n\
99 bne- 1b\n"
100 ISYNC_ON_SMP
101"3: .section .fixup,\"ax\"\n\
1024: li %0,%5\n\
103 b 3b\n\
104 .previous\n\
105 .section __ex_table,\"a\"\n\
106 .align 3\n\
107 " PPC_LONG "1b,4b,2b,4b\n\
108 .previous" \
109 : "=&r" (prev), "+m" (*uaddr)
110 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
111 : "cc", "memory");
112
113 return prev;
Ingo Molnare9056f12006-03-27 01:16:21 -0800114}
115
David Gibson2ff2ae72005-11-02 13:58:22 +1100116#endif /* __KERNEL__ */
117#endif /* _ASM_POWERPC_FUTEX_H */