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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <drm/drmP.h>
34#include "radeon_drm.h"
35#include "radeon.h"
36
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037
38int radeon_ttm_init(struct radeon_device *rdev);
39void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010040static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
42/*
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
45 */
46
Jerome Glisse4c788672009-11-20 14:29:23 +010047static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020048{
Jerome Glisse4c788672009-11-20 14:29:23 +010049 struct radeon_bo *bo;
50
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
56 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057}
58
Jerome Glisse4c788672009-11-20 14:29:23 +010059static inline u32 radeon_ttm_flags_from_domain(u32 domain)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020060{
Jerome Glisse4c788672009-11-20 14:29:23 +010061 u32 flags = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020062
Jerome Glisse771fe6b2009-06-05 14:42:42 +020063 if (domain & RADEON_GEM_DOMAIN_VRAM) {
Michel Dänzer664f8652009-07-28 12:30:57 +020064 flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020065 }
66 if (domain & RADEON_GEM_DOMAIN_GTT) {
Jerome Glisse985fe842009-07-29 18:55:53 +020067 flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020068 }
69 if (domain & RADEON_GEM_DOMAIN_CPU) {
Michel Dänzer664f8652009-07-28 12:30:57 +020070 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020071 }
72 if (!flags) {
Michel Dänzer664f8652009-07-28 12:30:57 +020073 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020074 }
75 return flags;
76}
77
Jerome Glisse312ea8d2009-12-07 15:52:58 +010078void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
79{
80 u32 c = 0;
81
82 rbo->placement.fpfn = 0;
83 rbo->placement.lpfn = 0;
84 rbo->placement.placement = rbo->placements;
85 rbo->placement.busy_placement = rbo->placements;
86 if (domain & RADEON_GEM_DOMAIN_VRAM)
87 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
88 TTM_PL_FLAG_VRAM;
89 if (domain & RADEON_GEM_DOMAIN_GTT)
90 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
91 if (domain & RADEON_GEM_DOMAIN_CPU)
92 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
93 rbo->placement.num_placement = c;
94 rbo->placement.num_busy_placement = c;
95}
96
Jerome Glisse4c788672009-11-20 14:29:23 +010097int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
98 unsigned long size, bool kernel, u32 domain,
99 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200100{
Jerome Glisse4c788672009-11-20 14:29:23 +0100101 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200102 enum ttm_bo_type type;
Jerome Glisse4c788672009-11-20 14:29:23 +0100103 u32 flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200104 int r;
105
106 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
107 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
108 }
109 if (kernel) {
110 type = ttm_bo_type_kernel;
111 } else {
112 type = ttm_bo_type_device;
113 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100114 *bo_ptr = NULL;
115 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
116 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200117 return -ENOMEM;
Jerome Glisse4c788672009-11-20 14:29:23 +0100118 bo->rdev = rdev;
119 bo->gobj = gobj;
120 bo->surface_reg = -1;
121 INIT_LIST_HEAD(&bo->list);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122
Jerome Glisse4c788672009-11-20 14:29:23 +0100123 flags = radeon_ttm_flags_from_domain(domain);
124retry:
125 r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
126 flags, 0, 0, true, NULL, size,
127 &radeon_ttm_bo_destroy);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100129 if (r == -ERESTART)
130 goto retry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200131 /* ttm call radeon_ttm_object_object_destroy if error happen */
Jerome Glisse4c788672009-11-20 14:29:23 +0100132 dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
133 size, flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200134 return r;
135 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100136 *bo_ptr = bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200137 if (gobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100138 mutex_lock(&bo->rdev->gem.mutex);
139 list_add_tail(&bo->list, &rdev->gem.objects);
140 mutex_unlock(&bo->rdev->gem.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200141 }
142 return 0;
143}
144
Jerome Glisse4c788672009-11-20 14:29:23 +0100145int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200146{
Jerome Glisse4c788672009-11-20 14:29:23 +0100147 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200148 int r;
149
Jerome Glisse4c788672009-11-20 14:29:23 +0100150 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200151 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100152 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200154 return 0;
155 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100156 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157 if (r) {
158 return r;
159 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100160 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100162 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100164 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200165 return 0;
166}
167
Jerome Glisse4c788672009-11-20 14:29:23 +0100168void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200169{
Jerome Glisse4c788672009-11-20 14:29:23 +0100170 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200171 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100172 bo->kptr = NULL;
173 radeon_bo_check_tiling(bo, 0, 0);
174 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200175}
176
Jerome Glisse4c788672009-11-20 14:29:23 +0100177void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200178{
Jerome Glisse4c788672009-11-20 14:29:23 +0100179 struct ttm_buffer_object *tbo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180
Jerome Glisse4c788672009-11-20 14:29:23 +0100181 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200182 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100183 tbo = &((*bo)->tbo);
184 ttm_bo_unref(&tbo);
185 if (tbo == NULL)
186 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200187}
188
Jerome Glisse4c788672009-11-20 14:29:23 +0100189int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100191 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200192
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100193 radeon_ttm_placement_from_domain(bo, domain);
Jerome Glisse4c788672009-11-20 14:29:23 +0100194 if (bo->pin_count) {
195 bo->pin_count++;
196 if (gpu_addr)
197 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200198 return 0;
199 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100200 radeon_ttm_placement_from_domain(bo, domain);
201 for (i = 0; i < bo->placement.num_placement; i++)
202 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
Jerome Glisse4c788672009-11-20 14:29:23 +0100203retry:
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100204 r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100205 if (likely(r == 0)) {
206 bo->pin_count = 1;
207 if (gpu_addr != NULL)
208 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100211 if (r == -ERESTART)
212 goto retry;
213 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200214 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215 return r;
216}
217
Jerome Glisse4c788672009-11-20 14:29:23 +0100218int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100220 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200221
Jerome Glisse4c788672009-11-20 14:29:23 +0100222 if (!bo->pin_count) {
223 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
224 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200225 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100226 bo->pin_count--;
227 if (bo->pin_count)
228 return 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100229 for (i = 0; i < bo->placement.num_placement; i++)
230 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
Jerome Glisse4c788672009-11-20 14:29:23 +0100231retry:
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100232 r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200233 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100234 if (r == -ERESTART)
235 goto retry;
236 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237 return r;
238 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100239 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200240}
241
Jerome Glisse4c788672009-11-20 14:29:23 +0100242int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200243{
244 if (rdev->flags & RADEON_IS_IGP) {
245 /* Useless to evict on IGP chips */
246 return 0;
247 }
248 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
249}
250
Jerome Glisse4c788672009-11-20 14:29:23 +0100251void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200252{
Jerome Glisse4c788672009-11-20 14:29:23 +0100253 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254 struct drm_gem_object *gobj;
255
256 if (list_empty(&rdev->gem.objects)) {
257 return;
258 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100259 dev_err(rdev->dev, "Userspace still has active objects !\n");
260 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100262 gobj = bo->gobj;
263 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
264 gobj, bo, (unsigned long)gobj->size,
265 *((unsigned long *)&gobj->refcount));
266 mutex_lock(&bo->rdev->gem.mutex);
267 list_del_init(&bo->list);
268 mutex_unlock(&bo->rdev->gem.mutex);
269 radeon_bo_unref(&bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200270 gobj->driver_private = NULL;
271 drm_gem_object_unreference(gobj);
272 mutex_unlock(&rdev->ddev->struct_mutex);
273 }
274}
275
Jerome Glisse4c788672009-11-20 14:29:23 +0100276int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200277{
Jerome Glissea4d68272009-09-11 13:00:43 +0200278 /* Add an MTRR for the VRAM */
279 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
280 MTRR_TYPE_WRCOMB, 1);
281 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
282 rdev->mc.mc_vram_size >> 20,
283 (unsigned long long)rdev->mc.aper_size >> 20);
284 DRM_INFO("RAM width %dbits %cDR\n",
285 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286 return radeon_ttm_init(rdev);
287}
288
Jerome Glisse4c788672009-11-20 14:29:23 +0100289void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200290{
291 radeon_ttm_fini(rdev);
292}
293
Jerome Glisse4c788672009-11-20 14:29:23 +0100294void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
295 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200296{
297 if (lobj->wdomain) {
298 list_add(&lobj->list, head);
299 } else {
300 list_add_tail(&lobj->list, head);
301 }
302}
303
Jerome Glisse4c788672009-11-20 14:29:23 +0100304int radeon_bo_list_reserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305{
Jerome Glisse4c788672009-11-20 14:29:23 +0100306 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200307 int r;
308
Dave Airlie9d8401f2009-10-08 09:28:19 +1000309 list_for_each_entry(lobj, head, list){
Jerome Glisse4c788672009-11-20 14:29:23 +0100310 r = radeon_bo_reserve(lobj->bo, false);
311 if (unlikely(r != 0))
312 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200313 }
314 return 0;
315}
316
Jerome Glisse4c788672009-11-20 14:29:23 +0100317void radeon_bo_list_unreserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318{
Jerome Glisse4c788672009-11-20 14:29:23 +0100319 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200320
Dave Airlie9d8401f2009-10-08 09:28:19 +1000321 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100322 /* only unreserve object we successfully reserved */
323 if (radeon_bo_is_reserved(lobj->bo))
324 radeon_bo_unreserve(lobj->bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200325 }
326}
327
Jerome Glisse4c788672009-11-20 14:29:23 +0100328int radeon_bo_list_validate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200329{
Jerome Glisse4c788672009-11-20 14:29:23 +0100330 struct radeon_bo_list *lobj;
331 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 struct radeon_fence *old_fence = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200333 int r;
334
Jerome Glisse4c788672009-11-20 14:29:23 +0100335 r = radeon_bo_list_reserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200336 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200337 return r;
338 }
Dave Airlie9d8401f2009-10-08 09:28:19 +1000339 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100340 bo = lobj->bo;
341 if (!bo->pin_count) {
Michel Dänzer664f8652009-07-28 12:30:57 +0200342 if (lobj->wdomain) {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100343 radeon_ttm_placement_from_domain(bo,
344 lobj->wdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200345 } else {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100346 radeon_ttm_placement_from_domain(bo,
347 lobj->rdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200348 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100349retry:
350 r = ttm_buffer_object_validate(&bo->tbo,
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100351 &bo->placement,
Jerome Glisse4c788672009-11-20 14:29:23 +0100352 true, false);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200353 if (unlikely(r)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100354 if (r == -ERESTART)
355 goto retry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200356 return r;
357 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200358 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100359 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
360 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200361 if (fence) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100362 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
363 bo->tbo.sync_obj = radeon_fence_ref(fence);
364 bo->tbo.sync_obj_arg = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200365 }
366 if (old_fence) {
367 radeon_fence_unref(&old_fence);
368 }
369 }
370 return 0;
371}
372
Jerome Glisse4c788672009-11-20 14:29:23 +0100373void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374{
Jerome Glisse4c788672009-11-20 14:29:23 +0100375 struct radeon_bo_list *lobj;
376 struct radeon_fence *old_fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200377
Jerome Glisse4c788672009-11-20 14:29:23 +0100378 if (fence)
379 list_for_each_entry(lobj, head, list) {
380 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
381 if (old_fence == fence) {
382 lobj->bo->tbo.sync_obj = NULL;
383 radeon_fence_unref(&old_fence);
384 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200385 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100386 radeon_bo_list_unreserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200387}
388
Jerome Glisse4c788672009-11-20 14:29:23 +0100389int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200390 struct vm_area_struct *vma)
391{
Jerome Glisse4c788672009-11-20 14:29:23 +0100392 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200393}
394
Jerome Glisse4c788672009-11-20 14:29:23 +0100395static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200396{
Jerome Glisse4c788672009-11-20 14:29:23 +0100397 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000398 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100399 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000400 int steal;
401 int i;
402
Jerome Glisse4c788672009-11-20 14:29:23 +0100403 BUG_ON(!atomic_read(&bo->tbo.reserved));
404
405 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000406 return 0;
407
Jerome Glisse4c788672009-11-20 14:29:23 +0100408 if (bo->surface_reg >= 0) {
409 reg = &rdev->surface_regs[bo->surface_reg];
410 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000411 goto out;
412 }
413
414 steal = -1;
415 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
416
417 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100418 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000419 break;
420
Jerome Glisse4c788672009-11-20 14:29:23 +0100421 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000422 if (old_object->pin_count == 0)
423 steal = i;
424 }
425
426 /* if we are all out */
427 if (i == RADEON_GEM_MAX_SURFACES) {
428 if (steal == -1)
429 return -ENOMEM;
430 /* find someone with a surface reg and nuke their BO */
431 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100432 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000433 /* blow away the mapping */
434 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100435 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000436 old_object->surface_reg = -1;
437 i = steal;
438 }
439
Jerome Glisse4c788672009-11-20 14:29:23 +0100440 bo->surface_reg = i;
441 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000442
443out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100444 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
445 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
446 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000447 return 0;
448}
449
Jerome Glisse4c788672009-11-20 14:29:23 +0100450static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000451{
Jerome Glisse4c788672009-11-20 14:29:23 +0100452 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000453 struct radeon_surface_reg *reg;
454
Jerome Glisse4c788672009-11-20 14:29:23 +0100455 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000456 return;
457
Jerome Glisse4c788672009-11-20 14:29:23 +0100458 reg = &rdev->surface_regs[bo->surface_reg];
459 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000460
Jerome Glisse4c788672009-11-20 14:29:23 +0100461 reg->bo = NULL;
462 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000463}
464
Jerome Glisse4c788672009-11-20 14:29:23 +0100465int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
466 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000467{
Jerome Glisse4c788672009-11-20 14:29:23 +0100468 int r;
469
470 r = radeon_bo_reserve(bo, false);
471 if (unlikely(r != 0))
472 return r;
473 bo->tiling_flags = tiling_flags;
474 bo->pitch = pitch;
475 radeon_bo_unreserve(bo);
476 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000477}
478
Jerome Glisse4c788672009-11-20 14:29:23 +0100479void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
480 uint32_t *tiling_flags,
481 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000482{
Jerome Glisse4c788672009-11-20 14:29:23 +0100483 BUG_ON(!atomic_read(&bo->tbo.reserved));
Dave Airliee024e112009-06-24 09:48:08 +1000484 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100485 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000486 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100487 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000488}
489
Jerome Glisse4c788672009-11-20 14:29:23 +0100490int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
491 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000492{
Jerome Glisse4c788672009-11-20 14:29:23 +0100493 BUG_ON(!atomic_read(&bo->tbo.reserved));
494
495 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000496 return 0;
497
498 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100499 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000500 return 0;
501 }
502
Jerome Glisse4c788672009-11-20 14:29:23 +0100503 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000504 if (!has_moved)
505 return 0;
506
Jerome Glisse4c788672009-11-20 14:29:23 +0100507 if (bo->surface_reg >= 0)
508 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000509 return 0;
510 }
511
Jerome Glisse4c788672009-11-20 14:29:23 +0100512 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000513 return 0;
514
Jerome Glisse4c788672009-11-20 14:29:23 +0100515 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000516}
517
518void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glisse4c788672009-11-20 14:29:23 +0100519 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000520{
Jerome Glisse4c788672009-11-20 14:29:23 +0100521 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
522 radeon_bo_check_tiling(rbo, 0, 1);
Dave Airliee024e112009-06-24 09:48:08 +1000523}
524
525void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
526{
Jerome Glisse4c788672009-11-20 14:29:23 +0100527 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
528 radeon_bo_check_tiling(rbo, 0, 0);
Dave Airliee024e112009-06-24 09:48:08 +1000529}