Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <linux/list.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include "radeon_drm.h" |
| 35 | #include "radeon.h" |
| 36 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | |
| 38 | int radeon_ttm_init(struct radeon_device *rdev); |
| 39 | void radeon_ttm_fini(struct radeon_device *rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 40 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
| 44 | * function are calling it. |
| 45 | */ |
| 46 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 47 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 49 | struct radeon_bo *bo; |
| 50 | |
| 51 | bo = container_of(tbo, struct radeon_bo, tbo); |
| 52 | mutex_lock(&bo->rdev->gem.mutex); |
| 53 | list_del_init(&bo->list); |
| 54 | mutex_unlock(&bo->rdev->gem.mutex); |
| 55 | radeon_bo_clear_surface_reg(bo); |
| 56 | kfree(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | } |
| 58 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 59 | static inline u32 radeon_ttm_flags_from_domain(u32 domain) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 60 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 61 | u32 flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 62 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 64 | flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | } |
| 66 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
Jerome Glisse | 985fe84 | 2009-07-29 18:55:53 +0200 | [diff] [blame] | 67 | flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | } |
| 69 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 70 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | } |
| 72 | if (!flags) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 73 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 74 | } |
| 75 | return flags; |
| 76 | } |
| 77 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 78 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
| 79 | { |
| 80 | u32 c = 0; |
| 81 | |
| 82 | rbo->placement.fpfn = 0; |
| 83 | rbo->placement.lpfn = 0; |
| 84 | rbo->placement.placement = rbo->placements; |
| 85 | rbo->placement.busy_placement = rbo->placements; |
| 86 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
| 87 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
| 88 | TTM_PL_FLAG_VRAM; |
| 89 | if (domain & RADEON_GEM_DOMAIN_GTT) |
| 90 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 91 | if (domain & RADEON_GEM_DOMAIN_CPU) |
| 92 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
| 93 | rbo->placement.num_placement = c; |
| 94 | rbo->placement.num_busy_placement = c; |
| 95 | } |
| 96 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 97 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
| 98 | unsigned long size, bool kernel, u32 domain, |
| 99 | struct radeon_bo **bo_ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 100 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 101 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 102 | enum ttm_bo_type type; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 103 | u32 flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | int r; |
| 105 | |
| 106 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 107 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 108 | } |
| 109 | if (kernel) { |
| 110 | type = ttm_bo_type_kernel; |
| 111 | } else { |
| 112 | type = ttm_bo_type_device; |
| 113 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 114 | *bo_ptr = NULL; |
| 115 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
| 116 | if (bo == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 117 | return -ENOMEM; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 118 | bo->rdev = rdev; |
| 119 | bo->gobj = gobj; |
| 120 | bo->surface_reg = -1; |
| 121 | INIT_LIST_HEAD(&bo->list); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 123 | flags = radeon_ttm_flags_from_domain(domain); |
| 124 | retry: |
| 125 | r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type, |
| 126 | flags, 0, 0, true, NULL, size, |
| 127 | &radeon_ttm_bo_destroy); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 128 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 129 | if (r == -ERESTART) |
| 130 | goto retry; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 131 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 132 | dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n", |
| 133 | size, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 134 | return r; |
| 135 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 136 | *bo_ptr = bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 137 | if (gobj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 138 | mutex_lock(&bo->rdev->gem.mutex); |
| 139 | list_add_tail(&bo->list, &rdev->gem.objects); |
| 140 | mutex_unlock(&bo->rdev->gem.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | } |
| 142 | return 0; |
| 143 | } |
| 144 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 145 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 146 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 147 | bool is_iomem; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | int r; |
| 149 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 150 | if (bo->kptr) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 152 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 153 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | return 0; |
| 155 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 156 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | if (r) { |
| 158 | return r; |
| 159 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 160 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 162 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 164 | radeon_bo_check_tiling(bo, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 168 | void radeon_bo_kunmap(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 170 | if (bo->kptr == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 171 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 172 | bo->kptr = NULL; |
| 173 | radeon_bo_check_tiling(bo, 0, 0); |
| 174 | ttm_bo_kunmap(&bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | } |
| 176 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 177 | void radeon_bo_unref(struct radeon_bo **bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 178 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 179 | struct ttm_buffer_object *tbo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 181 | if ((*bo) == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 182 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 183 | tbo = &((*bo)->tbo); |
| 184 | ttm_bo_unref(&tbo); |
| 185 | if (tbo == NULL) |
| 186 | *bo = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 187 | } |
| 188 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 189 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 190 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 191 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 192 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 193 | radeon_ttm_placement_from_domain(bo, domain); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 194 | if (bo->pin_count) { |
| 195 | bo->pin_count++; |
| 196 | if (gpu_addr) |
| 197 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 198 | return 0; |
| 199 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 200 | radeon_ttm_placement_from_domain(bo, domain); |
| 201 | for (i = 0; i < bo->placement.num_placement; i++) |
| 202 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 203 | retry: |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 204 | r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 205 | if (likely(r == 0)) { |
| 206 | bo->pin_count = 1; |
| 207 | if (gpu_addr != NULL) |
| 208 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 210 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 211 | if (r == -ERESTART) |
| 212 | goto retry; |
| 213 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 214 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 215 | return r; |
| 216 | } |
| 217 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 218 | int radeon_bo_unpin(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 220 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 221 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 222 | if (!bo->pin_count) { |
| 223 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
| 224 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 226 | bo->pin_count--; |
| 227 | if (bo->pin_count) |
| 228 | return 0; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 229 | for (i = 0; i < bo->placement.num_placement; i++) |
| 230 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 231 | retry: |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 232 | r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 233 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 234 | if (r == -ERESTART) |
| 235 | goto retry; |
| 236 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | return r; |
| 238 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 239 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | } |
| 241 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 242 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 243 | { |
| 244 | if (rdev->flags & RADEON_IS_IGP) { |
| 245 | /* Useless to evict on IGP chips */ |
| 246 | return 0; |
| 247 | } |
| 248 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 249 | } |
| 250 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 251 | void radeon_bo_force_delete(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 253 | struct radeon_bo *bo, *n; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 254 | struct drm_gem_object *gobj; |
| 255 | |
| 256 | if (list_empty(&rdev->gem.objects)) { |
| 257 | return; |
| 258 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 259 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
| 260 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 261 | mutex_lock(&rdev->ddev->struct_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 262 | gobj = bo->gobj; |
| 263 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
| 264 | gobj, bo, (unsigned long)gobj->size, |
| 265 | *((unsigned long *)&gobj->refcount)); |
| 266 | mutex_lock(&bo->rdev->gem.mutex); |
| 267 | list_del_init(&bo->list); |
| 268 | mutex_unlock(&bo->rdev->gem.mutex); |
| 269 | radeon_bo_unref(&bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | gobj->driver_private = NULL; |
| 271 | drm_gem_object_unreference(gobj); |
| 272 | mutex_unlock(&rdev->ddev->struct_mutex); |
| 273 | } |
| 274 | } |
| 275 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 276 | int radeon_bo_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 277 | { |
Jerome Glisse | a4d6827 | 2009-09-11 13:00:43 +0200 | [diff] [blame] | 278 | /* Add an MTRR for the VRAM */ |
| 279 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| 280 | MTRR_TYPE_WRCOMB, 1); |
| 281 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
| 282 | rdev->mc.mc_vram_size >> 20, |
| 283 | (unsigned long long)rdev->mc.aper_size >> 20); |
| 284 | DRM_INFO("RAM width %dbits %cDR\n", |
| 285 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | return radeon_ttm_init(rdev); |
| 287 | } |
| 288 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 289 | void radeon_bo_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 290 | { |
| 291 | radeon_ttm_fini(rdev); |
| 292 | } |
| 293 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 294 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
| 295 | struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 296 | { |
| 297 | if (lobj->wdomain) { |
| 298 | list_add(&lobj->list, head); |
| 299 | } else { |
| 300 | list_add_tail(&lobj->list, head); |
| 301 | } |
| 302 | } |
| 303 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 304 | int radeon_bo_list_reserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 305 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 306 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 307 | int r; |
| 308 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 309 | list_for_each_entry(lobj, head, list){ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 310 | r = radeon_bo_reserve(lobj->bo, false); |
| 311 | if (unlikely(r != 0)) |
| 312 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | } |
| 314 | return 0; |
| 315 | } |
| 316 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 317 | void radeon_bo_list_unreserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 319 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 320 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 321 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 322 | /* only unreserve object we successfully reserved */ |
| 323 | if (radeon_bo_is_reserved(lobj->bo)) |
| 324 | radeon_bo_unreserve(lobj->bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 325 | } |
| 326 | } |
| 327 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 328 | int radeon_bo_list_validate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 329 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 330 | struct radeon_bo_list *lobj; |
| 331 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 332 | struct radeon_fence *old_fence = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 333 | int r; |
| 334 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 335 | r = radeon_bo_list_reserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 336 | if (unlikely(r != 0)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | return r; |
| 338 | } |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 339 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 340 | bo = lobj->bo; |
| 341 | if (!bo->pin_count) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 342 | if (lobj->wdomain) { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 343 | radeon_ttm_placement_from_domain(bo, |
| 344 | lobj->wdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 345 | } else { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 346 | radeon_ttm_placement_from_domain(bo, |
| 347 | lobj->rdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 348 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 349 | retry: |
| 350 | r = ttm_buffer_object_validate(&bo->tbo, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame^] | 351 | &bo->placement, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 352 | true, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 353 | if (unlikely(r)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 354 | if (r == -ERESTART) |
| 355 | goto retry; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | return r; |
| 357 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 358 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 359 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
| 360 | lobj->tiling_flags = bo->tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | if (fence) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 362 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; |
| 363 | bo->tbo.sync_obj = radeon_fence_ref(fence); |
| 364 | bo->tbo.sync_obj_arg = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 365 | } |
| 366 | if (old_fence) { |
| 367 | radeon_fence_unref(&old_fence); |
| 368 | } |
| 369 | } |
| 370 | return 0; |
| 371 | } |
| 372 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 373 | void radeon_bo_list_unvalidate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 374 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 375 | struct radeon_bo_list *lobj; |
| 376 | struct radeon_fence *old_fence; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 377 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 378 | if (fence) |
| 379 | list_for_each_entry(lobj, head, list) { |
| 380 | old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); |
| 381 | if (old_fence == fence) { |
| 382 | lobj->bo->tbo.sync_obj = NULL; |
| 383 | radeon_fence_unref(&old_fence); |
| 384 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 385 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 386 | radeon_bo_list_unreserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 387 | } |
| 388 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 389 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 390 | struct vm_area_struct *vma) |
| 391 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 392 | return ttm_fbdev_mmap(vma, &bo->tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 393 | } |
| 394 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 395 | static int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 397 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 398 | struct radeon_surface_reg *reg; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 399 | struct radeon_bo *old_object; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 400 | int steal; |
| 401 | int i; |
| 402 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 403 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 404 | |
| 405 | if (!bo->tiling_flags) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 406 | return 0; |
| 407 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 408 | if (bo->surface_reg >= 0) { |
| 409 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 410 | i = bo->surface_reg; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 411 | goto out; |
| 412 | } |
| 413 | |
| 414 | steal = -1; |
| 415 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 416 | |
| 417 | reg = &rdev->surface_regs[i]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 418 | if (!reg->bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 419 | break; |
| 420 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 421 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 422 | if (old_object->pin_count == 0) |
| 423 | steal = i; |
| 424 | } |
| 425 | |
| 426 | /* if we are all out */ |
| 427 | if (i == RADEON_GEM_MAX_SURFACES) { |
| 428 | if (steal == -1) |
| 429 | return -ENOMEM; |
| 430 | /* find someone with a surface reg and nuke their BO */ |
| 431 | reg = &rdev->surface_regs[steal]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 432 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 433 | /* blow away the mapping */ |
| 434 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 435 | ttm_bo_unmap_virtual(&old_object->tbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 436 | old_object->surface_reg = -1; |
| 437 | i = steal; |
| 438 | } |
| 439 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 440 | bo->surface_reg = i; |
| 441 | reg->bo = bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 442 | |
| 443 | out: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 444 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
| 445 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, |
| 446 | bo->tbo.num_pages << PAGE_SHIFT); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 447 | return 0; |
| 448 | } |
| 449 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 450 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 451 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 452 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 453 | struct radeon_surface_reg *reg; |
| 454 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 455 | if (bo->surface_reg == -1) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 456 | return; |
| 457 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 458 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 459 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 460 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 461 | reg->bo = NULL; |
| 462 | bo->surface_reg = -1; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 463 | } |
| 464 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 465 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 466 | uint32_t tiling_flags, uint32_t pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 467 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 468 | int r; |
| 469 | |
| 470 | r = radeon_bo_reserve(bo, false); |
| 471 | if (unlikely(r != 0)) |
| 472 | return r; |
| 473 | bo->tiling_flags = tiling_flags; |
| 474 | bo->pitch = pitch; |
| 475 | radeon_bo_unreserve(bo); |
| 476 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 477 | } |
| 478 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 479 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 480 | uint32_t *tiling_flags, |
| 481 | uint32_t *pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 482 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 483 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 484 | if (tiling_flags) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 485 | *tiling_flags = bo->tiling_flags; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 486 | if (pitch) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 487 | *pitch = bo->pitch; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 488 | } |
| 489 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 490 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 491 | bool force_drop) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 492 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 493 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 494 | |
| 495 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 496 | return 0; |
| 497 | |
| 498 | if (force_drop) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 499 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 500 | return 0; |
| 501 | } |
| 502 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 503 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 504 | if (!has_moved) |
| 505 | return 0; |
| 506 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 507 | if (bo->surface_reg >= 0) |
| 508 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 509 | return 0; |
| 510 | } |
| 511 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 512 | if ((bo->surface_reg >= 0) && !has_moved) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 513 | return 0; |
| 514 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 515 | return radeon_bo_get_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 519 | struct ttm_mem_reg *mem) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 520 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 521 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 522 | radeon_bo_check_tiling(rbo, 0, 1); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 523 | } |
| 524 | |
| 525 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
| 526 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 527 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 528 | radeon_bo_check_tiling(rbo, 0, 0); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 529 | } |