blob: 08877652e321f8579d350effa6b0531be12f2be1 [file] [log] [blame]
Hans Verkuil1c1e45d2008-04-28 20:24:33 -03001/*
2 * cx18 System Control Block initialization
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
Andy Walls6afdeaf2010-05-23 18:53:35 -03005 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
Hans Verkuil1c1e45d2008-04-28 20:24:33 -03006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307 USA
21 */
22
23#ifndef CX18_SCB_H
24#define CX18_SCB_H
25
26#include "cx18-mailbox.h"
27
28/* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
29 are in the SW1 register. */
30
31#define IRQ_APU_TO_CPU 0x00000001
32#define IRQ_CPU_TO_APU_ACK 0x00000001
33#define IRQ_HPU_TO_CPU 0x00000002
34#define IRQ_CPU_TO_HPU_ACK 0x00000002
35#define IRQ_PPU_TO_CPU 0x00000004
36#define IRQ_CPU_TO_PPU_ACK 0x00000004
37#define IRQ_EPU_TO_CPU 0x00000008
38#define IRQ_CPU_TO_EPU_ACK 0x00000008
39
40#define IRQ_CPU_TO_APU 0x00000010
41#define IRQ_APU_TO_CPU_ACK 0x00000010
42#define IRQ_HPU_TO_APU 0x00000020
43#define IRQ_APU_TO_HPU_ACK 0x00000020
44#define IRQ_PPU_TO_APU 0x00000040
45#define IRQ_APU_TO_PPU_ACK 0x00000040
46#define IRQ_EPU_TO_APU 0x00000080
47#define IRQ_APU_TO_EPU_ACK 0x00000080
48
49#define IRQ_CPU_TO_HPU 0x00000100
50#define IRQ_HPU_TO_CPU_ACK 0x00000100
51#define IRQ_APU_TO_HPU 0x00000200
52#define IRQ_HPU_TO_APU_ACK 0x00000200
53#define IRQ_PPU_TO_HPU 0x00000400
54#define IRQ_HPU_TO_PPU_ACK 0x00000400
55#define IRQ_EPU_TO_HPU 0x00000800
56#define IRQ_HPU_TO_EPU_ACK 0x00000800
57
58#define IRQ_CPU_TO_PPU 0x00001000
59#define IRQ_PPU_TO_CPU_ACK 0x00001000
60#define IRQ_APU_TO_PPU 0x00002000
61#define IRQ_PPU_TO_APU_ACK 0x00002000
62#define IRQ_HPU_TO_PPU 0x00004000
63#define IRQ_PPU_TO_HPU_ACK 0x00004000
64#define IRQ_EPU_TO_PPU 0x00008000
65#define IRQ_PPU_TO_EPU_ACK 0x00008000
66
67#define IRQ_CPU_TO_EPU 0x00010000
68#define IRQ_EPU_TO_CPU_ACK 0x00010000
69#define IRQ_APU_TO_EPU 0x00020000
70#define IRQ_EPU_TO_APU_ACK 0x00020000
71#define IRQ_HPU_TO_EPU 0x00040000
72#define IRQ_EPU_TO_HPU_ACK 0x00040000
73#define IRQ_PPU_TO_EPU 0x00080000
74#define IRQ_EPU_TO_PPU_ACK 0x00080000
75
76#define SCB_OFFSET 0xDC0000
77
78/* If Firmware uses fixed memory map, it shall not allocate the area
79 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80#define SCB_RESERVED_SIZE 0x10000
81
82
83/* This structure is used by EPU to provide memory descriptors in its memory */
Andy Wallsf0076e62009-11-04 22:33:33 -030084struct cx18_mdl_ent {
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030085 u32 paddr; /* Physical address of a buffer segment */
86 u32 length; /* Length of the buffer segment */
87};
88
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030089struct cx18_scb {
90 /* These fields form the System Control Block which is used at boot time
91 for localizing the IPC data as well as the code positions for all
92 processors. The offsets are from the start of this struct. */
93
94 /* Offset where to find the Inter-Processor Communication data */
95 u32 ipc_offset;
96 u32 reserved01[7];
97 /* Offset where to find the start of the CPU code */
98 u32 cpu_code_offset;
99 u32 reserved02[3];
100 /* Offset where to find the start of the APU code */
101 u32 apu_code_offset;
102 u32 reserved03[3];
103 /* Offset where to find the start of the HPU code */
104 u32 hpu_code_offset;
105 u32 reserved04[3];
106 /* Offset where to find the start of the PPU code */
107 u32 ppu_code_offset;
108 u32 reserved05[3];
109
110 /* These fields form Inter-Processor Communication data which is used
111 by all processors to locate the information needed for communicating
112 with other processors */
113
114 /* Fields for CPU: */
115
116 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
117 u32 cpu_state;
118 u32 reserved1[7];
119 /* Offset to the mailbox used for sending commands from APU to CPU */
120 u32 apu2cpu_mb_offset;
121 /* Value to write to register SW1 register set (0xC7003100) after the
122 command is ready */
123 u32 apu2cpu_irq;
124 /* Value to write to register SW2 register set (0xC7003140) after the
125 command is cleared */
Andy Walls465f8a82008-11-04 22:02:23 -0300126 u32 cpu2apu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300127 u32 reserved2[13];
128
129 u32 hpu2cpu_mb_offset;
130 u32 hpu2cpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300131 u32 cpu2hpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300132 u32 reserved3[13];
133
134 u32 ppu2cpu_mb_offset;
135 u32 ppu2cpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300136 u32 cpu2ppu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300137 u32 reserved4[13];
138
139 u32 epu2cpu_mb_offset;
140 u32 epu2cpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300141 u32 cpu2epu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300142 u32 reserved5[13];
143 u32 reserved6[8];
144
145 /* Fields for APU: */
146
147 u32 apu_state;
148 u32 reserved11[7];
149 u32 cpu2apu_mb_offset;
150 u32 cpu2apu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300151 u32 apu2cpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300152 u32 reserved12[13];
153
154 u32 hpu2apu_mb_offset;
155 u32 hpu2apu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300156 u32 apu2hpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300157 u32 reserved13[13];
158
159 u32 ppu2apu_mb_offset;
160 u32 ppu2apu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300161 u32 apu2ppu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300162 u32 reserved14[13];
163
164 u32 epu2apu_mb_offset;
165 u32 epu2apu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300166 u32 apu2epu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300167 u32 reserved15[13];
168 u32 reserved16[8];
169
170 /* Fields for HPU: */
171
172 u32 hpu_state;
173 u32 reserved21[7];
174 u32 cpu2hpu_mb_offset;
175 u32 cpu2hpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300176 u32 hpu2cpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300177 u32 reserved22[13];
178
179 u32 apu2hpu_mb_offset;
180 u32 apu2hpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300181 u32 hpu2apu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300182 u32 reserved23[13];
183
184 u32 ppu2hpu_mb_offset;
185 u32 ppu2hpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300186 u32 hpu2ppu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300187 u32 reserved24[13];
188
189 u32 epu2hpu_mb_offset;
190 u32 epu2hpu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300191 u32 hpu2epu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300192 u32 reserved25[13];
193 u32 reserved26[8];
194
195 /* Fields for PPU: */
196
197 u32 ppu_state;
198 u32 reserved31[7];
199 u32 cpu2ppu_mb_offset;
200 u32 cpu2ppu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300201 u32 ppu2cpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300202 u32 reserved32[13];
203
204 u32 apu2ppu_mb_offset;
205 u32 apu2ppu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300206 u32 ppu2apu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300207 u32 reserved33[13];
208
209 u32 hpu2ppu_mb_offset;
210 u32 hpu2ppu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300211 u32 ppu2hpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300212 u32 reserved34[13];
213
214 u32 epu2ppu_mb_offset;
215 u32 epu2ppu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300216 u32 ppu2epu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300217 u32 reserved35[13];
218 u32 reserved36[8];
219
220 /* Fields for EPU: */
221
222 u32 epu_state;
223 u32 reserved41[7];
224 u32 cpu2epu_mb_offset;
225 u32 cpu2epu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300226 u32 epu2cpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300227 u32 reserved42[13];
228
229 u32 apu2epu_mb_offset;
230 u32 apu2epu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300231 u32 epu2apu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300232 u32 reserved43[13];
233
234 u32 hpu2epu_mb_offset;
235 u32 hpu2epu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300236 u32 epu2hpu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300237 u32 reserved44[13];
238
239 u32 ppu2epu_mb_offset;
240 u32 ppu2epu_irq;
Andy Walls465f8a82008-11-04 22:02:23 -0300241 u32 epu2ppu_irq_ack;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300242 u32 reserved45[13];
243 u32 reserved46[8];
244
245 u32 semaphores[8]; /* Semaphores */
246
247 u32 reserved50[32]; /* Reserved for future use */
248
249 struct cx18_mailbox apu2cpu_mb;
250 struct cx18_mailbox hpu2cpu_mb;
251 struct cx18_mailbox ppu2cpu_mb;
252 struct cx18_mailbox epu2cpu_mb;
253
254 struct cx18_mailbox cpu2apu_mb;
255 struct cx18_mailbox hpu2apu_mb;
256 struct cx18_mailbox ppu2apu_mb;
257 struct cx18_mailbox epu2apu_mb;
258
259 struct cx18_mailbox cpu2hpu_mb;
260 struct cx18_mailbox apu2hpu_mb;
261 struct cx18_mailbox ppu2hpu_mb;
262 struct cx18_mailbox epu2hpu_mb;
263
264 struct cx18_mailbox cpu2ppu_mb;
265 struct cx18_mailbox apu2ppu_mb;
266 struct cx18_mailbox hpu2ppu_mb;
267 struct cx18_mailbox epu2ppu_mb;
268
269 struct cx18_mailbox cpu2epu_mb;
270 struct cx18_mailbox apu2epu_mb;
271 struct cx18_mailbox hpu2epu_mb;
272 struct cx18_mailbox ppu2epu_mb;
273
Andy Wallsee2d64f2008-11-16 01:38:19 -0300274 struct cx18_mdl_ack cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS];
Andy Wallsf0076e62009-11-04 22:33:33 -0300275 struct cx18_mdl_ent cpu_mdl[1];
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300276};
277
278void cx18_init_scb(struct cx18 *cx);
279
280#endif