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Will Newtonf95f3852011-01-02 01:11:59 -05001/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Robert P. J. Day100e9182011-05-27 16:04:03 -040014#ifndef LINUX_MMC_DW_MMC_H
15#define LINUX_MMC_DW_MMC_H
Will Newtonf95f3852011-01-02 01:11:59 -050016
17#define MAX_MCI_SLOTS 2
18
19enum dw_mci_state {
20 STATE_IDLE = 0,
21 STATE_SENDING_CMD,
22 STATE_SENDING_DATA,
23 STATE_DATA_BUSY,
24 STATE_SENDING_STOP,
25 STATE_DATA_ERROR,
26};
27
28enum {
29 EVENT_CMD_COMPLETE = 0,
30 EVENT_XFER_COMPLETE,
31 EVENT_DATA_COMPLETE,
32 EVENT_DATA_ERROR,
33 EVENT_XFER_ERROR
34};
35
36struct mmc_data;
37
38/**
39 * struct dw_mci - MMC controller state shared between all slots
40 * @lock: Spinlock protecting the queue and associated data.
41 * @regs: Pointer to MMIO registers.
42 * @sg: Scatterlist entry currently being processed by PIO code, if any.
43 * @pio_offset: Offset into the current scatterlist entry.
44 * @cur_slot: The slot which is currently using the controller.
45 * @mrq: The request currently being processed on @cur_slot,
46 * or NULL if the controller is idle.
47 * @cmd: The command currently being sent to the card, or NULL.
48 * @data: The data currently being transferred, or NULL if no data
49 * transfer is in progress.
50 * @use_dma: Whether DMA channel is initialized or not.
51 * @sg_dma: Bus address of DMA buffer.
52 * @sg_cpu: Virtual address of DMA buffer.
53 * @dma_ops: Pointer to platform-specific DMA callbacks.
54 * @cmd_status: Snapshot of SR taken upon completion of the current
55 * command. Only valid when EVENT_CMD_COMPLETE is pending.
56 * @data_status: Snapshot of SR taken upon completion of the current
57 * data transfer. Only valid when EVENT_DATA_COMPLETE or
58 * EVENT_DATA_ERROR is pending.
59 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
60 * to be sent.
61 * @dir_status: Direction of current transfer.
62 * @tasklet: Tasklet running the request state machine.
63 * @card_tasklet: Tasklet handling card detect.
64 * @pending_events: Bitmask of events flagged by the interrupt handler
65 * to be processed by the tasklet.
66 * @completed_events: Bitmask of events which the state machine has
67 * processed.
68 * @state: Tasklet state.
69 * @queue: List of slots waiting for access to the controller.
70 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
71 * rate and timeout calculations.
72 * @current_speed: Configured rate of the controller.
73 * @num_slots: Number of slots available.
74 * @pdev: Platform device associated with the MMC controller.
75 * @pdata: Platform data associated with the MMC controller.
76 * @slot: Slots sharing this MMC controller.
James Hoganb86d8252011-06-24 13:57:18 +010077 * @fifo_depth: depth of FIFO.
Will Newtonf95f3852011-01-02 01:11:59 -050078 * @data_shift: log2 of FIFO item size.
James Hogan34b664a2011-06-24 13:57:56 +010079 * @part_buf_start: Start index in part_buf.
80 * @part_buf_count: Bytes of partial data in part_buf.
81 * @part_buf: Simple buffer for partial fifo reads/writes.
Will Newtonf95f3852011-01-02 01:11:59 -050082 * @push_data: Pointer to FIFO push function.
83 * @pull_data: Pointer to FIFO pull function.
84 * @quirks: Set of quirks that apply to specific versions of the IP.
85 *
86 * Locking
87 * =======
88 *
89 * @lock is a softirq-safe spinlock protecting @queue as well as
90 * @cur_slot, @mrq and @state. These must always be updated
91 * at the same time while holding @lock.
92 *
93 * The @mrq field of struct dw_mci_slot is also protected by @lock,
94 * and must always be written at the same time as the slot is added to
95 * @queue.
96 *
97 * @pending_events and @completed_events are accessed using atomic bit
98 * operations, so they don't need any locking.
99 *
100 * None of the fields touched by the interrupt handler need any
101 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
102 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
103 * interrupts must be disabled and @data_status updated with a
104 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300105 * CMDRDY interrupt must be disabled and @cmd_status updated with a
Will Newtonf95f3852011-01-02 01:11:59 -0500106 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
107 * bytes_xfered field of @data must be written. This is ensured by
108 * using barriers.
109 */
110struct dw_mci {
111 spinlock_t lock;
112 void __iomem *regs;
113
114 struct scatterlist *sg;
115 unsigned int pio_offset;
116
117 struct dw_mci_slot *cur_slot;
118 struct mmc_request *mrq;
119 struct mmc_command *cmd;
120 struct mmc_data *data;
121
122 /* DMA interface members*/
123 int use_dma;
124
125 dma_addr_t sg_dma;
126 void *sg_cpu;
127 struct dw_mci_dma_ops *dma_ops;
128#ifdef CONFIG_MMC_DW_IDMAC
129 unsigned int ring_size;
130#else
131 struct dw_mci_dma_data *dma_data;
132#endif
133 u32 cmd_status;
134 u32 data_status;
135 u32 stop_cmdr;
136 u32 dir_status;
137 struct tasklet_struct tasklet;
James Hogan1791b13e2011-06-24 13:55:55 +0100138 struct work_struct card_work;
Will Newtonf95f3852011-01-02 01:11:59 -0500139 unsigned long pending_events;
140 unsigned long completed_events;
141 enum dw_mci_state state;
142 struct list_head queue;
143
144 u32 bus_hz;
145 u32 current_speed;
146 u32 num_slots;
Jaehoon Chunge61cf112011-03-17 20:32:33 +0900147 u32 fifoth_val;
Will Newtonf95f3852011-01-02 01:11:59 -0500148 struct platform_device *pdev;
149 struct dw_mci_board *pdata;
150 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
151
152 /* FIFO push and pull */
James Hoganb86d8252011-06-24 13:57:18 +0100153 int fifo_depth;
Will Newtonf95f3852011-01-02 01:11:59 -0500154 int data_shift;
James Hogan34b664a2011-06-24 13:57:56 +0100155 u8 part_buf_start;
156 u8 part_buf_count;
157 union {
158 u16 part_buf16;
159 u32 part_buf32;
160 u64 part_buf;
161 };
Will Newtonf95f3852011-01-02 01:11:59 -0500162 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
163 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
164
165 /* Workaround flags */
166 u32 quirks;
Jaehoon Chungc07946a2011-02-25 11:08:14 +0900167
168 struct regulator *vmmc; /* Power regulator */
Will Newtonf95f3852011-01-02 01:11:59 -0500169};
170
171/* DMA ops for Internal/External DMAC interface */
172struct dw_mci_dma_ops {
173 /* DMA Ops */
174 int (*init)(struct dw_mci *host);
175 void (*start)(struct dw_mci *host, unsigned int sg_len);
176 void (*complete)(struct dw_mci *host);
177 void (*stop)(struct dw_mci *host);
178 void (*cleanup)(struct dw_mci *host);
179 void (*exit)(struct dw_mci *host);
180};
181
182/* IP Quirks/flags. */
Will Newtonf95f3852011-01-02 01:11:59 -0500183/* DTO fix for command transmission with IDMAC configured */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900184#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
Will Newtonf95f3852011-01-02 01:11:59 -0500185/* delay needed between retries on some 2.11a implementations */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900186#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300187/* High Speed Capable - Supports HS cards (up to 50MHz) */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900188#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
189/* Unreliable card detection */
190#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
Will Newtonf95f3852011-01-02 01:11:59 -0500191
192
193struct dma_pdata;
194
195struct block_settings {
196 unsigned short max_segs; /* see blk_queue_max_segments */
197 unsigned int max_blk_size; /* maximum size of one mmc block */
198 unsigned int max_blk_count; /* maximum number of blocks in one req*/
199 unsigned int max_req_size; /* maximum number of bytes in one req*/
200 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
201};
202
203/* Board platform data */
204struct dw_mci_board {
205 u32 num_slots;
206
207 u32 quirks; /* Workaround / Quirk flags */
208 unsigned int bus_hz; /* Bus speed */
209
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900210 unsigned int caps; /* Capabilities */
James Hoganb86d8252011-06-24 13:57:18 +0100211 /*
212 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
213 * but note that this may not be reliable after a bootloader has used
214 * it.
215 */
216 unsigned int fifo_depth;
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900217
Will Newtonf95f3852011-01-02 01:11:59 -0500218 /* delay in mS before detecting cards after interrupt */
219 u32 detect_delay_ms;
220
221 int (*init)(u32 slot_id, irq_handler_t , void *);
222 int (*get_ro)(u32 slot_id);
223 int (*get_cd)(u32 slot_id);
224 int (*get_ocr)(u32 slot_id);
225 int (*get_bus_wd)(u32 slot_id);
226 /*
227 * Enable power to selected slot and set voltage to desired level.
228 * Voltage levels are specified using MMC_VDD_xxx defines defined
229 * in linux/mmc/host.h file.
230 */
231 void (*setpower)(u32 slot_id, u32 volt);
232 void (*exit)(u32 slot_id);
233 void (*select_slot)(u32 slot_id);
234
235 struct dw_mci_dma_ops *dma_ops;
236 struct dma_pdata *data;
237 struct block_settings *blk_settings;
238};
239
Robert P. J. Day100e9182011-05-27 16:04:03 -0400240#endif /* LINUX_MMC_DW_MMC_H */