| Ralf Baechle | 35189fa | 2006-06-18 16:39:46 +0100 | [diff] [blame^] | 1 | #ifndef __EXCITE_H__ |
| 2 | #define __EXCITE_H__ |
| 3 | |
| 4 | #include <linux/config.h> |
| 5 | #include <linux/init.h> |
| 6 | #include <asm/addrspace.h> |
| 7 | #include <asm/types.h> |
| 8 | |
| 9 | #define EXCITE_CPU_EXT_CLOCK 100000000 |
| 10 | |
| 11 | #if !defined(__ASSEMBLER__) |
| 12 | void __init excite_kgdb_init(void); |
| 13 | void excite_procfs_init(void); |
| 14 | extern unsigned long memsize; |
| 15 | extern char modetty[]; |
| 16 | extern u32 unit_id; |
| 17 | #endif |
| 18 | |
| 19 | /* Base name for XICAP devices */ |
| 20 | #define XICAP_NAME "xicap_gpi" |
| 21 | |
| 22 | /* OCD register offsets */ |
| 23 | #define LKB0 0x0038 |
| 24 | #define LKB5 0x0128 |
| 25 | #define LKM5 0x012C |
| 26 | #define LKB7 0x0138 |
| 27 | #define LKM7 0x013c |
| 28 | #define LKB8 0x0140 |
| 29 | #define LKM8 0x0144 |
| 30 | #define LKB9 0x0148 |
| 31 | #define LKM9 0x014c |
| 32 | #define LKB10 0x0150 |
| 33 | #define LKM10 0x0154 |
| 34 | #define LKB11 0x0158 |
| 35 | #define LKM11 0x015c |
| 36 | #define LKB12 0x0160 |
| 37 | #define LKM12 0x0164 |
| 38 | #define LKB13 0x0168 |
| 39 | #define LKM13 0x016c |
| 40 | #define LDP0 0x0200 |
| 41 | #define LDP1 0x0210 |
| 42 | #define LDP2 0x0220 |
| 43 | #define LDP3 0x0230 |
| 44 | #define INTPIN0 0x0A40 |
| 45 | #define INTPIN1 0x0A44 |
| 46 | #define INTPIN2 0x0A48 |
| 47 | #define INTPIN3 0x0A4C |
| 48 | #define INTPIN4 0x0A50 |
| 49 | #define INTPIN5 0x0A54 |
| 50 | #define INTPIN6 0x0A58 |
| 51 | #define INTPIN7 0x0A5C |
| 52 | |
| 53 | |
| 54 | |
| 55 | |
| 56 | /* TITAN register offsets */ |
| 57 | #define CPRR 0x0004 |
| 58 | #define CPDSR 0x0008 |
| 59 | #define CPTC0R 0x000c |
| 60 | #define CPTC1R 0x0010 |
| 61 | #define CPCFG0 0x0020 |
| 62 | #define CPCFG1 0x0024 |
| 63 | #define CPDST0A 0x0028 |
| 64 | #define CPDST0B 0x002c |
| 65 | #define CPDST1A 0x0030 |
| 66 | #define CPDST1B 0x0034 |
| 67 | #define CPXDSTA 0x0038 |
| 68 | #define CPXDSTB 0x003c |
| 69 | #define CPXCISRA 0x0048 |
| 70 | #define CPXCISRB 0x004c |
| 71 | #define CPGIG0ER 0x0050 |
| 72 | #define CPGIG1ER 0x0054 |
| 73 | #define CPGRWL 0x0068 |
| 74 | #define CPURSLMT 0x00f8 |
| 75 | #define UACFG 0x0200 |
| 76 | #define UAINTS 0x0204 |
| 77 | #define SDRXFCIE 0x4828 |
| 78 | #define SDTXFCIE 0x4928 |
| 79 | #define INTP0Status0 0x1B00 |
| 80 | #define INTP0Mask0 0x1B04 |
| 81 | #define INTP0Set0 0x1B08 |
| 82 | #define INTP0Clear0 0x1B0C |
| 83 | #define GXCFG 0x5000 |
| 84 | #define GXDMADRPFX 0x5018 |
| 85 | #define GXDMA_DESCADR 0x501c |
| 86 | #define GXCH0TDESSTRT 0x5054 |
| 87 | |
| 88 | /* IRQ definitions */ |
| 89 | #define NMICONFIG 0xac0 |
| 90 | #define TITAN_MSGINT 0xc4 |
| 91 | #define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) |
| 92 | #define FPGA0_MSGINT 0x5a |
| 93 | #define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) |
| 94 | #define FPGA1_MSGINT 0x7b |
| 95 | #define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) |
| 96 | #define PHY_MSGINT 0x9c |
| 97 | #define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) |
| 98 | |
| 99 | #if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) |
| 100 | /* Pre-release units used interrupt pin #9 */ |
| 101 | #define USB_IRQ 11 |
| 102 | #else |
| 103 | /* Re-designed units use interrupt pin #1 */ |
| 104 | #define USB_MSGINT 0x39 |
| 105 | #define USB_IRQ ((USB_MSGINT / 0x20) + 2) |
| 106 | #endif |
| 107 | #define TIMER_IRQ 12 |
| 108 | |
| 109 | |
| 110 | /* Device address ranges */ |
| 111 | #define EXCITE_OFFS_OCD 0x1fffc000 |
| 112 | #define EXCITE_SIZE_OCD (16 * 1024) |
| 113 | #define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) |
| 114 | #define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) |
| 115 | |
| 116 | #define EXCITE_OFFS_SCRAM 0x1fffa000 |
| 117 | #define EXCITE_SIZE_SCRAM (8 << 10) |
| 118 | #define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) |
| 119 | #define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) |
| 120 | |
| 121 | #define EXCITE_OFFS_PCI_IO 0x1fff8000 |
| 122 | #define EXCITE_SIZE_PCI_IO (8 << 10) |
| 123 | #define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) |
| 124 | #define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) |
| 125 | |
| 126 | #define EXCITE_OFFS_TITAN 0x1fff0000 |
| 127 | #define EXCITE_SIZE_TITAN (32 << 10) |
| 128 | #define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) |
| 129 | #define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) |
| 130 | |
| 131 | #define EXCITE_OFFS_PCI_MEM 0x1ffe0000 |
| 132 | #define EXCITE_SIZE_PCI_MEM (64 << 10) |
| 133 | #define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) |
| 134 | #define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) |
| 135 | |
| 136 | #define EXCITE_OFFS_FPGA 0x1ffdc000 |
| 137 | #define EXCITE_SIZE_FPGA (16 << 10) |
| 138 | #define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) |
| 139 | #define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) |
| 140 | |
| 141 | #define EXCITE_OFFS_NAND 0x1ffd8000 |
| 142 | #define EXCITE_SIZE_NAND (16 << 10) |
| 143 | #define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) |
| 144 | #define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) |
| 145 | |
| 146 | #define EXCITE_OFFS_BOOTROM 0x1f000000 |
| 147 | #define EXCITE_SIZE_BOOTROM (8 << 20) |
| 148 | #define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) |
| 149 | #define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) |
| 150 | |
| 151 | /* FPGA address offsets */ |
| 152 | #define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ |
| 153 | #define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ |
| 154 | |
| 155 | #endif /* __EXCITE_H__ */ |