blob: 0f4d27aef44dfb0972d0d6bd890b899972179831 [file] [log] [blame]
Tony Lindgrenb824efa2006-04-02 17:46:20 +01001/*
Paul Walmsley96609ef2009-01-28 12:27:34 -07002 * linux/arch/arm/mach-omap2/sdrc2xxx.c
Tony Lindgrenb824efa2006-04-02 17:46:20 +01003 *
Paul Walmsley96609ef2009-01-28 12:27:34 -07004 * SDRAM timing related functions for OMAP2xxx
Tony Lindgrenb824efa2006-04-02 17:46:20 +01005 *
Paul Walmsleyf2ab9972009-01-28 12:27:37 -07006 * Copyright (C) 2005, 2008 Texas Instruments Inc.
7 * Copyright (C) 2005, 2008 Nokia Corporation
Tony Lindgrenb824efa2006-04-02 17:46:20 +01008 *
Tony Lindgrenb824efa2006-04-02 17:46:20 +01009 * Tony Lindgren <tony@atomide.com>
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070010 * Paul Walmsley
11 * Richard Woodruff <r-woodruff2@ti.com>
Tony Lindgrenb824efa2006-04-02 17:46:20 +010012 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
Tony Lindgrenb824efa2006-04-02 17:46:20 +010018#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Tony Lindgrenb824efa2006-04-02 17:46:20 +010026
Tony Lindgrence491cf2009-10-20 09:40:47 -070027#include <plat/common.h>
28#include <plat/clock.h>
29#include <plat/sram.h>
Tony Lindgrenb824efa2006-04-02 17:46:20 +010030
Paul Walmsley44595982008-03-18 10:04:51 +020031#include "prm.h"
Russell Kingc0bf3132009-02-19 13:29:22 +000032#include "clock.h"
Tony Lindgrence491cf2009-10-20 09:40:47 -070033#include <plat/sdrc.h>
Paul Walmsley44595982008-03-18 10:04:51 +020034#include "sdrc.h"
35
Paul Walmsleyf8de9b22009-01-28 12:27:31 -070036/* Memory timing, DLL mode flags */
37#define M_DDR 1
38#define M_LOCK_CTRL (1 << 2)
39#define M_UNLOCK 0
40#define M_LOCK 1
41
42
Tony Lindgrenb824efa2006-04-02 17:46:20 +010043static struct memory_timings mem_timings;
Paul Walmsley44595982008-03-18 10:04:51 +020044static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
Tony Lindgrenb824efa2006-04-02 17:46:20 +010045
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070046static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010047{
48 return mem_timings.slow_dll_ctrl;
49}
50
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070051static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010052{
53 return mem_timings.fast_dll_ctrl;
54}
55
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070056static u32 omap2xxx_sdrc_get_type(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010057{
58 return mem_timings.m_type;
59}
60
Paul Walmsley6b8858a2008-03-18 10:35:15 +020061/*
62 * Check the DLL lock state, and return tue if running in unlock mode.
63 * This is needed to compensate for the shifted DLL value in unlock mode.
64 */
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070065u32 omap2xxx_sdrc_dll_is_unlocked(void)
Paul Walmsley6b8858a2008-03-18 10:35:15 +020066{
67 /* dlla and dllb are a set */
68 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
69
70 if ((dll_state & (1 << 2)) == (1 << 2))
71 return 1;
72 else
73 return 0;
74}
75
76/*
77 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
78 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
79 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070080 *
81 * Used by the clock framework during CORE DPLL changes
Paul Walmsley6b8858a2008-03-18 10:35:15 +020082 */
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070083u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
Paul Walmsley6b8858a2008-03-18 10:35:15 +020084{
85 u32 dll_ctrl, m_type;
86 u32 prev = curr_perf_level;
87 unsigned long flags;
88
89 if ((curr_perf_level == level) && !force)
90 return prev;
91
Paul Walmsley96609ef2009-01-28 12:27:34 -070092 if (level == CORE_CLK_SRC_DPLL)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070093 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
Paul Walmsley96609ef2009-01-28 12:27:34 -070094 else if (level == CORE_CLK_SRC_DPLL_X2)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070095 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
Paul Walmsley96609ef2009-01-28 12:27:34 -070096 else
Paul Walmsley6b8858a2008-03-18 10:35:15 +020097 return prev;
Paul Walmsley6b8858a2008-03-18 10:35:15 +020098
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070099 m_type = omap2xxx_sdrc_get_type();
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200100
101 local_irq_save(flags);
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700102 if (cpu_is_omap2420())
103 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
104 else
105 __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200106 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
107 curr_perf_level = level;
108 local_irq_restore(flags);
109
110 return prev;
111}
112
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700113/* Used by the clock framework during CORE DPLL changes */
114void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100115{
116 unsigned long dll_cnt;
117 u32 fast_dll = 0;
118
Paul Walmsley96609ef2009-01-28 12:27:34 -0700119 /* DDR = 1, SDR = 0 */
120 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100121
122 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
123 * In the case of 2422, its ok to use CS1 instead of CS0.
124 */
125 if (cpu_is_omap2422())
126 mem_timings.base_cs = 1;
127 else
128 mem_timings.base_cs = 0;
129
130 if (mem_timings.m_type != M_DDR)
131 return;
132
133 /* With DDR we need to determine the low frequency DLL value */
134 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
135 mem_timings.dll_mode = M_UNLOCK;
136 else
137 mem_timings.dll_mode = M_LOCK;
138
139 if (mem_timings.base_cs == 0) {
Paul Walmsley44595982008-03-18 10:04:51 +0200140 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
141 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100142 } else {
Paul Walmsley44595982008-03-18 10:04:51 +0200143 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
144 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100145 }
146 if (force_lock_to_unlock_mode) {
147 fast_dll &= ~0xff00;
148 fast_dll |= dll_cnt; /* Current lock mode */
149 }
150 /* set fast timings with DLL filter disabled */
151 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
152
153 /* No disruptions, DDR will be offline & C-ABI not followed */
154 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
155 mem_timings.fast_dll_ctrl,
156 mem_timings.base_cs,
157 force_lock_to_unlock_mode);
158 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
159
160 /* Turn status into unlock ctrl */
161 mem_timings.slow_dll_ctrl |=
162 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
163
164 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
165 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
166}