Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SH_IRQ_H |
| 2 | #define __ASM_SH_IRQ_H |
| 3 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | #include <asm/machvec.h> |
| 5 | #include <asm/ptrace.h> /* for pt_regs */ |
| 6 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | /* NR_IRQS is made from three components: |
| 8 | * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules |
| 9 | * 2. PINT_NR_IRQS - number of PINT interrupts |
| 10 | * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules |
| 11 | */ |
| 12 | |
| 13 | /* 1. ONCHIP_NR_IRQS */ |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 14 | #if defined(CONFIG_CPU_SUBTYPE_SH7604) |
| 15 | # define ONCHIP_NR_IRQS 24 // Actually 21 |
| 16 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) |
| 17 | # define ONCHIP_NR_IRQS 64 |
| 18 | # define PINT_NR_IRQS 16 |
| 19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7708) |
| 20 | # define ONCHIP_NR_IRQS 32 |
| 21 | #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 22 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 23 | defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 24 | # define ONCHIP_NR_IRQS 64 // Actually 61 |
| 25 | # define PINT_NR_IRQS 16 |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 26 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
| 27 | # define ONCHIP_NR_IRQS 104 |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) |
| 29 | # define ONCHIP_NR_IRQS 48 // Actually 44 |
| 30 | #elif defined(CONFIG_CPU_SUBTYPE_SH7751) |
| 31 | # define ONCHIP_NR_IRQS 72 |
| 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| 33 | # define ONCHIP_NR_IRQS 112 /* XXX */ |
| 34 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 35 | # define ONCHIP_NR_IRQS 72 |
| 36 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | # define ONCHIP_NR_IRQS 144 |
Paul Mundt | 8d27e08 | 2006-02-01 03:06:04 -0800 | [diff] [blame] | 38 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 39 | defined(CONFIG_CPU_SUBTYPE_SH73180) || \ |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 40 | defined(CONFIG_CPU_SUBTYPE_SH7343) || \ |
| 41 | defined(CONFIG_CPU_SUBTYPE_SH7722) |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 42 | # define ONCHIP_NR_IRQS 109 |
Paul Mundt | 8d27e08 | 2006-02-01 03:06:04 -0800 | [diff] [blame] | 43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 44 | # define ONCHIP_NR_IRQS 111 |
Yoshinori Sato | b229632 | 2006-11-05 16:18:08 +0900 | [diff] [blame] | 45 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
| 46 | # define ONCHIP_NR_IRQS 256 |
| 47 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 48 | # define ONCHIP_NR_IRQS 128 |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 49 | #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ |
| 50 | # define ONCHIP_NR_IRQS 144 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | #endif |
| 52 | |
| 53 | /* 2. PINT_NR_IRQS */ |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 54 | #ifdef CONFIG_SH_UNKNOWN |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | # define PINT_NR_IRQS 16 |
| 56 | #else |
| 57 | # ifndef PINT_NR_IRQS |
| 58 | # define PINT_NR_IRQS 0 |
| 59 | # endif |
| 60 | #endif |
| 61 | |
| 62 | #if PINT_NR_IRQS > 0 |
| 63 | # define PINT_IRQ_BASE ONCHIP_NR_IRQS |
| 64 | #endif |
| 65 | |
| 66 | /* 3. OFFCHIP_NR_IRQS */ |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 67 | #if defined(CONFIG_HD64461) |
| 68 | # define OFFCHIP_NR_IRQS 18 |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 69 | #elif defined(CONFIG_HD64465) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | # define OFFCHIP_NR_IRQS 16 |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 71 | #elif defined (CONFIG_SH_DREAMCAST) |
| 72 | # define OFFCHIP_NR_IRQS 96 |
| 73 | #elif defined (CONFIG_SH_TITAN) |
| 74 | # define OFFCHIP_NR_IRQS 4 |
Paul Mundt | 8d27e08 | 2006-02-01 03:06:04 -0800 | [diff] [blame] | 75 | #elif defined(CONFIG_SH_R7780RP) |
| 76 | # define OFFCHIP_NR_IRQS 16 |
Paul Mundt | bc8fb5d | 2006-09-27 18:09:34 +0900 | [diff] [blame] | 77 | #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE) |
| 78 | # define OFFCHIP_NR_IRQS 12 |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 79 | #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE) |
| 80 | # define OFFCHIP_NR_IRQS 14 |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 81 | #elif defined(CONFIG_SH_UNKNOWN) |
| 82 | # define OFFCHIP_NR_IRQS 16 /* Must also be last */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | #else |
Paul Mundt | bf3a00f | 2006-01-16 22:14:14 -0800 | [diff] [blame] | 84 | # define OFFCHIP_NR_IRQS 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | #endif |
| 86 | |
| 87 | #if OFFCHIP_NR_IRQS > 0 |
| 88 | # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS) |
| 89 | #endif |
| 90 | |
| 91 | /* NR_IRQS. 1+2+3 */ |
| 92 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) |
| 93 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | /* |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 95 | * Convert back and forth between INTEVT and IRQ values. |
| 96 | */ |
Paul Mundt | 3afb209 | 2007-03-14 13:03:35 +0900 | [diff] [blame^] | 97 | #ifdef CONFIG_CPU_HAS_INTEVT |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 98 | #define evt2irq(evt) (((evt) >> 5) - 16) |
| 99 | #define irq2evt(irq) (((irq) + 16) << 5) |
Paul Mundt | 3afb209 | 2007-03-14 13:03:35 +0900 | [diff] [blame^] | 100 | #else |
| 101 | #define evt2irq(evt) (evt) |
| 102 | #define irq2evt(irq) (irq) |
| 103 | #endif |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 104 | |
| 105 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | * Simple Mask Register Support |
| 107 | */ |
| 108 | extern void make_maskreg_irq(unsigned int irq); |
| 109 | extern unsigned short *irq_mask_register; |
| 110 | |
| 111 | /* |
Paul Mundt | 0f08f33 | 2006-09-27 17:03:56 +0900 | [diff] [blame] | 112 | * PINT IRQs |
| 113 | */ |
| 114 | void init_IRQ_pint(void); |
| 115 | |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 116 | /* |
| 117 | * The shift value is now the number of bits to shift, not the number of |
| 118 | * bits/4. This is to make it easier to read the value directly from the |
| 119 | * datasheets. The IPR address, addr, will be set from ipr_idx via the |
| 120 | * map_ipridx_to_addr function. |
| 121 | */ |
Jamie Lenehan | bd71ab8 | 2006-10-31 12:35:02 +0900 | [diff] [blame] | 122 | struct ipr_data { |
| 123 | unsigned int irq; |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 124 | int ipr_idx; /* Index for the IPR registered */ |
| 125 | int shift; /* Number of bits to shift the data */ |
Jamie Lenehan | bd71ab8 | 2006-10-31 12:35:02 +0900 | [diff] [blame] | 126 | int priority; /* The priority */ |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 127 | unsigned int addr; /* Address of Interrupt Priority Register */ |
Jamie Lenehan | bd71ab8 | 2006-10-31 12:35:02 +0900 | [diff] [blame] | 128 | }; |
| 129 | |
Paul Mundt | 0f08f33 | 2006-09-27 17:03:56 +0900 | [diff] [blame] | 130 | /* |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 131 | * Given an IPR IDX, map the value to an IPR register address. |
| 132 | */ |
| 133 | unsigned int map_ipridx_to_addr(int idx); |
| 134 | |
| 135 | /* |
| 136 | * Enable individual interrupt mode for external IPR IRQs. |
| 137 | */ |
| 138 | void ipr_irq_enable_irlm(void); |
| 139 | |
| 140 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | * Function for "on chip support modules". |
| 142 | */ |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 143 | void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); |
| 144 | void make_imask_irq(unsigned int irq); |
| 145 | void init_IRQ_ipr(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | |
Paul Mundt | 525ccc4 | 2006-10-06 17:35:48 +0900 | [diff] [blame] | 147 | struct intc2_data { |
| 148 | unsigned short irq; |
| 149 | unsigned char ipr_offset, ipr_shift; |
| 150 | unsigned char msk_offset, msk_shift; |
| 151 | unsigned char priority; |
| 152 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | |
Paul Mundt | 66a7405 | 2006-10-20 15:30:55 +0900 | [diff] [blame] | 154 | void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs); |
Paul Mundt | 525ccc4 | 2006-10-06 17:35:48 +0900 | [diff] [blame] | 155 | void init_IRQ_intc2(void); |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 156 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | static inline int generic_irq_demux(int irq) |
| 158 | { |
| 159 | return irq; |
| 160 | } |
| 161 | |
| 162 | #define irq_canonicalize(irq) (irq) |
Paul Mundt | 9a7ef6d | 2006-11-20 13:55:34 +0900 | [diff] [blame] | 163 | #define irq_demux(irq) sh_mv.mv_irq_demux(irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | |
Paul Mundt | a6a31139 | 2006-09-27 18:22:14 +0900 | [diff] [blame] | 165 | #ifdef CONFIG_4KSTACKS |
| 166 | extern void irq_ctx_init(int cpu); |
| 167 | extern void irq_ctx_exit(int cpu); |
| 168 | # define __ARCH_HAS_DO_SOFTIRQ |
| 169 | #else |
| 170 | # define irq_ctx_init(cpu) do { } while (0) |
| 171 | # define irq_ctx_exit(cpu) do { } while (0) |
| 172 | #endif |
| 173 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | #endif /* __ASM_SH_IRQ_H */ |