blob: 570f22053be89fb56d99b464ecc36a9443e2cc8d [file] [log] [blame]
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -07001/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070034#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
Shawn Guo22a85e42011-07-10 01:16:41 +080037#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_gpio.h>
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070040
41#include <mach/spi.h>
42
43#define DRIVER_NAME "spi_imx"
44
45#define MXC_CSPIRXDATA 0x00
46#define MXC_CSPITXDATA 0x04
47#define MXC_CSPICTRL 0x08
48#define MXC_CSPIINT 0x0c
49#define MXC_RESET 0x1c
50
51/* generic defines to abstract from the different register layouts */
52#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
55struct spi_imx_config {
56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +020059 u8 cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070060};
61
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020062enum spi_imx_devtype {
Shawn Guo04ee5852011-07-10 01:16:39 +080063 IMX1_CSPI,
64 IMX21_CSPI,
65 IMX27_CSPI,
66 IMX31_CSPI,
67 IMX35_CSPI, /* CSPI on all i.mx except above */
68 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020069};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
Uwe Kleine-König1723e662010-09-10 09:19:18 +020078 void (*reset)(struct spi_imx_data *);
Shawn Guo04ee5852011-07-10 01:16:39 +080079 enum spi_imx_devtype devtype;
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020080};
81
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070082struct spi_imx_data {
83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
Uwe Kleine-Königcc4d22a2012-03-29 21:54:18 +020086 void __iomem *base;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070087 int irq;
88 struct clk *clk;
89 unsigned long spi_clk;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070090
91 unsigned int count;
92 void (*tx)(struct spi_imx_data *);
93 void (*rx)(struct spi_imx_data *);
94 void *rx_buf;
95 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */
97
Shawn Guoedd501b2011-07-10 01:16:35 +080098 struct spi_imx_devtype_data *devtype_data;
Shawn Guoc2387cb2011-07-10 01:16:40 +080099 int chipselect[0];
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700100};
101
Shawn Guo04ee5852011-07-10 01:16:39 +0800102static inline int is_imx27_cspi(struct spi_imx_data *d)
103{
104 return d->devtype_data->devtype == IMX27_CSPI;
105}
106
107static inline int is_imx35_cspi(struct spi_imx_data *d)
108{
109 return d->devtype_data->devtype == IMX35_CSPI;
110}
111
112static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
113{
114 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
115}
116
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700117#define MXC_SPI_BUF_RX(type) \
118static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
119{ \
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
121 \
122 if (spi_imx->rx_buf) { \
123 *(type *)spi_imx->rx_buf = val; \
124 spi_imx->rx_buf += sizeof(type); \
125 } \
126}
127
128#define MXC_SPI_BUF_TX(type) \
129static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
130{ \
131 type val = 0; \
132 \
133 if (spi_imx->tx_buf) { \
134 val = *(type *)spi_imx->tx_buf; \
135 spi_imx->tx_buf += sizeof(type); \
136 } \
137 \
138 spi_imx->count -= sizeof(type); \
139 \
140 writel(val, spi_imx->base + MXC_CSPITXDATA); \
141}
142
143MXC_SPI_BUF_RX(u8)
144MXC_SPI_BUF_TX(u8)
145MXC_SPI_BUF_RX(u16)
146MXC_SPI_BUF_TX(u16)
147MXC_SPI_BUF_RX(u32)
148MXC_SPI_BUF_TX(u32)
149
150/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
151 * (which is currently not the case in this driver)
152 */
153static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
154 256, 384, 512, 768, 1024};
155
156/* MX21, MX27 */
157static unsigned int spi_imx_clkdiv_1(unsigned int fin,
Shawn Guo04ee5852011-07-10 01:16:39 +0800158 unsigned int fspi, unsigned int max)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700159{
Shawn Guo04ee5852011-07-10 01:16:39 +0800160 int i;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700161
162 for (i = 2; i < max; i++)
163 if (fspi * mxc_clkdivs[i] >= fin)
164 return i;
165
166 return max;
167}
168
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200169/* MX1, MX31, MX35, MX51 CSPI */
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700170static unsigned int spi_imx_clkdiv_2(unsigned int fin,
171 unsigned int fspi)
172{
173 int i, div = 4;
174
175 for (i = 0; i < 7; i++) {
176 if (fspi * div >= fin)
177 return i;
178 div <<= 1;
179 }
180
181 return 7;
182}
183
Shawn Guo66de7572011-07-10 01:16:37 +0800184#define MX51_ECSPI_CTRL 0x08
185#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
186#define MX51_ECSPI_CTRL_XCH (1 << 2)
187#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
188#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
189#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
190#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
191#define MX51_ECSPI_CTRL_BL_OFFSET 20
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200192
Shawn Guo66de7572011-07-10 01:16:37 +0800193#define MX51_ECSPI_CONFIG 0x0c
194#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
195#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
196#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
197#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200198
Shawn Guo66de7572011-07-10 01:16:37 +0800199#define MX51_ECSPI_INT 0x10
200#define MX51_ECSPI_INT_TEEN (1 << 0)
201#define MX51_ECSPI_INT_RREN (1 << 3)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200202
Shawn Guo66de7572011-07-10 01:16:37 +0800203#define MX51_ECSPI_STAT 0x18
204#define MX51_ECSPI_STAT_RR (1 << 3)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200205
206/* MX51 eCSPI */
Shawn Guo66de7572011-07-10 01:16:37 +0800207static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200208{
209 /*
210 * there are two 4-bit dividers, the pre-divider divides by
211 * $pre, the post-divider by 2^$post
212 */
213 unsigned int pre, post;
214
215 if (unlikely(fspi > fin))
216 return 0;
217
218 post = fls(fin) - fls(fspi);
219 if (fin > fspi << post)
220 post++;
221
222 /* now we have: (fin <= fspi << post) with post being minimal */
223
224 post = max(4U, post) - 4;
225 if (unlikely(post > 0xf)) {
226 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
227 __func__, fspi, fin);
228 return 0xff;
229 }
230
231 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
232
233 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
234 __func__, fin, fspi, post, pre);
Shawn Guo66de7572011-07-10 01:16:37 +0800235 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
236 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200237}
238
Shawn Guo66de7572011-07-10 01:16:37 +0800239static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200240{
241 unsigned val = 0;
242
243 if (enable & MXC_INT_TE)
Shawn Guo66de7572011-07-10 01:16:37 +0800244 val |= MX51_ECSPI_INT_TEEN;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200245
246 if (enable & MXC_INT_RR)
Shawn Guo66de7572011-07-10 01:16:37 +0800247 val |= MX51_ECSPI_INT_RREN;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200248
Shawn Guo66de7572011-07-10 01:16:37 +0800249 writel(val, spi_imx->base + MX51_ECSPI_INT);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200250}
251
Shawn Guo66de7572011-07-10 01:16:37 +0800252static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200253{
254 u32 reg;
255
Shawn Guo66de7572011-07-10 01:16:37 +0800256 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
257 reg |= MX51_ECSPI_CTRL_XCH;
258 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200259}
260
Shawn Guo66de7572011-07-10 01:16:37 +0800261static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200262 struct spi_imx_config *config)
263{
Shawn Guo66de7572011-07-10 01:16:37 +0800264 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200265
Sascha Hauerf020c392011-02-08 21:08:59 +0100266 /*
267 * The hardware seems to have a race condition when changing modes. The
268 * current assumption is that the selection of the channel arrives
269 * earlier in the hardware than the mode bits when they are written at
270 * the same time.
271 * So set master mode for all channels as we do not support slave mode.
272 */
Shawn Guo66de7572011-07-10 01:16:37 +0800273 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200274
275 /* set clock speed */
Shawn Guo66de7572011-07-10 01:16:37 +0800276 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200277
278 /* set chip select to use */
Shawn Guo66de7572011-07-10 01:16:37 +0800279 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200280
Shawn Guo66de7572011-07-10 01:16:37 +0800281 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200282
Shawn Guo66de7572011-07-10 01:16:37 +0800283 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200284
285 if (config->mode & SPI_CPHA)
Shawn Guo66de7572011-07-10 01:16:37 +0800286 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200287
288 if (config->mode & SPI_CPOL)
Shawn Guo66de7572011-07-10 01:16:37 +0800289 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200290
291 if (config->mode & SPI_CS_HIGH)
Shawn Guo66de7572011-07-10 01:16:37 +0800292 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200293
Shawn Guo66de7572011-07-10 01:16:37 +0800294 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
295 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200296
297 return 0;
298}
299
Shawn Guo66de7572011-07-10 01:16:37 +0800300static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200301{
Shawn Guo66de7572011-07-10 01:16:37 +0800302 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200303}
304
Shawn Guo66de7572011-07-10 01:16:37 +0800305static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200306{
307 /* drain receive buffer */
Shawn Guo66de7572011-07-10 01:16:37 +0800308 while (mx51_ecspi_rx_available(spi_imx))
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200309 readl(spi_imx->base + MXC_CSPIRXDATA);
310}
311
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700312#define MX31_INTREG_TEEN (1 << 0)
313#define MX31_INTREG_RREN (1 << 3)
314
315#define MX31_CSPICTRL_ENABLE (1 << 0)
316#define MX31_CSPICTRL_MASTER (1 << 1)
317#define MX31_CSPICTRL_XCH (1 << 2)
318#define MX31_CSPICTRL_POL (1 << 4)
319#define MX31_CSPICTRL_PHA (1 << 5)
320#define MX31_CSPICTRL_SSCTL (1 << 6)
321#define MX31_CSPICTRL_SSPOL (1 << 7)
322#define MX31_CSPICTRL_BC_SHIFT 8
323#define MX35_CSPICTRL_BL_SHIFT 20
324#define MX31_CSPICTRL_CS_SHIFT 24
325#define MX35_CSPICTRL_CS_SHIFT 12
326#define MX31_CSPICTRL_DR_SHIFT 16
327
328#define MX31_CSPISTATUS 0x14
329#define MX31_STATUS_RR (1 << 3)
330
331/* These functions also work for the i.MX35, but be aware that
332 * the i.MX35 has a slightly different register layout for bits
333 * we do not use here.
334 */
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200335static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700336{
337 unsigned int val = 0;
338
339 if (enable & MXC_INT_TE)
340 val |= MX31_INTREG_TEEN;
341 if (enable & MXC_INT_RR)
342 val |= MX31_INTREG_RREN;
343
344 writel(val, spi_imx->base + MXC_CSPIINT);
345}
346
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200347static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700348{
349 unsigned int reg;
350
351 reg = readl(spi_imx->base + MXC_CSPICTRL);
352 reg |= MX31_CSPICTRL_XCH;
353 writel(reg, spi_imx->base + MXC_CSPICTRL);
354}
355
Shawn Guo2a64a902011-07-10 01:16:38 +0800356static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700357 struct spi_imx_config *config)
358{
359 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200360 int cs = spi_imx->chipselect[config->cs];
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700361
362 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
363 MX31_CSPICTRL_DR_SHIFT;
364
Shawn Guo04ee5852011-07-10 01:16:39 +0800365 if (is_imx35_cspi(spi_imx)) {
Shawn Guo2a64a902011-07-10 01:16:38 +0800366 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
367 reg |= MX31_CSPICTRL_SSCTL;
368 } else {
369 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
370 }
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700371
372 if (config->mode & SPI_CPHA)
373 reg |= MX31_CSPICTRL_PHA;
374 if (config->mode & SPI_CPOL)
375 reg |= MX31_CSPICTRL_POL;
376 if (config->mode & SPI_CS_HIGH)
377 reg |= MX31_CSPICTRL_SSPOL;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200378 if (cs < 0)
Shawn Guo2a64a902011-07-10 01:16:38 +0800379 reg |= (cs + 32) <<
Shawn Guo04ee5852011-07-10 01:16:39 +0800380 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
381 MX31_CSPICTRL_CS_SHIFT);
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200382
383 writel(reg, spi_imx->base + MXC_CSPICTRL);
384
385 return 0;
386}
387
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200388static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700389{
390 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
391}
392
Shawn Guo2a64a902011-07-10 01:16:38 +0800393static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200394{
395 /* drain receive buffer */
Shawn Guo2a64a902011-07-10 01:16:38 +0800396 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200397 readl(spi_imx->base + MXC_CSPIRXDATA);
398}
399
Shawn Guo3451fb12011-07-10 01:16:36 +0800400#define MX21_INTREG_RR (1 << 4)
401#define MX21_INTREG_TEEN (1 << 9)
402#define MX21_INTREG_RREN (1 << 13)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700403
Shawn Guo3451fb12011-07-10 01:16:36 +0800404#define MX21_CSPICTRL_POL (1 << 5)
405#define MX21_CSPICTRL_PHA (1 << 6)
406#define MX21_CSPICTRL_SSPOL (1 << 8)
407#define MX21_CSPICTRL_XCH (1 << 9)
408#define MX21_CSPICTRL_ENABLE (1 << 10)
409#define MX21_CSPICTRL_MASTER (1 << 11)
410#define MX21_CSPICTRL_DR_SHIFT 14
411#define MX21_CSPICTRL_CS_SHIFT 19
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700412
Shawn Guo3451fb12011-07-10 01:16:36 +0800413static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700414{
415 unsigned int val = 0;
416
417 if (enable & MXC_INT_TE)
Shawn Guo3451fb12011-07-10 01:16:36 +0800418 val |= MX21_INTREG_TEEN;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700419 if (enable & MXC_INT_RR)
Shawn Guo3451fb12011-07-10 01:16:36 +0800420 val |= MX21_INTREG_RREN;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700421
422 writel(val, spi_imx->base + MXC_CSPIINT);
423}
424
Shawn Guo3451fb12011-07-10 01:16:36 +0800425static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700426{
427 unsigned int reg;
428
429 reg = readl(spi_imx->base + MXC_CSPICTRL);
Shawn Guo3451fb12011-07-10 01:16:36 +0800430 reg |= MX21_CSPICTRL_XCH;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700431 writel(reg, spi_imx->base + MXC_CSPICTRL);
432}
433
Shawn Guo3451fb12011-07-10 01:16:36 +0800434static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700435 struct spi_imx_config *config)
436{
Shawn Guo3451fb12011-07-10 01:16:36 +0800437 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200438 int cs = spi_imx->chipselect[config->cs];
Shawn Guo04ee5852011-07-10 01:16:39 +0800439 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700440
Shawn Guo04ee5852011-07-10 01:16:39 +0800441 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
Shawn Guo3451fb12011-07-10 01:16:36 +0800442 MX21_CSPICTRL_DR_SHIFT;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700443 reg |= config->bpw - 1;
444
445 if (config->mode & SPI_CPHA)
Shawn Guo3451fb12011-07-10 01:16:36 +0800446 reg |= MX21_CSPICTRL_PHA;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700447 if (config->mode & SPI_CPOL)
Shawn Guo3451fb12011-07-10 01:16:36 +0800448 reg |= MX21_CSPICTRL_POL;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700449 if (config->mode & SPI_CS_HIGH)
Shawn Guo3451fb12011-07-10 01:16:36 +0800450 reg |= MX21_CSPICTRL_SSPOL;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200451 if (cs < 0)
Shawn Guo3451fb12011-07-10 01:16:36 +0800452 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700453
454 writel(reg, spi_imx->base + MXC_CSPICTRL);
455
456 return 0;
457}
458
Shawn Guo3451fb12011-07-10 01:16:36 +0800459static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700460{
Shawn Guo3451fb12011-07-10 01:16:36 +0800461 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700462}
463
Shawn Guo3451fb12011-07-10 01:16:36 +0800464static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200465{
466 writel(1, spi_imx->base + MXC_RESET);
467}
468
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700469#define MX1_INTREG_RR (1 << 3)
470#define MX1_INTREG_TEEN (1 << 8)
471#define MX1_INTREG_RREN (1 << 11)
472
473#define MX1_CSPICTRL_POL (1 << 4)
474#define MX1_CSPICTRL_PHA (1 << 5)
475#define MX1_CSPICTRL_XCH (1 << 8)
476#define MX1_CSPICTRL_ENABLE (1 << 9)
477#define MX1_CSPICTRL_MASTER (1 << 10)
478#define MX1_CSPICTRL_DR_SHIFT 13
479
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200480static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700481{
482 unsigned int val = 0;
483
484 if (enable & MXC_INT_TE)
485 val |= MX1_INTREG_TEEN;
486 if (enable & MXC_INT_RR)
487 val |= MX1_INTREG_RREN;
488
489 writel(val, spi_imx->base + MXC_CSPIINT);
490}
491
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200492static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700493{
494 unsigned int reg;
495
496 reg = readl(spi_imx->base + MXC_CSPICTRL);
497 reg |= MX1_CSPICTRL_XCH;
498 writel(reg, spi_imx->base + MXC_CSPICTRL);
499}
500
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200501static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700502 struct spi_imx_config *config)
503{
504 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
505
506 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
507 MX1_CSPICTRL_DR_SHIFT;
508 reg |= config->bpw - 1;
509
510 if (config->mode & SPI_CPHA)
511 reg |= MX1_CSPICTRL_PHA;
512 if (config->mode & SPI_CPOL)
513 reg |= MX1_CSPICTRL_POL;
514
515 writel(reg, spi_imx->base + MXC_CSPICTRL);
516
517 return 0;
518}
519
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200520static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700521{
522 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
523}
524
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200525static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
526{
527 writel(1, spi_imx->base + MXC_RESET);
528}
529
Shawn Guo04ee5852011-07-10 01:16:39 +0800530static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
531 .intctrl = mx1_intctrl,
532 .config = mx1_config,
533 .trigger = mx1_trigger,
534 .rx_available = mx1_rx_available,
535 .reset = mx1_reset,
536 .devtype = IMX1_CSPI,
537};
538
539static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
540 .intctrl = mx21_intctrl,
541 .config = mx21_config,
542 .trigger = mx21_trigger,
543 .rx_available = mx21_rx_available,
544 .reset = mx21_reset,
545 .devtype = IMX21_CSPI,
546};
547
548static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
549 /* i.mx27 cspi shares the functions with i.mx21 one */
550 .intctrl = mx21_intctrl,
551 .config = mx21_config,
552 .trigger = mx21_trigger,
553 .rx_available = mx21_rx_available,
554 .reset = mx21_reset,
555 .devtype = IMX27_CSPI,
556};
557
558static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
559 .intctrl = mx31_intctrl,
560 .config = mx31_config,
561 .trigger = mx31_trigger,
562 .rx_available = mx31_rx_available,
563 .reset = mx31_reset,
564 .devtype = IMX31_CSPI,
565};
566
567static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
568 /* i.mx35 and later cspi shares the functions with i.mx31 one */
569 .intctrl = mx31_intctrl,
570 .config = mx31_config,
571 .trigger = mx31_trigger,
572 .rx_available = mx31_rx_available,
573 .reset = mx31_reset,
574 .devtype = IMX35_CSPI,
575};
576
577static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
578 .intctrl = mx51_ecspi_intctrl,
579 .config = mx51_ecspi_config,
580 .trigger = mx51_ecspi_trigger,
581 .rx_available = mx51_ecspi_rx_available,
582 .reset = mx51_ecspi_reset,
583 .devtype = IMX51_ECSPI,
584};
585
586static struct platform_device_id spi_imx_devtype[] = {
587 {
588 .name = "imx1-cspi",
589 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
590 }, {
591 .name = "imx21-cspi",
592 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
593 }, {
594 .name = "imx27-cspi",
595 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
596 }, {
597 .name = "imx31-cspi",
598 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
599 }, {
600 .name = "imx35-cspi",
601 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
602 }, {
603 .name = "imx51-ecspi",
604 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
605 }, {
606 /* sentinel */
607 }
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200608};
609
Shawn Guo22a85e42011-07-10 01:16:41 +0800610static const struct of_device_id spi_imx_dt_ids[] = {
611 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
612 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
613 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
614 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
615 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
616 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
617 { /* sentinel */ }
618};
619
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700620static void spi_imx_chipselect(struct spi_device *spi, int is_active)
621{
622 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700623 int gpio = spi_imx->chipselect[spi->chip_select];
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700624 int active = is_active != BITBANG_CS_INACTIVE;
625 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700626
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700627 if (gpio < 0)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700628 return;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700629
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700630 gpio_set_value(gpio, dev_is_lowactive ^ active);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700631}
632
633static void spi_imx_push(struct spi_imx_data *spi_imx)
634{
Shawn Guo04ee5852011-07-10 01:16:39 +0800635 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700636 if (!spi_imx->count)
637 break;
638 spi_imx->tx(spi_imx);
639 spi_imx->txfifo++;
640 }
641
Shawn Guoedd501b2011-07-10 01:16:35 +0800642 spi_imx->devtype_data->trigger(spi_imx);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700643}
644
645static irqreturn_t spi_imx_isr(int irq, void *dev_id)
646{
647 struct spi_imx_data *spi_imx = dev_id;
648
Shawn Guoedd501b2011-07-10 01:16:35 +0800649 while (spi_imx->devtype_data->rx_available(spi_imx)) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700650 spi_imx->rx(spi_imx);
651 spi_imx->txfifo--;
652 }
653
654 if (spi_imx->count) {
655 spi_imx_push(spi_imx);
656 return IRQ_HANDLED;
657 }
658
659 if (spi_imx->txfifo) {
660 /* No data left to push, but still waiting for rx data,
661 * enable receive data available interrupt.
662 */
Shawn Guoedd501b2011-07-10 01:16:35 +0800663 spi_imx->devtype_data->intctrl(
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200664 spi_imx, MXC_INT_RR);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700665 return IRQ_HANDLED;
666 }
667
Shawn Guoedd501b2011-07-10 01:16:35 +0800668 spi_imx->devtype_data->intctrl(spi_imx, 0);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700669 complete(&spi_imx->xfer_done);
670
671 return IRQ_HANDLED;
672}
673
674static int spi_imx_setupxfer(struct spi_device *spi,
675 struct spi_transfer *t)
676{
677 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
678 struct spi_imx_config config;
679
680 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
681 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
682 config.mode = spi->mode;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200683 config.cs = spi->chip_select;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700684
Sascha Hauer462d26b2009-10-01 15:44:29 -0700685 if (!config.speed_hz)
686 config.speed_hz = spi->max_speed_hz;
687 if (!config.bpw)
688 config.bpw = spi->bits_per_word;
689 if (!config.speed_hz)
690 config.speed_hz = spi->max_speed_hz;
691
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700692 /* Initialize the functions for transfer */
693 if (config.bpw <= 8) {
694 spi_imx->rx = spi_imx_buf_rx_u8;
695 spi_imx->tx = spi_imx_buf_tx_u8;
696 } else if (config.bpw <= 16) {
697 spi_imx->rx = spi_imx_buf_rx_u16;
698 spi_imx->tx = spi_imx_buf_tx_u16;
699 } else if (config.bpw <= 32) {
700 spi_imx->rx = spi_imx_buf_rx_u32;
701 spi_imx->tx = spi_imx_buf_tx_u32;
702 } else
703 BUG();
704
Shawn Guoedd501b2011-07-10 01:16:35 +0800705 spi_imx->devtype_data->config(spi_imx, &config);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700706
707 return 0;
708}
709
710static int spi_imx_transfer(struct spi_device *spi,
711 struct spi_transfer *transfer)
712{
713 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
714
715 spi_imx->tx_buf = transfer->tx_buf;
716 spi_imx->rx_buf = transfer->rx_buf;
717 spi_imx->count = transfer->len;
718 spi_imx->txfifo = 0;
719
720 init_completion(&spi_imx->xfer_done);
721
722 spi_imx_push(spi_imx);
723
Shawn Guoedd501b2011-07-10 01:16:35 +0800724 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700725
726 wait_for_completion(&spi_imx->xfer_done);
727
728 return transfer->len;
729}
730
731static int spi_imx_setup(struct spi_device *spi)
732{
Sascha Hauer6c23e5d2009-10-01 15:44:29 -0700733 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
734 int gpio = spi_imx->chipselect[spi->chip_select];
735
Alberto Panizzof4d4ecf2010-01-20 13:49:45 -0700736 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700737 spi->mode, spi->bits_per_word, spi->max_speed_hz);
738
Sascha Hauer6c23e5d2009-10-01 15:44:29 -0700739 if (gpio >= 0)
740 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
741
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700742 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
743
744 return 0;
745}
746
747static void spi_imx_cleanup(struct spi_device *spi)
748{
749}
750
Grant Likely965346e2009-12-13 01:03:12 -0700751static int __devinit spi_imx_probe(struct platform_device *pdev)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700752{
Shawn Guo22a85e42011-07-10 01:16:41 +0800753 struct device_node *np = pdev->dev.of_node;
754 const struct of_device_id *of_id =
755 of_match_device(spi_imx_dt_ids, &pdev->dev);
756 struct spi_imx_master *mxc_platform_info =
757 dev_get_platdata(&pdev->dev);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700758 struct spi_master *master;
759 struct spi_imx_data *spi_imx;
760 struct resource *res;
Shawn Guoc2387cb2011-07-10 01:16:40 +0800761 int i, ret, num_cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700762
Shawn Guo22a85e42011-07-10 01:16:41 +0800763 if (!np && !mxc_platform_info) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700764 dev_err(&pdev->dev, "can't get the platform data\n");
765 return -EINVAL;
766 }
767
Shawn Guo22a85e42011-07-10 01:16:41 +0800768 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
Lothar Waßmann39ec0d32012-04-03 15:03:44 +0200769 if (ret < 0) {
770 if (mxc_platform_info)
771 num_cs = mxc_platform_info->num_chipselect;
772 else
773 return ret;
774 }
Shawn Guo22a85e42011-07-10 01:16:41 +0800775
Shawn Guoc2387cb2011-07-10 01:16:40 +0800776 master = spi_alloc_master(&pdev->dev,
777 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700778 if (!master)
779 return -ENOMEM;
780
781 platform_set_drvdata(pdev, master);
782
783 master->bus_num = pdev->id;
Shawn Guoc2387cb2011-07-10 01:16:40 +0800784 master->num_chipselect = num_cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700785
786 spi_imx = spi_master_get_devdata(master);
787 spi_imx->bitbang.master = spi_master_get(master);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700788
789 for (i = 0; i < master->num_chipselect; i++) {
Shawn Guo22a85e42011-07-10 01:16:41 +0800790 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
Lothar Waßmann39ec0d32012-04-03 15:03:44 +0200791 if (cs_gpio < 0 && mxc_platform_info)
Shawn Guo22a85e42011-07-10 01:16:41 +0800792 cs_gpio = mxc_platform_info->chipselect[i];
Fabio Estevam4cc122a2011-09-15 17:21:15 -0300793
794 spi_imx->chipselect[i] = cs_gpio;
Shawn Guo22a85e42011-07-10 01:16:41 +0800795 if (cs_gpio < 0)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700796 continue;
Fabio Estevam4cc122a2011-09-15 17:21:15 -0300797
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700798 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
799 if (ret) {
John Ognessbbd050a2009-11-24 16:53:07 +0000800 dev_err(&pdev->dev, "can't get cs gpios\n");
Axel Lin00ffc132012-01-10 15:27:36 +0800801 goto out_gpio_free;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700802 }
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700803 }
804
805 spi_imx->bitbang.chipselect = spi_imx_chipselect;
806 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
807 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
808 spi_imx->bitbang.master->setup = spi_imx_setup;
809 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
Sascha Hauer3910f2c2009-10-01 15:44:30 -0700810 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700811
812 init_completion(&spi_imx->xfer_done);
813
Shawn Guo22a85e42011-07-10 01:16:41 +0800814 spi_imx->devtype_data = of_id ? of_id->data :
Shawn Guo04ee5852011-07-10 01:16:39 +0800815 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200816
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 if (!res) {
819 dev_err(&pdev->dev, "can't get platform resource\n");
820 ret = -ENOMEM;
821 goto out_gpio_free;
822 }
823
824 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
825 dev_err(&pdev->dev, "request_mem_region failed\n");
826 ret = -EBUSY;
827 goto out_gpio_free;
828 }
829
830 spi_imx->base = ioremap(res->start, resource_size(res));
831 if (!spi_imx->base) {
832 ret = -EINVAL;
833 goto out_release_mem;
834 }
835
836 spi_imx->irq = platform_get_irq(pdev, 0);
Richard Genoud73575932011-01-07 15:26:01 +0100837 if (spi_imx->irq < 0) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700838 ret = -EINVAL;
839 goto out_iounmap;
840 }
841
842 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
843 if (ret) {
844 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
845 goto out_iounmap;
846 }
847
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700848 spi_imx->clk = clk_get(&pdev->dev, NULL);
849 if (IS_ERR(spi_imx->clk)) {
850 dev_err(&pdev->dev, "unable to get clock\n");
851 ret = PTR_ERR(spi_imx->clk);
852 goto out_free_irq;
853 }
854
855 clk_enable(spi_imx->clk);
856 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
857
Shawn Guoedd501b2011-07-10 01:16:35 +0800858 spi_imx->devtype_data->reset(spi_imx);
Daniel Mackce1807b2009-11-19 19:01:42 +0000859
Shawn Guoedd501b2011-07-10 01:16:35 +0800860 spi_imx->devtype_data->intctrl(spi_imx, 0);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700861
Shawn Guo22a85e42011-07-10 01:16:41 +0800862 master->dev.of_node = pdev->dev.of_node;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700863 ret = spi_bitbang_start(&spi_imx->bitbang);
864 if (ret) {
865 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
866 goto out_clk_put;
867 }
868
869 dev_info(&pdev->dev, "probed\n");
870
871 return ret;
872
873out_clk_put:
874 clk_disable(spi_imx->clk);
875 clk_put(spi_imx->clk);
876out_free_irq:
877 free_irq(spi_imx->irq, spi_imx);
878out_iounmap:
879 iounmap(spi_imx->base);
880out_release_mem:
881 release_mem_region(res->start, resource_size(res));
882out_gpio_free:
Axel Lin00ffc132012-01-10 15:27:36 +0800883 while (--i >= 0) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700884 if (spi_imx->chipselect[i] >= 0)
885 gpio_free(spi_imx->chipselect[i]);
Axel Lin00ffc132012-01-10 15:27:36 +0800886 }
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700887 spi_master_put(master);
888 kfree(master);
889 platform_set_drvdata(pdev, NULL);
890 return ret;
891}
892
Grant Likely965346e2009-12-13 01:03:12 -0700893static int __devexit spi_imx_remove(struct platform_device *pdev)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700894{
895 struct spi_master *master = platform_get_drvdata(pdev);
896 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
898 int i;
899
900 spi_bitbang_stop(&spi_imx->bitbang);
901
902 writel(0, spi_imx->base + MXC_CSPICTRL);
903 clk_disable(spi_imx->clk);
904 clk_put(spi_imx->clk);
905 free_irq(spi_imx->irq, spi_imx);
906 iounmap(spi_imx->base);
907
908 for (i = 0; i < master->num_chipselect; i++)
909 if (spi_imx->chipselect[i] >= 0)
910 gpio_free(spi_imx->chipselect[i]);
911
912 spi_master_put(master);
913
914 release_mem_region(res->start, resource_size(res));
915
916 platform_set_drvdata(pdev, NULL);
917
918 return 0;
919}
920
921static struct platform_driver spi_imx_driver = {
922 .driver = {
923 .name = DRIVER_NAME,
924 .owner = THIS_MODULE,
Shawn Guo22a85e42011-07-10 01:16:41 +0800925 .of_match_table = spi_imx_dt_ids,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700926 },
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200927 .id_table = spi_imx_devtype,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700928 .probe = spi_imx_probe,
Grant Likely965346e2009-12-13 01:03:12 -0700929 .remove = __devexit_p(spi_imx_remove),
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700930};
Grant Likely940ab882011-10-05 11:29:49 -0600931module_platform_driver(spi_imx_driver);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700932
933MODULE_DESCRIPTION("SPI Master Controller driver");
934MODULE_AUTHOR("Sascha Hauer, Pengutronix");
935MODULE_LICENSE("GPL");