Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-ppc/mv64x60.h |
| 3 | * |
| 4 | * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. |
| 5 | * |
| 6 | * Author: Mark A. Greer <mgreer@mvista.com> |
| 7 | * |
| 8 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under |
| 9 | * the terms of the GNU General Public License version 2. This program |
| 10 | * is licensed "as is" without any warranty of any kind, whether express |
| 11 | * or implied. |
| 12 | */ |
| 13 | #ifndef __ASMPPC_MV64x60_H |
| 14 | #define __ASMPPC_MV64x60_H |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/pci.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/config.h> |
| 21 | |
| 22 | #include <asm/byteorder.h> |
| 23 | #include <asm/io.h> |
| 24 | #include <asm/irq.h> |
| 25 | #include <asm/uaccess.h> |
| 26 | #include <asm/machdep.h> |
| 27 | #include <asm/pci-bridge.h> |
| 28 | #include <asm/mv64x60_defs.h> |
| 29 | |
| 30 | extern u8 mv64x60_pci_exclude_bridge; |
| 31 | |
| 32 | extern spinlock_t mv64x60_lock; |
| 33 | |
| 34 | /* 32-bit Window table entry defines */ |
| 35 | #define MV64x60_CPU2MEM_0_WIN 0 |
| 36 | #define MV64x60_CPU2MEM_1_WIN 1 |
| 37 | #define MV64x60_CPU2MEM_2_WIN 2 |
| 38 | #define MV64x60_CPU2MEM_3_WIN 3 |
| 39 | #define MV64x60_CPU2DEV_0_WIN 4 |
| 40 | #define MV64x60_CPU2DEV_1_WIN 5 |
| 41 | #define MV64x60_CPU2DEV_2_WIN 6 |
| 42 | #define MV64x60_CPU2DEV_3_WIN 7 |
| 43 | #define MV64x60_CPU2BOOT_WIN 8 |
| 44 | #define MV64x60_CPU2PCI0_IO_WIN 9 |
| 45 | #define MV64x60_CPU2PCI0_MEM_0_WIN 10 |
| 46 | #define MV64x60_CPU2PCI0_MEM_1_WIN 11 |
| 47 | #define MV64x60_CPU2PCI0_MEM_2_WIN 12 |
| 48 | #define MV64x60_CPU2PCI0_MEM_3_WIN 13 |
| 49 | #define MV64x60_CPU2PCI1_IO_WIN 14 |
| 50 | #define MV64x60_CPU2PCI1_MEM_0_WIN 15 |
| 51 | #define MV64x60_CPU2PCI1_MEM_1_WIN 16 |
| 52 | #define MV64x60_CPU2PCI1_MEM_2_WIN 17 |
| 53 | #define MV64x60_CPU2PCI1_MEM_3_WIN 18 |
| 54 | #define MV64x60_CPU2SRAM_WIN 19 |
| 55 | #define MV64x60_CPU2PCI0_IO_REMAP_WIN 20 |
| 56 | #define MV64x60_CPU2PCI1_IO_REMAP_WIN 21 |
| 57 | #define MV64x60_CPU_PROT_0_WIN 22 |
| 58 | #define MV64x60_CPU_PROT_1_WIN 23 |
| 59 | #define MV64x60_CPU_PROT_2_WIN 24 |
| 60 | #define MV64x60_CPU_PROT_3_WIN 25 |
| 61 | #define MV64x60_CPU_SNOOP_0_WIN 26 |
| 62 | #define MV64x60_CPU_SNOOP_1_WIN 27 |
| 63 | #define MV64x60_CPU_SNOOP_2_WIN 28 |
| 64 | #define MV64x60_CPU_SNOOP_3_WIN 29 |
| 65 | #define MV64x60_PCI02MEM_REMAP_0_WIN 30 |
| 66 | #define MV64x60_PCI02MEM_REMAP_1_WIN 31 |
| 67 | #define MV64x60_PCI02MEM_REMAP_2_WIN 32 |
| 68 | #define MV64x60_PCI02MEM_REMAP_3_WIN 33 |
| 69 | #define MV64x60_PCI12MEM_REMAP_0_WIN 34 |
| 70 | #define MV64x60_PCI12MEM_REMAP_1_WIN 35 |
| 71 | #define MV64x60_PCI12MEM_REMAP_2_WIN 36 |
| 72 | #define MV64x60_PCI12MEM_REMAP_3_WIN 37 |
| 73 | #define MV64x60_ENET2MEM_0_WIN 38 |
| 74 | #define MV64x60_ENET2MEM_1_WIN 39 |
| 75 | #define MV64x60_ENET2MEM_2_WIN 40 |
| 76 | #define MV64x60_ENET2MEM_3_WIN 41 |
| 77 | #define MV64x60_ENET2MEM_4_WIN 42 |
| 78 | #define MV64x60_ENET2MEM_5_WIN 43 |
| 79 | #define MV64x60_MPSC2MEM_0_WIN 44 |
| 80 | #define MV64x60_MPSC2MEM_1_WIN 45 |
| 81 | #define MV64x60_MPSC2MEM_2_WIN 46 |
| 82 | #define MV64x60_MPSC2MEM_3_WIN 47 |
| 83 | #define MV64x60_IDMA2MEM_0_WIN 48 |
| 84 | #define MV64x60_IDMA2MEM_1_WIN 49 |
| 85 | #define MV64x60_IDMA2MEM_2_WIN 50 |
| 86 | #define MV64x60_IDMA2MEM_3_WIN 51 |
| 87 | #define MV64x60_IDMA2MEM_4_WIN 52 |
| 88 | #define MV64x60_IDMA2MEM_5_WIN 53 |
| 89 | #define MV64x60_IDMA2MEM_6_WIN 54 |
| 90 | #define MV64x60_IDMA2MEM_7_WIN 55 |
| 91 | |
| 92 | #define MV64x60_32BIT_WIN_COUNT 56 |
| 93 | |
| 94 | /* 64-bit Window table entry defines */ |
| 95 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 |
| 96 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1 |
| 97 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2 |
| 98 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3 |
| 99 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4 |
| 100 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5 |
| 101 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6 |
| 102 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7 |
| 103 | #define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8 |
| 104 | #define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9 |
| 105 | #define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10 |
| 106 | #define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11 |
| 107 | #define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12 |
| 108 | #define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13 |
| 109 | #define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14 |
| 110 | #define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15 |
| 111 | #define MV64x60_PCI02MEM_SNOOP_0_WIN 16 |
| 112 | #define MV64x60_PCI02MEM_SNOOP_1_WIN 17 |
| 113 | #define MV64x60_PCI02MEM_SNOOP_2_WIN 18 |
| 114 | #define MV64x60_PCI02MEM_SNOOP_3_WIN 19 |
| 115 | #define MV64x60_PCI12MEM_SNOOP_0_WIN 20 |
| 116 | #define MV64x60_PCI12MEM_SNOOP_1_WIN 21 |
| 117 | #define MV64x60_PCI12MEM_SNOOP_2_WIN 22 |
| 118 | #define MV64x60_PCI12MEM_SNOOP_3_WIN 23 |
| 119 | |
| 120 | #define MV64x60_64BIT_WIN_COUNT 24 |
| 121 | |
James Chapman | 3be1021 | 2005-08-17 09:01:33 +0200 | [diff] [blame^] | 122 | /* Watchdog Platform Device, Driver Data */ |
| 123 | #define MV64x60_WDT_NAME "wdt" |
| 124 | |
| 125 | struct mv64x60_wdt_pdata { |
| 126 | int timeout; /* watchdog expiry in seconds, default 10 */ |
| 127 | int bus_clk; /* bus clock in MHz, default 133 */ |
| 128 | }; |
| 129 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | /* |
| 131 | * Define a structure that's used to pass in config information to the |
| 132 | * core routines. |
| 133 | */ |
| 134 | struct mv64x60_pci_window { |
| 135 | u32 cpu_base; |
| 136 | u32 pci_base_hi; |
| 137 | u32 pci_base_lo; |
| 138 | u32 size; |
| 139 | u32 swap; |
| 140 | }; |
| 141 | |
| 142 | struct mv64x60_pci_info { |
| 143 | u8 enable_bus; /* allow access to this PCI bus? */ |
| 144 | |
| 145 | struct mv64x60_pci_window pci_io; |
| 146 | struct mv64x60_pci_window pci_mem[3]; |
| 147 | |
| 148 | u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; |
| 149 | u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; |
| 150 | u16 pci_cmd_bits; |
| 151 | u16 latency_timer; |
| 152 | }; |
| 153 | |
| 154 | struct mv64x60_setup_info { |
| 155 | u32 phys_reg_base; |
| 156 | u32 window_preserve_mask_32_hi; |
| 157 | u32 window_preserve_mask_32_lo; |
| 158 | u32 window_preserve_mask_64; |
| 159 | |
| 160 | u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; |
| 161 | u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; |
| 162 | u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; |
| 163 | u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; |
| 164 | u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; |
| 165 | |
| 166 | struct mv64x60_pci_info pci_0; |
| 167 | struct mv64x60_pci_info pci_1; |
| 168 | }; |
| 169 | |
| 170 | /* Define what the top bits in the extra member of a window entry means. */ |
| 171 | #define MV64x60_EXTRA_INVALID 0x00000000 |
| 172 | #define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 |
| 173 | #define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 |
| 174 | #define MV64x60_EXTRA_ENET_ENAB 0x30000000 |
| 175 | #define MV64x60_EXTRA_MPSC_ENAB 0x40000000 |
| 176 | #define MV64x60_EXTRA_IDMA_ENAB 0x50000000 |
| 177 | #define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 |
| 178 | |
| 179 | #define MV64x60_EXTRA_MASK 0xf0000000 |
| 180 | |
| 181 | /* |
| 182 | * Define the 'handle' struct that will be passed between the 64x60 core |
| 183 | * code and the platform-specific code that will use it. The handle |
| 184 | * will contain pointers to chip-specific routines & information. |
| 185 | */ |
| 186 | struct mv64x60_32bit_window { |
| 187 | u32 base_reg; |
| 188 | u32 size_reg; |
| 189 | u8 base_bits; |
| 190 | u8 size_bits; |
| 191 | u32 (*get_from_field)(u32 val, u32 num_bits); |
| 192 | u32 (*map_to_field)(u32 val, u32 num_bits); |
| 193 | u32 extra; |
| 194 | }; |
| 195 | |
| 196 | struct mv64x60_64bit_window { |
| 197 | u32 base_hi_reg; |
| 198 | u32 base_lo_reg; |
| 199 | u32 size_reg; |
| 200 | u8 base_lo_bits; |
| 201 | u8 size_bits; |
| 202 | u32 (*get_from_field)(u32 val, u32 num_bits); |
| 203 | u32 (*map_to_field)(u32 val, u32 num_bits); |
| 204 | u32 extra; |
| 205 | }; |
| 206 | |
| 207 | typedef struct mv64x60_handle mv64x60_handle_t; |
| 208 | struct mv64x60_chip_info { |
| 209 | u32 (*translate_size)(u32 base, u32 size, u32 num_bits); |
| 210 | u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); |
| 211 | void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, |
| 212 | u32 window, u32 base); |
| 213 | void (*set_pci2regs_window)(struct mv64x60_handle *bh, |
| 214 | struct pci_controller *hose, u32 bus, u32 base); |
| 215 | u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); |
| 216 | void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); |
| 217 | void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); |
| 218 | void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); |
| 219 | void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); |
| 220 | void (*disable_all_windows)(mv64x60_handle_t *bh, |
| 221 | struct mv64x60_setup_info *si); |
| 222 | void (*config_io2mem_windows)(mv64x60_handle_t *bh, |
| 223 | struct mv64x60_setup_info *si, |
| 224 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); |
| 225 | void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); |
| 226 | void (*chip_specific_init)(mv64x60_handle_t *bh, |
| 227 | struct mv64x60_setup_info *si); |
| 228 | |
| 229 | struct mv64x60_32bit_window *window_tab_32bit; |
| 230 | struct mv64x60_64bit_window *window_tab_64bit; |
| 231 | }; |
| 232 | |
| 233 | struct mv64x60_handle { |
| 234 | u32 type; /* type of bridge */ |
| 235 | u32 rev; /* revision of bridge */ |
| 236 | void *v_base; /* virtual base addr of bridge regs */ |
| 237 | phys_addr_t p_base; /* physical base addr of bridge regs */ |
| 238 | |
| 239 | u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ |
| 240 | u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ |
| 241 | |
| 242 | u32 io_base_a; /* vaddr of pci 0's I/O space */ |
| 243 | u32 io_base_b; /* vaddr of pci 1's I/O space */ |
| 244 | |
| 245 | struct pci_controller *hose_a; |
| 246 | struct pci_controller *hose_b; |
| 247 | |
| 248 | struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ |
| 249 | }; |
| 250 | |
| 251 | |
| 252 | /* Define I/O routines for accessing registers on the 64x60 bridge. */ |
| 253 | extern inline void |
| 254 | mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { |
| 255 | ulong flags; |
| 256 | |
| 257 | spin_lock_irqsave(&mv64x60_lock, flags); |
| 258 | out_le32(bh->v_base + offset, val); |
| 259 | spin_unlock_irqrestore(&mv64x60_lock, flags); |
| 260 | } |
| 261 | |
| 262 | extern inline u32 |
| 263 | mv64x60_read(struct mv64x60_handle *bh, u32 offset) { |
| 264 | ulong flags; |
| 265 | u32 reg; |
| 266 | |
| 267 | spin_lock_irqsave(&mv64x60_lock, flags); |
| 268 | reg = in_le32(bh->v_base + offset); |
| 269 | spin_unlock_irqrestore(&mv64x60_lock, flags); |
| 270 | return reg; |
| 271 | } |
| 272 | |
| 273 | extern inline void |
| 274 | mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) |
| 275 | { |
| 276 | u32 reg; |
| 277 | ulong flags; |
| 278 | |
| 279 | spin_lock_irqsave(&mv64x60_lock, flags); |
| 280 | reg = in_le32(bh->v_base + offs) & (~mask); |
| 281 | reg |= data & mask; |
| 282 | out_le32(bh->v_base + offs, reg); |
| 283 | spin_unlock_irqrestore(&mv64x60_lock, flags); |
| 284 | } |
| 285 | |
| 286 | #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) |
| 287 | #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) |
| 288 | |
Mark A. Greer | d01c08c | 2005-09-03 15:55:56 -0700 | [diff] [blame] | 289 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) |
| 290 | #define MV64XXX_DEV_NAME "mv64xxx" |
| 291 | |
| 292 | struct mv64xxx_pdata { |
| 293 | u32 hs_reg_valid; |
| 294 | }; |
| 295 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
| 297 | /* Externally visible function prototypes */ |
| 298 | int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); |
| 299 | u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); |
| 300 | void mv64x60_early_init(struct mv64x60_handle *bh, |
| 301 | struct mv64x60_setup_info *si); |
| 302 | void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, |
| 303 | u32 cfg_data, struct pci_controller **hose); |
| 304 | int mv64x60_get_type(struct mv64x60_handle *bh); |
| 305 | int mv64x60_setup_for_chip(struct mv64x60_handle *bh); |
| 306 | void *mv64x60_get_bridge_vbase(void); |
| 307 | u32 mv64x60_get_bridge_type(void); |
| 308 | u32 mv64x60_get_bridge_rev(void); |
| 309 | void mv64x60_get_mem_windows(struct mv64x60_handle *bh, |
| 310 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); |
| 311 | void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, |
| 312 | struct mv64x60_setup_info *si, |
| 313 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); |
| 314 | void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, |
| 315 | struct mv64x60_pci_info *pi, u32 bus); |
| 316 | void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, |
| 317 | struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, |
| 318 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); |
| 319 | void mv64x60_config_resources(struct pci_controller *hose, |
| 320 | struct mv64x60_pci_info *pi, u32 io_base); |
| 321 | void mv64x60_config_pci_params(struct pci_controller *hose, |
| 322 | struct mv64x60_pci_info *pi); |
| 323 | void mv64x60_pd_fixup(struct mv64x60_handle *bh, |
| 324 | struct platform_device *pd_devs[], u32 entries); |
| 325 | void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, |
| 326 | u32 *base, u32 *size); |
| 327 | void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, |
| 328 | u32 size, u32 other_bits); |
| 329 | void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, |
| 330 | u32 *base_hi, u32 *base_lo, u32 *size); |
| 331 | void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, |
| 332 | u32 base_hi, u32 base_lo, u32 size, u32 other_bits); |
| 333 | void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); |
| 334 | int mv64x60_pci_exclude_device(u8 bus, u8 devfn); |
| 335 | |
| 336 | |
| 337 | void gt64260_init_irq(void); |
| 338 | int gt64260_get_irq(struct pt_regs *regs); |
| 339 | void mv64360_init_irq(void); |
| 340 | int mv64360_get_irq(struct pt_regs *regs); |
| 341 | |
| 342 | u32 mv64x60_mask(u32 val, u32 num_bits); |
| 343 | u32 mv64x60_shift_left(u32 val, u32 num_bits); |
| 344 | u32 mv64x60_shift_right(u32 val, u32 num_bits); |
| 345 | u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, |
| 346 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); |
| 347 | |
| 348 | void mv64x60_progress_init(u32 base); |
| 349 | void mv64x60_mpsc_progress(char *s, unsigned short hex); |
| 350 | |
| 351 | extern struct mv64x60_32bit_window |
| 352 | gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; |
| 353 | extern struct mv64x60_64bit_window |
| 354 | gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; |
| 355 | extern struct mv64x60_32bit_window |
| 356 | mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; |
| 357 | extern struct mv64x60_64bit_window |
| 358 | mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; |
| 359 | |
| 360 | #endif /* __ASMPPC_MV64x60_H */ |