Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef _INTELFBHW_H |
| 2 | #define _INTELFBHW_H |
| 3 | |
| 4 | /* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */ |
| 5 | |
| 6 | |
| 7 | /*** HW-specific data ***/ |
| 8 | |
| 9 | /* Information about the 852GM/855GM variants */ |
| 10 | #define INTEL_85X_CAPID 0x44 |
| 11 | #define INTEL_85X_VARIANT_MASK 0x7 |
| 12 | #define INTEL_85X_VARIANT_SHIFT 5 |
| 13 | #define INTEL_VAR_855GME 0x0 |
| 14 | #define INTEL_VAR_855GM 0x4 |
| 15 | #define INTEL_VAR_852GME 0x2 |
| 16 | #define INTEL_VAR_852GM 0x5 |
| 17 | |
| 18 | /* Information about DVO/LVDS Ports */ |
| 19 | #define DVOA_PORT 0x1 |
| 20 | #define DVOB_PORT 0x2 |
| 21 | #define DVOC_PORT 0x4 |
| 22 | #define LVDS_PORT 0x8 |
| 23 | |
| 24 | /* |
| 25 | * The Bridge device's PCI config space has information about the |
| 26 | * fb aperture size and the amount of pre-reserved memory. |
| 27 | */ |
| 28 | #define INTEL_GMCH_CTRL 0x52 |
| 29 | #define INTEL_GMCH_ENABLED 0x4 |
| 30 | #define INTEL_GMCH_MEM_MASK 0x1 |
| 31 | #define INTEL_GMCH_MEM_64M 0x1 |
| 32 | #define INTEL_GMCH_MEM_128M 0 |
| 33 | |
| 34 | #define INTEL_830_GMCH_GMS_MASK (0x7 << 4) |
| 35 | #define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4) |
| 36 | #define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4) |
| 37 | #define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4) |
| 38 | #define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4) |
| 39 | #define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4) |
| 40 | |
| 41 | #define INTEL_855_GMCH_GMS_MASK (0x7 << 4) |
| 42 | #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) |
| 43 | #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) |
| 44 | #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) |
| 45 | #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) |
| 46 | #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) |
| 47 | #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) |
| 48 | |
| 49 | #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) |
| 50 | #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) |
| 51 | |
| 52 | /* HW registers */ |
| 53 | |
| 54 | /* Fence registers */ |
| 55 | #define FENCE 0x2000 |
| 56 | #define FENCE_NUM 8 |
| 57 | |
| 58 | /* Primary ring buffer */ |
| 59 | #define PRI_RING_TAIL 0x2030 |
| 60 | #define RING_TAIL_MASK 0x001ffff8 |
| 61 | #define RING_INUSE 0x1 |
| 62 | |
| 63 | #define PRI_RING_HEAD 0x2034 |
| 64 | #define RING_HEAD_WRAP_MASK 0x7ff |
| 65 | #define RING_HEAD_WRAP_SHIFT 21 |
| 66 | #define RING_HEAD_MASK 0x001ffffc |
| 67 | |
| 68 | #define PRI_RING_START 0x2038 |
| 69 | #define RING_START_MASK 0xfffff000 |
| 70 | |
| 71 | #define PRI_RING_LENGTH 0x203c |
| 72 | #define RING_LENGTH_MASK 0x001ff000 |
| 73 | #define RING_REPORT_MASK (0x3 << 1) |
| 74 | #define RING_NO_REPORT (0x0 << 1) |
| 75 | #define RING_REPORT_64K (0x1 << 1) |
| 76 | #define RING_REPORT_4K (0x2 << 1) |
| 77 | #define RING_REPORT_128K (0x3 << 1) |
| 78 | #define RING_ENABLE 0x1 |
| 79 | |
| 80 | /* |
| 81 | * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head, |
| 82 | * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP |
| 83 | */ |
| 84 | #define RING_MIN_FREE 64 |
| 85 | |
| 86 | #define IPEHR 0x2088 |
| 87 | |
| 88 | #define INSTDONE 0x2090 |
| 89 | #define PRI_RING_EMPTY 1 |
| 90 | |
| 91 | #define INSTPM 0x20c0 |
| 92 | #define SYNC_FLUSH_ENABLE (1 << 5) |
| 93 | |
| 94 | #define INSTPS 0x20c4 |
| 95 | |
| 96 | #define MEM_MODE 0x20cc |
| 97 | |
| 98 | #define MASK_SHIFT 16 |
| 99 | |
| 100 | #define FW_BLC_0 0x20d8 |
| 101 | #define FW_DISPA_WM_SHIFT 0 |
| 102 | #define FW_DISPA_WM_MASK 0x3f |
| 103 | #define FW_DISPA_BL_SHIFT 8 |
| 104 | #define FW_DISPA_BL_MASK 0xf |
| 105 | #define FW_DISPB_WM_SHIFT 16 |
| 106 | #define FW_DISPB_WM_MASK 0x1f |
| 107 | #define FW_DISPB_BL_SHIFT 24 |
| 108 | #define FW_DISPB_BL_MASK 0x7 |
| 109 | |
| 110 | #define FW_BLC_1 0x20dc |
| 111 | #define FW_DISPC_WM_SHIFT 0 |
| 112 | #define FW_DISPC_WM_MASK 0x1f |
| 113 | #define FW_DISPC_BL_SHIFT 8 |
| 114 | #define FW_DISPC_BL_MASK 0x7 |
| 115 | |
| 116 | |
| 117 | /* PLL registers */ |
| 118 | #define VGA0_DIVISOR 0x06000 |
| 119 | #define VGA1_DIVISOR 0x06004 |
| 120 | #define VGAPD 0x06010 |
| 121 | #define VGAPD_0_P1_SHIFT 0 |
| 122 | #define VGAPD_0_P1_FORCE_DIV2 (1 << 5) |
| 123 | #define VGAPD_0_P2_SHIFT 7 |
| 124 | #define VGAPD_1_P1_SHIFT 8 |
| 125 | #define VGAPD_1_P1_FORCE_DIV2 (1 << 13) |
| 126 | #define VGAPD_1_P2_SHIFT 15 |
| 127 | |
| 128 | #define DPLL_A 0x06014 |
| 129 | #define DPLL_B 0x06018 |
| 130 | #define DPLL_VCO_ENABLE (1 << 31) |
| 131 | #define DPLL_2X_CLOCK_ENABLE (1 << 30) |
| 132 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
| 133 | #define DPLL_VGA_MODE_DISABLE (1 << 28) |
| 134 | #define DPLL_P2_MASK 1 |
| 135 | #define DPLL_P2_SHIFT 23 |
Dave Airlie | 3aff13c | 2006-03-31 17:08:52 +1000 | [diff] [blame] | 136 | #define DPLL_I9XX_P2_SHIFT 24 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | #define DPLL_P1_FORCE_DIV2 (1 << 21) |
| 138 | #define DPLL_P1_MASK 0x1f |
| 139 | #define DPLL_P1_SHIFT 16 |
| 140 | #define DPLL_REFERENCE_SELECT_MASK (0x3 << 13) |
| 141 | #define DPLL_REFERENCE_DEFAULT (0x0 << 13) |
| 142 | #define DPLL_REFERENCE_TVCLK (0x2 << 13) |
| 143 | #define DPLL_RATE_SELECT_MASK (1 << 8) |
| 144 | #define DPLL_RATE_SELECT_FP0 (0 << 8) |
| 145 | #define DPLL_RATE_SELECT_FP1 (1 << 8) |
| 146 | |
| 147 | #define FPA0 0x06040 |
| 148 | #define FPA1 0x06044 |
| 149 | #define FPB0 0x06048 |
| 150 | #define FPB1 0x0604c |
| 151 | #define FP_DIVISOR_MASK 0x3f |
| 152 | #define FP_N_DIVISOR_SHIFT 16 |
| 153 | #define FP_M1_DIVISOR_SHIFT 8 |
| 154 | #define FP_M2_DIVISOR_SHIFT 0 |
| 155 | |
| 156 | /* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */ |
| 157 | /* Clock values are in units of kHz */ |
| 158 | #define PLL_REFCLK 48000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | #define MIN_CLOCK 25000 |
| 160 | #define MAX_CLOCK 350000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | /* Two pipes */ |
| 163 | #define PIPE_A 0 |
| 164 | #define PIPE_B 1 |
| 165 | #define PIPE_MASK 1 |
| 166 | |
| 167 | /* palette registers */ |
| 168 | #define PALETTE_A 0x0a000 |
| 169 | #define PALETTE_B 0x0a800 |
| 170 | #ifndef PALETTE_8_ENTRIES |
| 171 | #define PALETTE_8_ENTRIES 256 |
| 172 | #endif |
| 173 | #define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4) |
| 174 | #define PALETTE_10_ENTRIES 128 |
| 175 | #define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8) |
| 176 | #define PALETTE_8_MASK 0xff |
| 177 | #define PALETTE_8_RED_SHIFT 16 |
| 178 | #define PALETTE_8_GREEN_SHIFT 8 |
| 179 | #define PALETTE_8_BLUE_SHIFT 0 |
| 180 | |
| 181 | /* CRTC registers */ |
| 182 | #define HTOTAL_A 0x60000 |
| 183 | #define HBLANK_A 0x60004 |
| 184 | #define HSYNC_A 0x60008 |
| 185 | #define VTOTAL_A 0x6000c |
| 186 | #define VBLANK_A 0x60010 |
| 187 | #define VSYNC_A 0x60014 |
| 188 | #define SRC_SIZE_A 0x6001c |
| 189 | #define BCLRPAT_A 0x60020 |
| 190 | |
| 191 | #define HTOTAL_B 0x61000 |
| 192 | #define HBLANK_B 0x61004 |
| 193 | #define HSYNC_B 0x61008 |
| 194 | #define VTOTAL_B 0x6100c |
| 195 | #define VBLANK_B 0x61010 |
| 196 | #define VSYNC_B 0x61014 |
| 197 | #define SRC_SIZE_B 0x6101c |
| 198 | #define BCLRPAT_B 0x61020 |
| 199 | |
| 200 | #define HTOTAL_MASK 0xfff |
| 201 | #define HTOTAL_SHIFT 16 |
| 202 | #define HACTIVE_MASK 0x7ff |
| 203 | #define HACTIVE_SHIFT 0 |
| 204 | #define HBLANKEND_MASK 0xfff |
| 205 | #define HBLANKEND_SHIFT 16 |
| 206 | #define HBLANKSTART_MASK 0xfff |
| 207 | #define HBLANKSTART_SHIFT 0 |
| 208 | #define HSYNCEND_MASK 0xfff |
| 209 | #define HSYNCEND_SHIFT 16 |
| 210 | #define HSYNCSTART_MASK 0xfff |
| 211 | #define HSYNCSTART_SHIFT 0 |
| 212 | #define VTOTAL_MASK 0xfff |
| 213 | #define VTOTAL_SHIFT 16 |
| 214 | #define VACTIVE_MASK 0x7ff |
| 215 | #define VACTIVE_SHIFT 0 |
| 216 | #define VBLANKEND_MASK 0xfff |
| 217 | #define VBLANKEND_SHIFT 16 |
| 218 | #define VBLANKSTART_MASK 0xfff |
| 219 | #define VBLANKSTART_SHIFT 0 |
| 220 | #define VSYNCEND_MASK 0xfff |
| 221 | #define VSYNCEND_SHIFT 16 |
| 222 | #define VSYNCSTART_MASK 0xfff |
| 223 | #define VSYNCSTART_SHIFT 0 |
| 224 | #define SRC_SIZE_HORIZ_MASK 0x7ff |
| 225 | #define SRC_SIZE_HORIZ_SHIFT 16 |
| 226 | #define SRC_SIZE_VERT_MASK 0x7ff |
| 227 | #define SRC_SIZE_VERT_SHIFT 0 |
| 228 | |
| 229 | #define ADPA 0x61100 |
| 230 | #define ADPA_DAC_ENABLE (1 << 31) |
| 231 | #define ADPA_DAC_DISABLE 0 |
| 232 | #define ADPA_PIPE_SELECT_SHIFT 30 |
| 233 | #define ADPA_USE_VGA_HVPOLARITY (1 << 15) |
| 234 | #define ADPA_SETS_HVPOLARITY 0 |
| 235 | #define ADPA_DPMS_CONTROL_MASK (0x3 << 10) |
| 236 | #define ADPA_DPMS_D0 (0x0 << 10) |
| 237 | #define ADPA_DPMS_D2 (0x1 << 10) |
| 238 | #define ADPA_DPMS_D1 (0x2 << 10) |
| 239 | #define ADPA_DPMS_D3 (0x3 << 10) |
| 240 | #define ADPA_VSYNC_ACTIVE_SHIFT 4 |
| 241 | #define ADPA_HSYNC_ACTIVE_SHIFT 3 |
| 242 | #define ADPA_SYNC_ACTIVE_MASK 1 |
| 243 | #define ADPA_SYNC_ACTIVE_HIGH 1 |
| 244 | #define ADPA_SYNC_ACTIVE_LOW 0 |
| 245 | |
| 246 | #define DVOA 0x61120 |
| 247 | #define DVOB 0x61140 |
| 248 | #define DVOC 0x61160 |
| 249 | #define LVDS 0x61180 |
| 250 | #define PORT_ENABLE (1 << 31) |
| 251 | #define PORT_PIPE_SELECT_SHIFT 30 |
| 252 | #define PORT_TV_FLAGS_MASK 0xFF |
| 253 | #define PORT_TV_FLAGS 0xC4 // ripped from my BIOS |
| 254 | // to understand and correct |
| 255 | |
| 256 | #define DVOA_SRCDIM 0x61124 |
| 257 | #define DVOB_SRCDIM 0x61144 |
| 258 | #define DVOC_SRCDIM 0x61164 |
| 259 | |
| 260 | #define PIPEACONF 0x70008 |
| 261 | #define PIPEBCONF 0x71008 |
| 262 | #define PIPECONF_ENABLE (1 << 31) |
| 263 | #define PIPECONF_DISABLE 0 |
| 264 | #define PIPECONF_DOUBLE_WIDE (1 << 30) |
| 265 | #define PIPECONF_SINGLE_WIDE 0 |
| 266 | #define PIPECONF_LOCKED (1 << 25) |
| 267 | #define PIPECONF_UNLOCKED 0 |
| 268 | #define PIPECONF_GAMMA (1 << 24) |
| 269 | #define PIPECONF_PALETTE 0 |
| 270 | |
| 271 | #define DISPARB 0x70030 |
| 272 | #define DISPARB_AEND_MASK 0x1ff |
| 273 | #define DISPARB_AEND_SHIFT 0 |
| 274 | #define DISPARB_BEND_MASK 0x3ff |
| 275 | #define DISPARB_BEND_SHIFT 9 |
| 276 | |
| 277 | /* Desktop HW cursor */ |
| 278 | #define CURSOR_CONTROL 0x70080 |
| 279 | #define CURSOR_ENABLE (1 << 31) |
| 280 | #define CURSOR_GAMMA_ENABLE (1 << 30) |
| 281 | #define CURSOR_STRIDE_MASK (0x3 << 28) |
| 282 | #define CURSOR_STRIDE_256 (0x0 << 28) |
| 283 | #define CURSOR_STRIDE_512 (0x1 << 28) |
| 284 | #define CURSOR_STRIDE_1K (0x2 << 28) |
| 285 | #define CURSOR_STRIDE_2K (0x3 << 28) |
| 286 | #define CURSOR_FORMAT_MASK (0x7 << 24) |
| 287 | #define CURSOR_FORMAT_2C (0x0 << 24) |
| 288 | #define CURSOR_FORMAT_3C (0x1 << 24) |
| 289 | #define CURSOR_FORMAT_4C (0x2 << 24) |
| 290 | #define CURSOR_FORMAT_ARGB (0x4 << 24) |
| 291 | #define CURSOR_FORMAT_XRGB (0x5 << 24) |
| 292 | |
| 293 | /* Mobile HW cursor (and i810) */ |
| 294 | #define CURSOR_A_CONTROL CURSOR_CONTROL |
| 295 | #define CURSOR_B_CONTROL 0x700c0 |
| 296 | #define CURSOR_MODE_MASK 0x27 |
| 297 | #define CURSOR_MODE_DISABLE 0 |
| 298 | #define CURSOR_MODE_64_3C 0x04 |
| 299 | #define CURSOR_MODE_64_4C_AX 0x05 |
| 300 | #define CURSOR_MODE_64_4C 0x06 |
| 301 | #define CURSOR_MODE_64_32B_AX 0x07 |
| 302 | #define CURSOR_MODE_64_ARGB_AX 0x27 |
| 303 | #define CURSOR_PIPE_SELECT_SHIFT 28 |
| 304 | #define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26) |
| 305 | #define CURSOR_MEM_TYPE_LOCAL (1 << 25) |
| 306 | |
| 307 | /* All platforms (desktop has no pipe B) */ |
| 308 | #define CURSOR_A_BASEADDR 0x70084 |
| 309 | #define CURSOR_B_BASEADDR 0x700c4 |
| 310 | #define CURSOR_BASE_MASK 0xffffff00 |
| 311 | |
| 312 | #define CURSOR_A_POSITION 0x70088 |
| 313 | #define CURSOR_B_POSITION 0x700c8 |
| 314 | #define CURSOR_POS_SIGN (1 << 15) |
| 315 | #define CURSOR_POS_MASK 0x7ff |
| 316 | #define CURSOR_X_SHIFT 0 |
| 317 | #define CURSOR_Y_SHIFT 16 |
| 318 | |
| 319 | #define CURSOR_A_PALETTE0 0x70090 |
| 320 | #define CURSOR_A_PALETTE1 0x70094 |
| 321 | #define CURSOR_A_PALETTE2 0x70098 |
| 322 | #define CURSOR_A_PALETTE3 0x7009c |
| 323 | #define CURSOR_B_PALETTE0 0x700d0 |
| 324 | #define CURSOR_B_PALETTE1 0x700d4 |
| 325 | #define CURSOR_B_PALETTE2 0x700d8 |
| 326 | #define CURSOR_B_PALETTE3 0x700dc |
| 327 | #define CURSOR_COLOR_MASK 0xff |
| 328 | #define CURSOR_RED_SHIFT 16 |
| 329 | #define CURSOR_GREEN_SHIFT 8 |
| 330 | #define CURSOR_BLUE_SHIFT 0 |
| 331 | #define CURSOR_PALETTE_MASK 0xffffff |
| 332 | |
| 333 | /* Desktop only */ |
| 334 | #define CURSOR_SIZE 0x700a0 |
| 335 | #define CURSOR_SIZE_MASK 0x3ff |
| 336 | #define CURSOR_SIZE_H_SHIFT 0 |
| 337 | #define CURSOR_SIZE_V_SHIFT 12 |
| 338 | |
| 339 | #define DSPACNTR 0x70180 |
| 340 | #define DSPBCNTR 0x71180 |
| 341 | #define DISPPLANE_PLANE_ENABLE (1 << 31) |
| 342 | #define DISPPLANE_PLANE_DISABLE 0 |
| 343 | #define DISPPLANE_GAMMA_ENABLE (1<<30) |
| 344 | #define DISPPLANE_GAMMA_DISABLE 0 |
| 345 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
| 346 | #define DISPPLANE_8BPP (0x2<<26) |
| 347 | #define DISPPLANE_15_16BPP (0x4<<26) |
| 348 | #define DISPPLANE_16BPP (0x5<<26) |
| 349 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) |
| 350 | #define DISPPLANE_32BPP (0x7<<26) |
| 351 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
| 352 | #define DISPPLANE_STEREO_DISABLE 0 |
| 353 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
| 354 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
| 355 | #define DISPPLANE_SRC_KEY_DISABLE 0 |
| 356 | #define DISPPLANE_LINE_DOUBLE (1<<20) |
| 357 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
| 358 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
| 359 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
| 360 | /* plane B only */ |
| 361 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
| 362 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
| 363 | #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 |
| 364 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY 1 |
| 365 | |
| 366 | #define DSPABASE 0x70184 |
| 367 | #define DSPASTRIDE 0x70188 |
| 368 | |
| 369 | #define DSPBBASE 0x71184 |
| 370 | #define DSPBSTRIDE 0x71188 |
| 371 | |
| 372 | #define VGACNTRL 0x71400 |
| 373 | #define VGA_DISABLE (1 << 31) |
| 374 | #define VGA_ENABLE 0 |
| 375 | #define VGA_PIPE_SELECT_SHIFT 29 |
| 376 | #define VGA_PALETTE_READ_SELECT 23 |
| 377 | #define VGA_PALETTE_A_WRITE_DISABLE (1 << 22) |
| 378 | #define VGA_PALETTE_B_WRITE_DISABLE (1 << 21) |
| 379 | #define VGA_LEGACY_PALETTE (1 << 20) |
| 380 | #define VGA_6BIT_DAC 0 |
| 381 | #define VGA_8BIT_DAC (1 << 20) |
| 382 | |
| 383 | #define ADD_ID 0x71408 |
| 384 | #define ADD_ID_MASK 0xff |
| 385 | |
| 386 | /* BIOS scratch area registers (830M and 845G). */ |
| 387 | #define SWF0 0x71410 |
| 388 | #define SWF1 0x71414 |
| 389 | #define SWF2 0x71418 |
| 390 | #define SWF3 0x7141c |
| 391 | #define SWF4 0x71420 |
| 392 | #define SWF5 0x71424 |
| 393 | #define SWF6 0x71428 |
| 394 | |
| 395 | /* BIOS scratch area registers (852GM, 855GM, 865G). */ |
| 396 | #define SWF00 0x70410 |
| 397 | #define SWF01 0x70414 |
| 398 | #define SWF02 0x70418 |
| 399 | #define SWF03 0x7041c |
| 400 | #define SWF04 0x70420 |
| 401 | #define SWF05 0x70424 |
| 402 | #define SWF06 0x70428 |
| 403 | |
| 404 | #define SWF10 SWF0 |
| 405 | #define SWF11 SWF1 |
| 406 | #define SWF12 SWF2 |
| 407 | #define SWF13 SWF3 |
| 408 | #define SWF14 SWF4 |
| 409 | #define SWF15 SWF5 |
| 410 | #define SWF16 SWF6 |
| 411 | |
| 412 | #define SWF30 0x72414 |
| 413 | #define SWF31 0x72418 |
| 414 | #define SWF32 0x7241c |
| 415 | |
| 416 | /* Memory Commands */ |
| 417 | #define MI_NOOP (0x00 << 23) |
| 418 | #define MI_NOOP_WRITE_ID (1 << 22) |
| 419 | #define MI_NOOP_ID_MASK ((1 << 22) - 1) |
| 420 | |
| 421 | #define MI_FLUSH (0x04 << 23) |
| 422 | #define MI_WRITE_DIRTY_STATE (1 << 4) |
| 423 | #define MI_END_SCENE (1 << 3) |
| 424 | #define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2) |
| 425 | #define MI_INVALIDATE_MAP_CACHE (1 << 0) |
| 426 | |
| 427 | #define MI_STORE_DWORD_IMM ((0x20 << 23) | 1) |
| 428 | |
| 429 | /* 2D Commands */ |
| 430 | #define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3) |
| 431 | #define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4) |
| 432 | #define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1) |
| 433 | #define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6) |
| 434 | #define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4) |
| 435 | #define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7) |
| 436 | #define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6) |
| 437 | #define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5) |
| 438 | #define TXT_IMM_BLT_CMD ((2 << 29) | (0x30 << 22) | 2) |
| 439 | #define SETUP_BLT_CMD ((2 << 29) | (0x00 << 22) | 6) |
| 440 | |
| 441 | #define DW_LENGTH_MASK 0xff |
| 442 | |
| 443 | #define WRITE_ALPHA (1 << 21) |
| 444 | #define WRITE_RGB (1 << 20) |
| 445 | #define VERT_SEED (3 << 8) |
| 446 | #define HORIZ_SEED (3 << 12) |
| 447 | |
| 448 | #define COLOR_DEPTH_8 (0 << 24) |
| 449 | #define COLOR_DEPTH_16 (1 << 24) |
| 450 | #define COLOR_DEPTH_32 (3 << 24) |
| 451 | |
| 452 | #define SRC_ROP_GXCOPY 0xcc |
| 453 | #define SRC_ROP_GXXOR 0x66 |
| 454 | |
| 455 | #define PAT_ROP_GXCOPY 0xf0 |
| 456 | #define PAT_ROP_GXXOR 0x5a |
| 457 | |
| 458 | #define PITCH_SHIFT 0 |
| 459 | #define ROP_SHIFT 16 |
| 460 | #define WIDTH_SHIFT 0 |
| 461 | #define HEIGHT_SHIFT 16 |
| 462 | |
| 463 | /* in bytes */ |
| 464 | #define MAX_MONO_IMM_SIZE 128 |
| 465 | |
| 466 | |
| 467 | /*** Macros ***/ |
| 468 | |
| 469 | /* I/O macros */ |
| 470 | #define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr))) |
Eric Hustvedt | 3ce6fb4 | 2006-06-20 14:36:41 -0400 | [diff] [blame^] | 471 | #define INREG16(addr) readw((u16 __iomem *)(dinfo->mmio_base + (addr))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 472 | #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr))) |
| 473 | #define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \ |
| 474 | (addr))) |
Eric Hustvedt | 3ce6fb4 | 2006-06-20 14:36:41 -0400 | [diff] [blame^] | 475 | #define OUTREG16(addr, val) writew((val),(u16 __iomem *)(dinfo->mmio_base + \ |
| 476 | (addr))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | #define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \ |
| 478 | (addr))) |
| 479 | |
| 480 | /* Ring buffer macros */ |
| 481 | #define OUT_RING(n) do { \ |
| 482 | writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\ |
| 483 | dinfo->ring_tail += 4; \ |
| 484 | dinfo->ring_tail &= dinfo->ring_tail_mask; \ |
| 485 | } while (0) |
| 486 | |
| 487 | #define START_RING(n) do { \ |
| 488 | if (dinfo->ring_space < (n) * 4) \ |
| 489 | wait_ring(dinfo,(n) * 4); \ |
| 490 | dinfo->ring_space -= (n) * 4; \ |
| 491 | } while (0) |
| 492 | |
| 493 | #define ADVANCE_RING() do { \ |
| 494 | OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \ |
| 495 | } while (0) |
| 496 | |
| 497 | #define DO_RING_IDLE() do { \ |
| 498 | u32 head, tail; \ |
| 499 | do { \ |
| 500 | head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \ |
| 501 | tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \ |
| 502 | udelay(10); \ |
| 503 | } while (head != tail); \ |
| 504 | } while (0) |
| 505 | |
| 506 | |
| 507 | /* function protoypes */ |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame] | 508 | extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, |
| 510 | int *stolen_size); |
| 511 | extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo); |
| 512 | extern const char *intelfbhw_dvo_to_string(int dvo); |
| 513 | extern int intelfbhw_validate_mode(struct intelfb_info *dinfo, |
| 514 | struct fb_var_screeninfo *var); |
| 515 | extern int intelfbhw_pan_display(struct fb_var_screeninfo *var, |
| 516 | struct fb_info *info); |
| 517 | extern void intelfbhw_do_blank(int blank, struct fb_info *info); |
| 518 | extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno, |
| 519 | unsigned red, unsigned green, unsigned blue, |
| 520 | unsigned transp); |
| 521 | extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo, |
| 522 | struct intelfb_hwstate *hw, int flag); |
| 523 | extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo, |
| 524 | struct intelfb_hwstate *hw); |
| 525 | extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo, |
| 526 | struct intelfb_hwstate *hw, |
| 527 | struct fb_var_screeninfo *var); |
| 528 | extern int intelfbhw_program_mode(struct intelfb_info *dinfo, |
| 529 | const struct intelfb_hwstate *hw, int blank); |
| 530 | extern void intelfbhw_do_sync(struct intelfb_info *dinfo); |
| 531 | extern void intelfbhw_2d_stop(struct intelfb_info *dinfo); |
| 532 | extern void intelfbhw_2d_start(struct intelfb_info *dinfo); |
| 533 | extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, |
| 534 | u32 w, u32 h, u32 color, u32 pitch, u32 bpp, |
| 535 | u32 rop); |
| 536 | extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury, |
| 537 | u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, |
| 538 | u32 bpp); |
| 539 | extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, |
| 540 | u32 w, u32 h, const u8* cdat, u32 x, u32 y, |
| 541 | u32 pitch, u32 bpp); |
| 542 | extern void intelfbhw_cursor_init(struct intelfb_info *dinfo); |
| 543 | extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo); |
| 544 | extern void intelfbhw_cursor_show(struct intelfb_info *dinfo); |
| 545 | extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y); |
| 546 | extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, |
| 547 | u32 fg); |
| 548 | extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, |
| 549 | int height, u8 *data); |
| 550 | extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo); |
| 551 | |
| 552 | #endif /* _INTELFBHW_H */ |