Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994 |
| 3 | * |
| 4 | * Copyright 2010 Wolfson Microelectronics PLC. |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/i2c.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/mfd/core.h> |
| 20 | #include <linux/interrupt.h> |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 21 | #include <linux/regmap.h> |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 22 | |
| 23 | #include <linux/mfd/wm8994/core.h> |
| 24 | #include <linux/mfd/wm8994/registers.h> |
| 25 | |
| 26 | #include <linux/delay.h> |
| 27 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 28 | static struct regmap_irq wm8994_irqs[] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 29 | [WM8994_IRQ_TEMP_SHUT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 30 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 31 | .mask = WM8994_TEMP_SHUT_EINT, |
| 32 | }, |
| 33 | [WM8994_IRQ_MIC1_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 34 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 35 | .mask = WM8994_MIC1_DET_EINT, |
| 36 | }, |
| 37 | [WM8994_IRQ_MIC1_SHRT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 38 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 39 | .mask = WM8994_MIC1_SHRT_EINT, |
| 40 | }, |
| 41 | [WM8994_IRQ_MIC2_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 42 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 43 | .mask = WM8994_MIC2_DET_EINT, |
| 44 | }, |
| 45 | [WM8994_IRQ_MIC2_SHRT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 46 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 47 | .mask = WM8994_MIC2_SHRT_EINT, |
| 48 | }, |
| 49 | [WM8994_IRQ_FLL1_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 50 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 51 | .mask = WM8994_FLL1_LOCK_EINT, |
| 52 | }, |
| 53 | [WM8994_IRQ_FLL2_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 54 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 55 | .mask = WM8994_FLL2_LOCK_EINT, |
| 56 | }, |
| 57 | [WM8994_IRQ_SRC1_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 58 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 59 | .mask = WM8994_SRC1_LOCK_EINT, |
| 60 | }, |
| 61 | [WM8994_IRQ_SRC2_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 62 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 63 | .mask = WM8994_SRC2_LOCK_EINT, |
| 64 | }, |
| 65 | [WM8994_IRQ_AIF1DRC1_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 66 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 67 | .mask = WM8994_AIF1DRC1_SIG_DET, |
| 68 | }, |
| 69 | [WM8994_IRQ_AIF1DRC2_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 70 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 71 | .mask = WM8994_AIF1DRC2_SIG_DET_EINT, |
| 72 | }, |
| 73 | [WM8994_IRQ_AIF2DRC_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 74 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 75 | .mask = WM8994_AIF2DRC_SIG_DET_EINT, |
| 76 | }, |
| 77 | [WM8994_IRQ_FIFOS_ERR] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 78 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 79 | .mask = WM8994_FIFOS_ERR_EINT, |
| 80 | }, |
| 81 | [WM8994_IRQ_WSEQ_DONE] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 82 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 83 | .mask = WM8994_WSEQ_DONE_EINT, |
| 84 | }, |
| 85 | [WM8994_IRQ_DCS_DONE] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 86 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 87 | .mask = WM8994_DCS_DONE_EINT, |
| 88 | }, |
| 89 | [WM8994_IRQ_TEMP_WARN] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 90 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 91 | .mask = WM8994_TEMP_WARN_EINT, |
| 92 | }, |
| 93 | [WM8994_IRQ_GPIO(1)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 94 | .mask = WM8994_GP1_EINT, |
| 95 | }, |
| 96 | [WM8994_IRQ_GPIO(2)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 97 | .mask = WM8994_GP2_EINT, |
| 98 | }, |
| 99 | [WM8994_IRQ_GPIO(3)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 100 | .mask = WM8994_GP3_EINT, |
| 101 | }, |
| 102 | [WM8994_IRQ_GPIO(4)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 103 | .mask = WM8994_GP4_EINT, |
| 104 | }, |
| 105 | [WM8994_IRQ_GPIO(5)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 106 | .mask = WM8994_GP5_EINT, |
| 107 | }, |
| 108 | [WM8994_IRQ_GPIO(6)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 109 | .mask = WM8994_GP6_EINT, |
| 110 | }, |
| 111 | [WM8994_IRQ_GPIO(7)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 112 | .mask = WM8994_GP7_EINT, |
| 113 | }, |
| 114 | [WM8994_IRQ_GPIO(8)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 115 | .mask = WM8994_GP8_EINT, |
| 116 | }, |
| 117 | [WM8994_IRQ_GPIO(9)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 118 | .mask = WM8994_GP8_EINT, |
| 119 | }, |
| 120 | [WM8994_IRQ_GPIO(10)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 121 | .mask = WM8994_GP10_EINT, |
| 122 | }, |
| 123 | [WM8994_IRQ_GPIO(11)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 124 | .mask = WM8994_GP11_EINT, |
| 125 | }, |
| 126 | }; |
| 127 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 128 | static struct regmap_irq_chip wm8994_irq_chip = { |
| 129 | .name = "wm8994", |
| 130 | .irqs = wm8994_irqs, |
| 131 | .num_irqs = ARRAY_SIZE(wm8994_irqs), |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 132 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 133 | .num_regs = 2, |
| 134 | .status_base = WM8994_INTERRUPT_STATUS_1, |
| 135 | .mask_base = WM8994_INTERRUPT_STATUS_1_MASK, |
| 136 | .ack_base = WM8994_INTERRUPT_STATUS_1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 137 | }; |
| 138 | |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 139 | int wm8994_irq_init(struct wm8994 *wm8994) |
| 140 | { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 141 | int ret; |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 142 | |
| 143 | if (!wm8994->irq) { |
| 144 | dev_warn(wm8994->dev, |
| 145 | "No interrupt specified, no interrupts\n"); |
| 146 | wm8994->irq_base = 0; |
| 147 | return 0; |
| 148 | } |
| 149 | |
| 150 | if (!wm8994->irq_base) { |
| 151 | dev_err(wm8994->dev, |
| 152 | "No interrupt base specified, no interrupts\n"); |
| 153 | return 0; |
| 154 | } |
| 155 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 156 | ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, |
| 157 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
| 158 | wm8994->irq_base, &wm8994_irq_chip, |
| 159 | &wm8994->irq_data); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 160 | if (ret != 0) { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 161 | dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 162 | return ret; |
| 163 | } |
| 164 | |
| 165 | /* Enable top level interrupt if it was masked */ |
| 166 | wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0); |
| 167 | |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | void wm8994_irq_exit(struct wm8994 *wm8994) |
| 172 | { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 173 | regmap_del_irq_chip(wm8994->irq, wm8994->irq_data); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 174 | } |