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Russell King5e742ad2005-08-18 10:08:15 +01001/*
2 * linux/drivers/mfd/mcp-sa11x0.c
3 *
4 * Copyright (C) 2001-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * SA11x0 MCP (Multimedia Communications Port) driver.
11 *
12 * MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
Russell King45c7f752012-01-20 23:09:42 +000016#include <linux/io.h>
Russell King5e742ad2005-08-18 10:08:15 +010017#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/spinlock.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010021#include <linux/platform_device.h>
Thomas Kunzec8602ed2009-02-10 14:54:57 +010022#include <linux/mfd/mcp.h>
Russell King5e742ad2005-08-18 10:08:15 +010023
Russell Kinga09e64f2008-08-05 16:14:15 +010024#include <mach/hardware.h>
Russell King5e742ad2005-08-18 10:08:15 +010025#include <asm/mach-types.h>
26#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/mcp.h>
Russell King5e742ad2005-08-18 10:08:15 +010028
Russell King216f63c2012-01-20 17:37:21 +000029#include <mach/assabet.h>
30
Russell Kingc4592ce2012-01-20 22:30:15 +000031#define DRIVER_NAME "sa11x0-mcp"
Russell King5e742ad2005-08-18 10:08:15 +010032
33struct mcp_sa11x0 {
Russell King45c7f752012-01-20 23:09:42 +000034 void __iomem *base0;
35 void __iomem *base1;
36 u32 mccr0;
37 u32 mccr1;
Russell King5e742ad2005-08-18 10:08:15 +010038};
39
Russell King45c7f752012-01-20 23:09:42 +000040/* Register offsets */
41#define MCCR0(m) ((m)->base0 + 0x00)
42#define MCDR0(m) ((m)->base0 + 0x08)
43#define MCDR1(m) ((m)->base0 + 0x0c)
44#define MCDR2(m) ((m)->base0 + 0x10)
45#define MCSR(m) ((m)->base0 + 0x18)
46#define MCCR1(m) ((m)->base1 + 0x00)
47
Russell King5e742ad2005-08-18 10:08:15 +010048#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
49
50static void
51mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
52{
Russell King45c7f752012-01-20 23:09:42 +000053 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010054
55 divisor /= 32;
56
Russell King45c7f752012-01-20 23:09:42 +000057 m->mccr0 &= ~0x00007f00;
58 m->mccr0 |= divisor << 8;
59 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +010060}
61
62static void
63mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
64{
Russell King45c7f752012-01-20 23:09:42 +000065 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010066
67 divisor /= 32;
68
Russell King45c7f752012-01-20 23:09:42 +000069 m->mccr0 &= ~0x0000007f;
70 m->mccr0 |= divisor;
71 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +010072}
73
74/*
75 * Write data to the device. The bit should be set after 3 subframe
76 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
77 * We really should try doing something more productive while we
78 * wait.
79 */
80static void
81mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
82{
Russell King45c7f752012-01-20 23:09:42 +000083 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010084 int ret = -ETIME;
85 int i;
86
Russell King45c7f752012-01-20 23:09:42 +000087 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));
Russell King5e742ad2005-08-18 10:08:15 +010088
89 for (i = 0; i < 2; i++) {
90 udelay(mcp->rw_timeout);
Russell King45c7f752012-01-20 23:09:42 +000091 if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
Russell King5e742ad2005-08-18 10:08:15 +010092 ret = 0;
93 break;
94 }
95 }
96
97 if (ret < 0)
98 printk(KERN_WARNING "mcp: write timed out\n");
99}
100
101/*
102 * Read data from the device. The bit should be set after 3 subframe
103 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
104 * We really should try doing something more productive while we
105 * wait.
106 */
107static unsigned int
108mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
109{
Russell King45c7f752012-01-20 23:09:42 +0000110 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100111 int ret = -ETIME;
112 int i;
113
Russell King45c7f752012-01-20 23:09:42 +0000114 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
Russell King5e742ad2005-08-18 10:08:15 +0100115
116 for (i = 0; i < 2; i++) {
117 udelay(mcp->rw_timeout);
Russell King45c7f752012-01-20 23:09:42 +0000118 if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
119 ret = readl_relaxed(MCDR2(m)) & 0xffff;
Russell King5e742ad2005-08-18 10:08:15 +0100120 break;
121 }
122 }
123
124 if (ret < 0)
125 printk(KERN_WARNING "mcp: read timed out\n");
126
127 return ret;
128}
129
130static void mcp_sa11x0_enable(struct mcp *mcp)
131{
Russell King45c7f752012-01-20 23:09:42 +0000132 struct mcp_sa11x0 *m = priv(mcp);
133
134 writel(-1, MCSR(m));
135 m->mccr0 |= MCCR0_MCE;
136 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100137}
138
139static void mcp_sa11x0_disable(struct mcp *mcp)
140{
Russell King45c7f752012-01-20 23:09:42 +0000141 struct mcp_sa11x0 *m = priv(mcp);
142
143 m->mccr0 &= ~MCCR0_MCE;
144 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100145}
146
147/*
148 * Our methods.
149 */
150static struct mcp_ops mcp_sa11x0 = {
151 .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
152 .set_audio_divisor = mcp_sa11x0_set_audio_divisor,
153 .reg_write = mcp_sa11x0_write,
154 .reg_read = mcp_sa11x0_read,
155 .enable = mcp_sa11x0_enable,
156 .disable = mcp_sa11x0_disable,
157};
158
Russell King45c7f752012-01-20 23:09:42 +0000159static int mcp_sa11x0_probe(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100160{
Russell King45c7f752012-01-20 23:09:42 +0000161 struct mcp_plat_data *data = dev->dev.platform_data;
162 struct resource *mem0, *mem1;
163 struct mcp_sa11x0 *m;
Russell King5e742ad2005-08-18 10:08:15 +0100164 struct mcp *mcp;
165 int ret;
166
Russell King323cdfc2005-08-18 10:10:46 +0100167 if (!data)
Russell King5e742ad2005-08-18 10:08:15 +0100168 return -ENODEV;
169
Russell King45c7f752012-01-20 23:09:42 +0000170 mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
171 mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
172 if (!mem0 || !mem1)
173 return -ENXIO;
Russell King5e742ad2005-08-18 10:08:15 +0100174
Russell King45c7f752012-01-20 23:09:42 +0000175 if (!request_mem_region(mem0->start, resource_size(mem0),
176 DRIVER_NAME)) {
177 ret = -EBUSY;
178 goto err_mem0;
179 }
180
181 if (!request_mem_region(mem1->start, resource_size(mem1),
182 DRIVER_NAME)) {
183 ret = -EBUSY;
184 goto err_mem1;
185 }
186
187 mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
Russell King5e742ad2005-08-18 10:08:15 +0100188 if (!mcp) {
189 ret = -ENOMEM;
Russell King45c7f752012-01-20 23:09:42 +0000190 goto err_alloc;
Russell King5e742ad2005-08-18 10:08:15 +0100191 }
192
193 mcp->owner = THIS_MODULE;
194 mcp->ops = &mcp_sa11x0;
Russell King323cdfc2005-08-18 10:10:46 +0100195 mcp->sclk_rate = data->sclk_rate;
Russell King65f2e752012-01-20 17:38:58 +0000196 mcp->gpio_base = data->gpio_base;
Russell King5e742ad2005-08-18 10:08:15 +0100197
Russell King45c7f752012-01-20 23:09:42 +0000198 m = priv(mcp);
199 m->mccr0 = data->mccr0 | 0x7f7f;
200 m->mccr1 = data->mccr1;
201
202 m->base0 = ioremap(mem0->start, resource_size(mem0));
203 m->base1 = ioremap(mem1->start, resource_size(mem1));
204 if (!m->base0 || !m->base1) {
205 ret = -ENOMEM;
206 goto err_ioremap;
207 }
208
209 platform_set_drvdata(dev, mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100210
Russell King216f63c2012-01-20 17:37:21 +0000211 if (machine_is_assabet()) {
212 ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
213 }
214
215 /*
Russell King323cdfc2005-08-18 10:10:46 +0100216 * Initialise device. Note that we initially
217 * set the sampling rate to minimum.
218 */
Russell King45c7f752012-01-20 23:09:42 +0000219 writel_relaxed(-1, MCSR(m));
220 writel_relaxed(m->mccr1, MCCR1(m));
221 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100222
223 /*
224 * Calculate the read/write timeout (us) from the bit clock
225 * rate. This is the period for 3 64-bit frames. Always
226 * round this time up.
227 */
228 mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
229 mcp->sclk_rate;
230
Russell King30816ac2012-01-20 22:51:07 +0000231 ret = mcp_host_add(mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100232 if (ret == 0)
Russell King45c7f752012-01-20 23:09:42 +0000233 return 0;
Russell King5e742ad2005-08-18 10:08:15 +0100234
Russell King45c7f752012-01-20 23:09:42 +0000235 platform_set_drvdata(dev, NULL);
236
237 err_ioremap:
238 iounmap(m->base1);
239 iounmap(m->base0);
Russell King30816ac2012-01-20 22:51:07 +0000240 mcp_host_free(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000241 err_alloc:
242 release_mem_region(mem1->start, resource_size(mem1));
243 err_mem1:
244 release_mem_region(mem0->start, resource_size(mem0));
245 err_mem0:
Russell King5e742ad2005-08-18 10:08:15 +0100246 return ret;
247}
248
Russell King216f63c2012-01-20 17:37:21 +0000249static int mcp_sa11x0_remove(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100250{
Russell King216f63c2012-01-20 17:37:21 +0000251 struct mcp *mcp = platform_get_drvdata(dev);
Russell King45c7f752012-01-20 23:09:42 +0000252 struct mcp_sa11x0 *m = priv(mcp);
253 struct resource *mem0, *mem1;
254
255 mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
256 mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
Russell King5e742ad2005-08-18 10:08:15 +0100257
Russell King216f63c2012-01-20 17:37:21 +0000258 platform_set_drvdata(dev, NULL);
Russell King30816ac2012-01-20 22:51:07 +0000259 mcp_host_del(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000260 iounmap(m->base1);
261 iounmap(m->base0);
Russell King30816ac2012-01-20 22:51:07 +0000262 mcp_host_free(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000263 release_mem_region(mem1->start, resource_size(mem1));
264 release_mem_region(mem0->start, resource_size(mem0));
Russell King5e742ad2005-08-18 10:08:15 +0100265
266 return 0;
267}
268
Russell King3ae5eae2005-11-09 22:32:44 +0000269static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
Russell King5e742ad2005-08-18 10:08:15 +0100270{
Russell King45c7f752012-01-20 23:09:42 +0000271 struct mcp_sa11x0 *m = priv(platform_get_drvdata(dev));
Russell King5e742ad2005-08-18 10:08:15 +0100272
Russell King45c7f752012-01-20 23:09:42 +0000273 writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
Russell King9480e302005-10-28 09:52:56 -0700274
Russell King5e742ad2005-08-18 10:08:15 +0100275 return 0;
276}
277
Russell King3ae5eae2005-11-09 22:32:44 +0000278static int mcp_sa11x0_resume(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100279{
Russell King45c7f752012-01-20 23:09:42 +0000280 struct mcp_sa11x0 *m = priv(platform_get_drvdata(dev));
Russell King5e742ad2005-08-18 10:08:15 +0100281
Russell King45c7f752012-01-20 23:09:42 +0000282 writel_relaxed(m->mccr1, MCCR1(m));
283 writel_relaxed(m->mccr0, MCCR0(m));
Russell King9480e302005-10-28 09:52:56 -0700284
Russell King5e742ad2005-08-18 10:08:15 +0100285 return 0;
286}
287
Russell King3ae5eae2005-11-09 22:32:44 +0000288static struct platform_driver mcp_sa11x0_driver = {
Russell King5e742ad2005-08-18 10:08:15 +0100289 .probe = mcp_sa11x0_probe,
290 .remove = mcp_sa11x0_remove,
291 .suspend = mcp_sa11x0_suspend,
292 .resume = mcp_sa11x0_resume,
Russell King3ae5eae2005-11-09 22:32:44 +0000293 .driver = {
Russell Kingc4592ce2012-01-20 22:30:15 +0000294 .name = DRIVER_NAME,
295 .owner = THIS_MODULE,
Russell King3ae5eae2005-11-09 22:32:44 +0000296 },
Russell King5e742ad2005-08-18 10:08:15 +0100297};
298
299/*
300 * This needs re-working
301 */
Mark Brown65349d62011-11-23 22:58:34 +0000302module_platform_driver(mcp_sa11x0_driver);
Russell King5e742ad2005-08-18 10:08:15 +0100303
Russell Kingc4592ce2012-01-20 22:30:15 +0000304MODULE_ALIAS("platform:" DRIVER_NAME);
Russell King5e742ad2005-08-18 10:08:15 +0100305MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
306MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
307MODULE_LICENSE("GPL");