Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/timer-gp.c |
| 3 | * |
| 4 | * OMAP2 GP timer support. |
| 5 | * |
| 6 | * Copyright (C) 2005 Nokia Corporation |
| 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * Juha Yrjölä <juha.yrjola@nokia.com> |
| 9 | * |
| 10 | * Some parts based off of TI's 24xx code: |
| 11 | * |
| 12 | * Copyright (C) 2004 Texas Instruments, Inc. |
| 13 | * |
| 14 | * Roughly modelled after the OMAP1 MPU timer code. |
| 15 | * |
| 16 | * This file is subject to the terms and conditions of the GNU General Public |
| 17 | * License. See the file "COPYING" in the main directory of this archive |
| 18 | * for more details. |
| 19 | */ |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/time.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/err.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 24 | #include <linux/clk.h> |
| 25 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 26 | #include <asm/mach/time.h> |
| 27 | #include <asm/delay.h> |
| 28 | #include <asm/io.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 29 | |
| 30 | #define OMAP2_GP_TIMER1_BASE 0x48028000 |
| 31 | #define OMAP2_GP_TIMER2_BASE 0x4802a000 |
| 32 | #define OMAP2_GP_TIMER3_BASE 0x48078000 |
| 33 | #define OMAP2_GP_TIMER4_BASE 0x4807a000 |
| 34 | |
| 35 | #define GP_TIMER_TIDR 0x00 |
| 36 | #define GP_TIMER_TISR 0x18 |
| 37 | #define GP_TIMER_TIER 0x1c |
| 38 | #define GP_TIMER_TCLR 0x24 |
| 39 | #define GP_TIMER_TCRR 0x28 |
| 40 | #define GP_TIMER_TLDR 0x2c |
| 41 | #define GP_TIMER_TSICR 0x40 |
| 42 | |
| 43 | #define OS_TIMER_NR 1 /* GP timer 2 */ |
| 44 | |
| 45 | static unsigned long timer_base[] = { |
| 46 | IO_ADDRESS(OMAP2_GP_TIMER1_BASE), |
| 47 | IO_ADDRESS(OMAP2_GP_TIMER2_BASE), |
| 48 | IO_ADDRESS(OMAP2_GP_TIMER3_BASE), |
| 49 | IO_ADDRESS(OMAP2_GP_TIMER4_BASE), |
| 50 | }; |
| 51 | |
| 52 | static inline unsigned int timer_read_reg(int nr, unsigned int reg) |
| 53 | { |
| 54 | return __raw_readl(timer_base[nr] + reg); |
| 55 | } |
| 56 | |
| 57 | static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val) |
| 58 | { |
| 59 | __raw_writel(val, timer_base[nr] + reg); |
| 60 | } |
| 61 | |
| 62 | /* Note that we always enable the clock prescale divider bit */ |
| 63 | static inline void omap2_gp_timer_start(int nr, unsigned long load_val) |
| 64 | { |
| 65 | unsigned int tmp; |
| 66 | |
| 67 | tmp = 0xffffffff - load_val; |
| 68 | |
| 69 | timer_write_reg(nr, GP_TIMER_TLDR, tmp); |
| 70 | timer_write_reg(nr, GP_TIMER_TCRR, tmp); |
| 71 | timer_write_reg(nr, GP_TIMER_TIER, 1 << 1); |
| 72 | timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1); |
| 73 | } |
| 74 | |
| 75 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id, |
| 76 | struct pt_regs *regs) |
| 77 | { |
| 78 | write_seqlock(&xtime_lock); |
| 79 | |
| 80 | timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1); |
| 81 | timer_tick(regs); |
| 82 | |
| 83 | write_sequnlock(&xtime_lock); |
| 84 | |
| 85 | return IRQ_HANDLED; |
| 86 | } |
| 87 | |
| 88 | static struct irqaction omap2_gp_timer_irq = { |
| 89 | .name = "gp timer", |
| 90 | .flags = SA_INTERRUPT, |
| 91 | .handler = omap2_gp_timer_interrupt, |
| 92 | }; |
| 93 | |
| 94 | static void __init omap2_gp_timer_init(void) |
| 95 | { |
| 96 | struct clk * sys_ck; |
| 97 | u32 tick_period = 120000; |
| 98 | u32 l; |
| 99 | |
| 100 | /* Reset clock and prescale value */ |
| 101 | timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0); |
| 102 | |
| 103 | sys_ck = clk_get(NULL, "sys_ck"); |
| 104 | if (IS_ERR(sys_ck)) |
| 105 | printk(KERN_ERR "Could not get sys_ck\n"); |
| 106 | else { |
| 107 | clk_use(sys_ck); |
| 108 | tick_period = clk_get_rate(sys_ck) / 100; |
| 109 | clk_put(sys_ck); |
| 110 | } |
| 111 | |
| 112 | tick_period /= 2; /* Minimum prescale divider is 2 */ |
| 113 | tick_period -= 1; |
| 114 | |
| 115 | l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR); |
| 116 | printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n", |
| 117 | (l >> 4) & 0x0f, l & 0x0f); |
| 118 | |
| 119 | setup_irq(38, &omap2_gp_timer_irq); |
| 120 | |
| 121 | omap2_gp_timer_start(OS_TIMER_NR, tick_period); |
| 122 | } |
| 123 | |
| 124 | struct sys_timer omap_timer = { |
| 125 | .init = omap2_gp_timer_init, |
| 126 | }; |
| 127 | |