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Arnd Bergmann67207b92005-11-15 15:53:48 -05001/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
Arnd Bergmann88ced032005-12-16 22:43:46 +010025#ifdef __KERNEL__
26
Arnd Bergmann67207b92005-11-15 15:53:48 -050027#include <linux/workqueue.h>
Jeremy Kerr1d640932006-06-19 20:33:19 +020028#include <linux/sysdev.h>
Arnd Bergmann67207b92005-11-15 15:53:48 -050029
Arnd Bergmannaeb01372006-01-04 20:31:32 +010030#define LS_SIZE (256 * 1024)
Mark Nutter5473af02005-11-15 15:53:49 -050031#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flags indicating progress during context switch. */
Arnd Bergmann8837d922006-01-04 20:31:28 +0100102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
Arnd Bergmann67207b92005-11-15 15:53:48 -0500104
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500105struct spu_context;
106struct spu_runqueue;
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900107struct device_node;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500108
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000109enum spu_utilization_state {
110 SPU_UTIL_SYSTEM,
111 SPU_UTIL_USER,
112 SPU_UTIL_IOWAIT,
113 SPU_UTIL_IDLE,
114 SPU_UTIL_MAX
115};
116
Arnd Bergmann67207b92005-11-15 15:53:48 -0500117struct spu {
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000118 const char *name;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500119 unsigned long local_store_phys;
120 u8 *local_store;
Mark Nutter6df10a82006-03-23 00:00:12 +0100121 unsigned long problem_phys;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500122 struct spu_problem __iomem *problem;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500123 struct spu_priv2 __iomem *priv2;
124 struct list_head list;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500125 struct list_head sched_list;
Christian Kraffte570beb2006-10-24 18:31:23 +0200126 struct list_head full_list;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500127 int number;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000128 unsigned int irqs[3];
Arnd Bergmann67207b92005-11-15 15:53:48 -0500129 u32 node;
Mark Nutter5473af02005-11-15 15:53:49 -0500130 u64 flags;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500131 u64 dar;
132 u64 dsisr;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500133 size_t ls_size;
134 unsigned int slb_replace;
135 struct mm_struct *mm;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500136 struct spu_context *ctx;
137 struct spu_runqueue *rq;
Arnd Bergmann2a911f02005-12-05 22:52:26 -0500138 unsigned long long timestamp;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500139 pid_t pid;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500140 int class_0_pending;
141 spinlock_t register_lock;
142
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500143 void (* wbox_callback)(struct spu *spu);
144 void (* ibox_callback)(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500145 void (* stop_callback)(struct spu *spu);
Arnd Bergmanna33a7d72006-03-23 00:00:11 +0100146 void (* mfc_callback)(struct spu *spu);
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200147 void (* dma_callback)(struct spu *spu, int type);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500148
149 char irq_c0[8];
150 char irq_c1[8];
151 char irq_c2[8];
Jeremy Kerr1d640932006-06-19 20:33:19 +0200152
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900153 u64 spe_id;
154
Geoff Levande28b0032006-11-23 00:46:49 +0100155 void* pdata; /* platform private data */
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900156
157 /* of based platforms only */
158 struct device_node *devnode;
159
160 /* native only */
161 struct spu_priv1 __iomem *priv1;
162
163 /* beat only */
164 u64 shadow_int_mask_RW[3];
165
Jeremy Kerr1d640932006-06-19 20:33:19 +0200166 struct sys_device sysdev;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000167
168 struct {
169 /* protected by interrupt reentrancy */
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000170 enum spu_utilization_state utilization_state;
171 unsigned long tstamp; /* time of last ctx switch */
172 unsigned long times[SPU_UTIL_MAX];
173 unsigned long long vol_ctx_switch;
174 unsigned long long invol_ctx_switch;
175 unsigned long long min_flt;
176 unsigned long long maj_flt;
177 unsigned long long hash_flt;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000178 unsigned long long slb_flt;
179 unsigned long long class2_intr;
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000180 unsigned long long libassist;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000181 } stats;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500182};
183
184struct spu *spu_alloc(void);
Mark Nuttera68cf982006-10-04 17:26:12 +0200185struct spu *spu_alloc_node(int node);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500186void spu_free(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500187int spu_irq_class_0_bottom(struct spu *spu);
188int spu_irq_class_1_bottom(struct spu *spu);
Arnd Bergmann2fb9d202006-01-05 14:05:29 +0000189void spu_irq_setaffinity(struct spu *spu, int cpu);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500190
Andre Detsch8d2655e2007-07-20 21:39:27 +0200191#ifdef CONFIG_KEXEC
192void crash_register_spus(struct list_head *list);
193#else
194static inline void crash_register_spus(struct list_head *list)
195{
196}
197#endif
198
Benjamin Herrenschmidt94b2a432007-03-10 00:05:37 +0100199extern void spu_invalidate_slbs(struct spu *spu);
200extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
201
202/* Calls from the memory management to the SPU */
203struct mm_struct;
204extern void spu_flush_all_slbs(struct mm_struct *mm);
205
Arnd Bergmann2dd14932006-03-23 00:00:09 +0100206/* system callbacks from the SPU */
207struct spu_syscall_block {
208 u64 nr_ret;
209 u64 parm[6];
210};
211extern long spu_sys_callback(struct spu_syscall_block *s);
212
213/* syscalls implemented in spufs */
Arnd Bergmannf1fa16e2006-12-19 15:32:42 +0100214struct file;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500215extern struct spufs_calls {
216 asmlinkage long (*create_thread)(const char __user *name,
217 unsigned int flags, mode_t mode);
218 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
219 __u32 __user *ustatus);
220 struct module *owner;
221} spufs_calls;
222
Dwayne Grant McConnellbf1ab972006-11-23 00:46:37 +0100223/* coredump calls implemented in spufs */
224struct spu_coredump_calls {
225 asmlinkage int (*arch_notes_size)(void);
226 asmlinkage void (*arch_write_notes)(struct file *file);
227 struct module *owner;
228};
229
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200230/* return status from spu_run, same as in libspe */
231#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
232#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
233#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
234#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
235#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
236
237/*
238 * Flags for sys_spu_create.
239 */
240#define SPU_CREATE_EVENTS_ENABLED 0x0001
Arnd Bergmann62632032006-10-04 17:26:15 +0200241#define SPU_CREATE_GANG 0x0002
Mark Nutter5737edd2006-10-24 18:31:16 +0200242#define SPU_CREATE_NOSCHED 0x0004
243#define SPU_CREATE_ISOLATE 0x0008
Arnd Bergmann62632032006-10-04 17:26:15 +0200244
Mark Nutter5737edd2006-10-24 18:31:16 +0200245#define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */
Arnd Bergmann62632032006-10-04 17:26:15 +0200246
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200247
Arnd Bergmann67207b92005-11-15 15:53:48 -0500248#ifdef CONFIG_SPU_FS_MODULE
249int register_spu_syscalls(struct spufs_calls *calls);
250void unregister_spu_syscalls(struct spufs_calls *calls);
251#else
252static inline int register_spu_syscalls(struct spufs_calls *calls)
253{
254 return 0;
255}
256static inline void unregister_spu_syscalls(struct spufs_calls *calls)
257{
258}
259#endif /* MODULE */
260
Dwayne Grant McConnellbf1ab972006-11-23 00:46:37 +0100261int register_arch_coredump_calls(struct spu_coredump_calls *calls);
262void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
263
Christian Kraffte570beb2006-10-24 18:31:23 +0200264int spu_add_sysdev_attr(struct sysdev_attribute *attr);
265void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
266
267int spu_add_sysdev_attr_group(struct attribute_group *attrs);
268void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
269
Arnd Bergmann67207b92005-11-15 15:53:48 -0500270
271/*
Arnd Bergmann86767272006-10-04 17:26:21 +0200272 * Notifier blocks:
273 *
274 * oprofile can get notified when a context switch is performed
275 * on an spe. The notifer function that gets called is passed
276 * a pointer to the SPU structure as well as the object-id that
277 * identifies the binary running on that SPU now.
278 *
279 * For a context save, the object-id that is passed is zero,
280 * identifying that the kernel will run from that moment on.
281 *
282 * For a context restore, the object-id is the value written
283 * to object-id spufs file from user space and the notifer
284 * function can assume that spu->ctx is valid.
285 */
Arnd Bergmannf1fa16e2006-12-19 15:32:42 +0100286struct notifier_block;
Arnd Bergmann86767272006-10-04 17:26:21 +0200287int spu_switch_event_register(struct notifier_block * n);
288int spu_switch_event_unregister(struct notifier_block * n);
289
290/*
Arnd Bergmann67207b92005-11-15 15:53:48 -0500291 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
292 */
293
294union mfc_tag_size_class_cmd {
295 struct {
296 u16 mfc_size;
297 u16 mfc_tag;
298 u8 pad;
299 u8 mfc_rclassid;
300 u16 mfc_cmd;
301 } u;
302 struct {
303 u32 mfc_size_tag32;
304 u32 mfc_class_cmd32;
305 } by32;
306 u64 all64;
307};
308
309struct mfc_cq_sr {
310 u64 mfc_cq_data0_RW;
311 u64 mfc_cq_data1_RW;
312 u64 mfc_cq_data2_RW;
313 u64 mfc_cq_data3_RW;
314};
315
316struct spu_problem {
317#define MS_SYNC_PENDING 1L
318 u64 spc_mssync_RW; /* 0x0000 */
319 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
320
321 /* DMA Area */
322 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
323 u32 mfc_lsa_W; /* 0x3004 */
324 u64 mfc_ea_W; /* 0x3008 */
325 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
326 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
327 u32 dma_qstatus_R; /* 0x3104 */
328 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
329 u32 dma_querytype_RW; /* 0x3204 */
330 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
331 u32 dma_querymask_RW; /* 0x321c */
332 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
333 u32 dma_tagstatus_R; /* 0x322c */
334#define DMA_TAGSTATUS_INTR_ANY 1u
335#define DMA_TAGSTATUS_INTR_ALL 2u
336 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
337
338 /* SPU Control Area */
339 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
340 u32 pu_mb_R; /* 0x4004 */
341 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
342 u32 spu_mb_W; /* 0x400c */
343 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
344 u32 mb_stat_R; /* 0x4014 */
345 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
346 u32 spu_runcntl_RW; /* 0x401c */
347#define SPU_RUNCNTL_STOP 0L
348#define SPU_RUNCNTL_RUNNABLE 1L
Mark Nutter5737edd2006-10-24 18:31:16 +0200349#define SPU_RUNCNTL_ISOLATE 2L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500350 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
351 u32 spu_status_R; /* 0x4024 */
352#define SPU_STOP_STATUS_SHIFT 16
353#define SPU_STATUS_STOPPED 0x0
354#define SPU_STATUS_RUNNING 0x1
355#define SPU_STATUS_STOPPED_BY_STOP 0x2
356#define SPU_STATUS_STOPPED_BY_HALT 0x4
357#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
358#define SPU_STATUS_SINGLE_STEP 0x10
359#define SPU_STATUS_INVALID_INSTR 0x20
360#define SPU_STATUS_INVALID_CH 0x40
361#define SPU_STATUS_ISOLATED_STATE 0x80
arnd@arndb.deeb758ce2006-10-24 18:31:17 +0200362#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
363#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
Arnd Bergmann67207b92005-11-15 15:53:48 -0500364 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
365 u32 spu_spe_R; /* 0x402c */
366 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
367 u32 spu_npc_RW; /* 0x4034 */
368 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
369
370 /* Signal Notification Area */
371 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
372 u32 signal_notify1; /* 0x1400c */
373 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
374 u32 signal_notify2; /* 0x1c00c */
375} __attribute__ ((aligned(0x20000)));
376
377/* SPU Privilege 2 State Area */
378struct spu_priv2 {
379 /* MFC Registers */
380 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
381
382 /* SLB Management Registers */
383 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
384 u64 slb_index_W; /* 0x1108 */
385#define SLB_INDEX_MASK 0x7L
386 u64 slb_esid_RW; /* 0x1110 */
387 u64 slb_vsid_RW; /* 0x1118 */
388#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
389#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
390#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
391#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
392#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
393#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
394#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
395#define SLB_VSID_4K_PAGE (0x0 << 8)
396#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
397#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
398#define SLB_VSID_CLASS_MASK (0x1ull << 7)
399#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
400 u64 slb_invalidate_entry_W; /* 0x1120 */
401 u64 slb_invalidate_all_W; /* 0x1128 */
402 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
403
404 /* Context Save / Restore Area */
405 struct mfc_cq_sr spuq[16]; /* 0x2000 */
406 struct mfc_cq_sr puq[8]; /* 0x2200 */
407 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
408
409 /* MFC Control */
410 u64 mfc_control_RW; /* 0x3000 */
411#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
412#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
413#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
Kazunori Asayama49776d32007-07-20 21:39:30 +0200414#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
Arnd Bergmann67207b92005-11-15 15:53:48 -0500415#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
416#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
417#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
418#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
419#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
420#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
421#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
422#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
423#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
424#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
425#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
426#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
427#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
428#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
429#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
430#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
431#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
432#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
433#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
434 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
435
436 /* Interrupt Mailbox */
437 u64 puint_mb_R; /* 0x4000 */
438 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
439
440 /* SPU Control */
441 u64 spu_privcntl_RW; /* 0x4040 */
442#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
443#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
444#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
445#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
446#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
447#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
448#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
449#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
450 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
451 u64 spu_lslr_RW; /* 0x4058 */
452 u64 spu_chnlcntptr_RW; /* 0x4060 */
453 u64 spu_chnlcnt_RW; /* 0x4068 */
454 u64 spu_chnldata_RW; /* 0x4070 */
455 u64 spu_cfg_RW; /* 0x4078 */
456 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
457
458 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
459 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
460 u64 spu_tag_status_query_RW; /* 0x5008 */
461#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
462#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
463 u64 spu_cmd_buf1_RW; /* 0x5010 */
464#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
465#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
466 u64 spu_cmd_buf2_RW; /* 0x5018 */
467#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
468#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
469#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
470 u64 spu_atomic_status_RW; /* 0x5020 */
471} __attribute__ ((aligned(0x20000)));
472
473/* SPU Privilege 1 State Area */
474struct spu_priv1 {
475 /* Control and Configuration Area */
476 u64 mfc_sr1_RW; /* 0x000 */
477#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
478#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
479#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
480#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
481#define MFC_STATE1_RELOCATE_MASK 0x10ull
482#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
Sebastian Siewiorbe703172007-06-29 10:57:50 +1000483#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
Arnd Bergmann67207b92005-11-15 15:53:48 -0500484 u64 mfc_lpid_RW; /* 0x008 */
485 u64 spu_idr_RW; /* 0x010 */
486 u64 mfc_vr_RO; /* 0x018 */
487#define MFC_VERSION_BITS (0xffff << 16)
488#define MFC_REVISION_BITS (0xffff)
489#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
490#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
491 u64 spu_vr_RO; /* 0x020 */
492#define SPU_VERSION_BITS (0xffff << 16)
493#define SPU_REVISION_BITS (0xffff)
494#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
495#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
496 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
497
Arnd Bergmann67207b92005-11-15 15:53:48 -0500498 /* Interrupt Area */
Arnd Bergmannf0831ac2006-01-04 20:31:30 +0100499 u64 int_mask_RW[3]; /* 0x100 */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500500#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
501#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
502#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
503#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500504#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
505#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
506#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
507#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500508#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
509#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
510#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
511#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
512 u8 pad_0x118_0x140[0x28]; /* 0x118 */
Arnd Bergmannf0831ac2006-01-04 20:31:30 +0100513 u64 int_stat_RW[3]; /* 0x140 */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500514 u8 pad_0x158_0x180[0x28]; /* 0x158 */
515 u64 int_route_RW; /* 0x180 */
516
517 /* Interrupt Routing */
518 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
519
520 /* Atomic Unit Control Area */
521 u64 mfc_atomic_flush_RW; /* 0x200 */
522#define mfc_atomic_flush_enable 0x1L
523 u8 pad_0x208_0x280[0x78]; /* 0x208 */
524 u64 resource_allocation_groupID_RW; /* 0x280 */
525 u64 resource_allocation_enable_RW; /* 0x288 */
526 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
527
528 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
529
530 u64 smf_sbi_signal_sel; /* 0x3c8 */
531#define smf_sbi_mask_lsb 56
532#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
533#define smf_sbi_mask (0x301LL << smf_sbi_shift)
534#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
535#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
536#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
537#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
538 u64 smf_ato_signal_sel; /* 0x3d0 */
539#define smf_ato_mask_lsb 35
540#define smf_ato_shift (63 - smf_ato_mask_lsb)
541#define smf_ato_mask (0x3LL << smf_ato_shift)
542#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
543#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
544 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
545
546 /* TLB Management Registers */
547 u64 mfc_sdr_RW; /* 0x400 */
548 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
549 u64 tlb_index_hint_RO; /* 0x500 */
550 u64 tlb_index_W; /* 0x508 */
551 u64 tlb_vpn_RW; /* 0x510 */
552 u64 tlb_rpn_RW; /* 0x518 */
553 u8 pad_0x520_0x540[0x20]; /* 0x520 */
554 u64 tlb_invalidate_entry_W; /* 0x540 */
555 u64 tlb_invalidate_all_W; /* 0x548 */
556 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
557
558 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
559 u64 smm_hid; /* 0x580 */
560#define PAGE_SIZE_MASK 0xf000000000000000ull
561#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
562 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
563
564 /* MFC Status/Control Area */
565 u64 mfc_accr_RW; /* 0x600 */
566#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
567#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
568#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
569#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
570 u8 pad_0x608_0x610[0x8]; /* 0x608 */
571 u64 mfc_dsisr_RW; /* 0x610 */
572#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
573#define MFC_DSISR_ACCESS_DENIED (1 << 27)
574#define MFC_DSISR_ATOMIC (1 << 26)
575#define MFC_DSISR_ACCESS_PUT (1 << 25)
576#define MFC_DSISR_ADDR_MATCH (1 << 22)
577#define MFC_DSISR_LS (1 << 17)
578#define MFC_DSISR_L (1 << 16)
579#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
580 u8 pad_0x618_0x620[0x8]; /* 0x618 */
581 u64 mfc_dar_RW; /* 0x620 */
582 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
583
584 /* Replacement Management Table (RMT) Area */
585 u64 rmt_index_RW; /* 0x700 */
586 u8 pad_0x708_0x710[0x8]; /* 0x708 */
587 u64 rmt_data1_RW; /* 0x710 */
588 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
589
590 /* Control/Configuration Registers */
591 u64 mfc_dsir_R; /* 0x800 */
592#define MFC_DSIR_Q (1 << 31)
593#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
594 u64 mfc_lsacr_RW; /* 0x808 */
595#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
596#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
597 u64 mfc_lscrr_R; /* 0x810 */
598#define MFC_LSCRR_Q (1 << 31)
599#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
600#define MFC_LSCRR_QI_SHIFT 32
601#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
602 u8 pad_0x818_0x820[0x8]; /* 0x818 */
603 u64 mfc_tclass_id_RW; /* 0x820 */
604#define MFC_TCLASS_ID_ENABLE (1L << 0L)
605#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
606#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
607#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
608#define MFC_TCLASS_QUOTA_2_SHIFT 8L
609#define MFC_TCLASS_QUOTA_1_SHIFT 16L
610#define MFC_TCLASS_QUOTA_0_SHIFT 24L
611#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
612#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
613#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
614 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
615
616 /* Real Mode Support Registers */
617 u64 mfc_rm_boundary; /* 0x900 */
618 u8 pad_0x908_0x938[0x30]; /* 0x908 */
619 u64 smf_dma_signal_sel; /* 0x938 */
620#define mfc_dma1_mask_lsb 41
621#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
622#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
623#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
624#define mfc_dma2_mask_lsb 43
625#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
626#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
627#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
628 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
629 u64 smm_signal_sel; /* 0xa38 */
630#define smm_sig_mask_lsb 12
631#define smm_sig_shift (63 - smm_sig_mask_lsb)
632#define smm_sig_mask (0x3LL << smm_sig_shift)
633#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
634#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
635 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
636
637 /* DMA Command Error Area */
638 u64 mfc_cer_R; /* 0xc00 */
639#define MFC_CER_Q (1 << 31)
640#define MFC_CER_SPU_QUEUE MFC_CER_Q
641 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
642
643 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
644 /* DMA Command Error Area */
645 u64 spu_ecc_cntl_RW; /* 0x1000 */
646#define SPU_ECC_CNTL_E (1ull << 0ull)
647#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
648#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
649#define SPU_ECC_CNTL_S (1ull << 1ull)
650#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
651#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
652#define SPU_ECC_CNTL_B (1ull << 2ull)
653#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
654#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
655#define SPU_ECC_CNTL_I_SHIFT 3ull
656#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
657#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
658#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
659#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
660#define SPU_ECC_CNTL_D (1ull << 5ull)
661#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
662#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
663 u64 spu_ecc_stat_RW; /* 0x1008 */
664#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
665#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
666#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
667#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
668#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
669#define SPU_ECC_DATA_ERROR (1ull << 5ul)
670#define SPU_ECC_DMA_ERROR (1ull << 6ul)
671#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
672 u64 spu_ecc_addr_RW; /* 0x1010 */
673 u64 spu_err_mask_RW; /* 0x1018 */
674#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
675#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
676 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
677
678 /* SPU Debug-Trace Bus (DTB) Selection Registers */
679 u64 spu_trig0_sel; /* 0x1028 */
680 u64 spu_trig1_sel; /* 0x1030 */
681 u64 spu_trig2_sel; /* 0x1038 */
682 u64 spu_trig3_sel; /* 0x1040 */
683 u64 spu_trace_sel; /* 0x1048 */
684#define spu_trace_sel_mask 0x1f1fLL
685#define spu_trace_sel_bus0_bits 0x1000LL
686#define spu_trace_sel_bus2_bits 0x0010LL
687 u64 spu_event0_sel; /* 0x1050 */
688 u64 spu_event1_sel; /* 0x1058 */
689 u64 spu_event2_sel; /* 0x1060 */
690 u64 spu_event3_sel; /* 0x1068 */
691 u64 spu_trace_cntl; /* 0x1070 */
692} __attribute__ ((aligned(0x2000)));
693
Arnd Bergmann88ced032005-12-16 22:43:46 +0100694#endif /* __KERNEL__ */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500695#endif