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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020043#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
Jeff Garzik7bdd7202005-11-16 11:06:59 -050051#define DRV_VERSION "1.2"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
144
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400148
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151};
152
153struct ahci_cmd_hdr {
154 u32 opts;
155 u32 status;
156 u32 tbl_addr;
157 u32 tbl_addr_hi;
158 u32 reserved[4];
159};
160
161struct ahci_sg {
162 u32 addr;
163 u32 addr_hi;
164 u32 reserved;
165 u32 flags_size;
166};
167
168struct ahci_host_priv {
169 unsigned long flags;
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172};
173
174struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
177 void *cmd_tbl;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
180 void *rx_fis;
181 dma_addr_t rx_fis_dma;
182};
183
184static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187static int ahci_qc_issue(struct ata_queued_cmd *qc);
188static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189static void ahci_phy_reset(struct ata_port *ap);
190static void ahci_irq_clear(struct ata_port *ap);
191static void ahci_eng_timeout(struct ata_port *ap);
192static int ahci_port_start(struct ata_port *ap);
193static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195static void ahci_qc_prep(struct ata_queued_cmd *qc);
196static u8 ahci_check_status(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
Jeff Garzik907f4672005-05-12 15:03:42 -0400198static void ahci_remove_one (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
Jeff Garzik193515d2005-11-07 00:59:37 -0500200static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 .module = THIS_MODULE,
202 .name = DRV_NAME,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217};
218
Jeff Garzik057ace52005-10-22 14:27:05 -0400219static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 .dev_select = ata_noop_dev_select,
225
226 .tf_read = ahci_tf_read,
227
228 .phy_reset = ahci_phy_reset,
229
230 .qc_prep = ahci_qc_prep,
231 .qc_issue = ahci_qc_issue,
232
233 .eng_timeout = ahci_eng_timeout,
234
235 .irq_handler = ahci_interrupt,
236 .irq_clear = ahci_irq_clear,
237
238 .scr_read = ahci_scr_read,
239 .scr_write = ahci_scr_write,
240
241 .port_start = ahci_port_start,
242 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243};
244
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100245static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 /* board_ahci */
247 {
248 .sht = &ahci_sht,
249 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
250 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
251 ATA_FLAG_PIO_DMA,
Brett Russ7da79312005-09-01 21:53:34 -0400252 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
254 .port_ops = &ahci_ops,
255 },
256};
257
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500258static const struct pci_device_id ahci_pci_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7R */
269 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ULi M5288 */
Jason Gaston680d3232005-04-16 15:24:45 -0700271 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
Jason Gaston3db368f2005-08-10 06:18:43 -0700277 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ICH7-M DH */
Jason Gastonf2857572006-01-09 11:09:13 -0800279 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH8 */
281 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8M */
287 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 { } /* terminate list */
290};
291
292
293static struct pci_driver ahci_pci_driver = {
294 .name = DRV_NAME,
295 .id_table = ahci_pci_tbl,
296 .probe = ahci_init_one,
Jeff Garzik907f4672005-05-12 15:03:42 -0400297 .remove = ahci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298};
299
300
301static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
302{
303 return base + 0x100 + (port * 0x80);
304}
305
Jeff Garzikea6ba102005-08-30 05:18:18 -0400306static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400308 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309}
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311static int ahci_port_start(struct ata_port *ap)
312{
313 struct device *dev = ap->host_set->dev;
314 struct ahci_host_priv *hpriv = ap->host_set->private_data;
315 struct ahci_port_priv *pp;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400316 void __iomem *mmio = ap->host_set->mmio_base;
317 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
318 void *mem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 dma_addr_t mem_dma;
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500320 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
Tejun Heo0a139e72005-06-26 23:52:50 +0900323 if (!pp)
324 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 memset(pp, 0, sizeof(*pp));
326
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500327 rc = ata_pad_alloc(ap, dev);
328 if (rc) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400329 kfree(pp);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500330 return rc;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400331 }
332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
334 if (!mem) {
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500335 ata_pad_free(ap, dev);
Tejun Heo0a139e72005-06-26 23:52:50 +0900336 kfree(pp);
337 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 }
339 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
340
341 /*
342 * First item in chunk of DMA memory: 32-slot command table,
343 * 32 bytes each in size
344 */
345 pp->cmd_slot = mem;
346 pp->cmd_slot_dma = mem_dma;
347
348 mem += AHCI_CMD_SLOT_SZ;
349 mem_dma += AHCI_CMD_SLOT_SZ;
350
351 /*
352 * Second item: Received-FIS area
353 */
354 pp->rx_fis = mem;
355 pp->rx_fis_dma = mem_dma;
356
357 mem += AHCI_RX_FIS_SZ;
358 mem_dma += AHCI_RX_FIS_SZ;
359
360 /*
361 * Third item: data area for storing a single command
362 * and its scatter-gather table
363 */
364 pp->cmd_tbl = mem;
365 pp->cmd_tbl_dma = mem_dma;
366
367 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
368
369 ap->private_data = pp;
370
371 if (hpriv->cap & HOST_CAP_64)
372 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
373 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
374 readl(port_mmio + PORT_LST_ADDR); /* flush */
375
376 if (hpriv->cap & HOST_CAP_64)
377 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
378 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
379 readl(port_mmio + PORT_FIS_ADDR); /* flush */
380
381 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
382 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
383 PORT_CMD_START, port_mmio + PORT_CMD);
384 readl(port_mmio + PORT_CMD); /* flush */
385
386 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387}
388
389
390static void ahci_port_stop(struct ata_port *ap)
391{
392 struct device *dev = ap->host_set->dev;
393 struct ahci_port_priv *pp = ap->private_data;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400394 void __iomem *mmio = ap->host_set->mmio_base;
395 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 u32 tmp;
397
398 tmp = readl(port_mmio + PORT_CMD);
399 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
400 writel(tmp, port_mmio + PORT_CMD);
401 readl(port_mmio + PORT_CMD); /* flush */
402
403 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
404 * this is slightly incorrect.
405 */
406 msleep(500);
407
408 ap->private_data = NULL;
409 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
410 pp->cmd_slot, pp->cmd_slot_dma);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500411 ata_pad_free(ap, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 kfree(pp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413}
414
415static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
416{
417 unsigned int sc_reg;
418
419 switch (sc_reg_in) {
420 case SCR_STATUS: sc_reg = 0; break;
421 case SCR_CONTROL: sc_reg = 1; break;
422 case SCR_ERROR: sc_reg = 2; break;
423 case SCR_ACTIVE: sc_reg = 3; break;
424 default:
425 return 0xffffffffU;
426 }
427
Al Viro1e4f2a92005-10-21 06:46:02 +0100428 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429}
430
431
432static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
433 u32 val)
434{
435 unsigned int sc_reg;
436
437 switch (sc_reg_in) {
438 case SCR_STATUS: sc_reg = 0; break;
439 case SCR_CONTROL: sc_reg = 1; break;
440 case SCR_ERROR: sc_reg = 2; break;
441 case SCR_ACTIVE: sc_reg = 3; break;
442 default:
443 return;
444 }
445
Al Viro1e4f2a92005-10-21 06:46:02 +0100446 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447}
448
449static void ahci_phy_reset(struct ata_port *ap)
450{
451 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
452 struct ata_taskfile tf;
453 struct ata_device *dev = &ap->device[0];
Jeff Garzik02eaa662005-11-12 01:32:19 -0500454 u32 new_tmp, tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455
456 __sata_phy_reset(ap);
457
458 if (ap->flags & ATA_FLAG_PORT_DISABLED)
459 return;
460
461 tmp = readl(port_mmio + PORT_SIG);
462 tf.lbah = (tmp >> 24) & 0xff;
463 tf.lbam = (tmp >> 16) & 0xff;
464 tf.lbal = (tmp >> 8) & 0xff;
465 tf.nsect = (tmp) & 0xff;
466
467 dev->class = ata_dev_classify(&tf);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500468 if (!ata_dev_present(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469 ata_port_disable(ap);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500470 return;
471 }
472
473 /* Make sure port's ATAPI bit is set appropriately */
474 new_tmp = tmp = readl(port_mmio + PORT_CMD);
475 if (dev->class == ATA_DEV_ATAPI)
476 new_tmp |= PORT_CMD_ATAPI;
477 else
478 new_tmp &= ~PORT_CMD_ATAPI;
479 if (new_tmp != tmp) {
480 writel(new_tmp, port_mmio + PORT_CMD);
481 readl(port_mmio + PORT_CMD); /* flush */
482 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483}
484
485static u8 ahci_check_status(struct ata_port *ap)
486{
Al Viro1e4f2a92005-10-21 06:46:02 +0100487 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489 return readl(mmio + PORT_TFDATA) & 0xFF;
490}
491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
493{
494 struct ahci_port_priv *pp = ap->private_data;
495 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
496
497 ata_tf_from_fis(d2h_fis, tf);
498}
499
Jeff Garzik828d09d2005-11-12 01:27:07 -0500500static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501{
502 struct ahci_port_priv *pp = qc->ap->private_data;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400503 struct scatterlist *sg;
504 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500505 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
507 VPRINTK("ENTER\n");
508
509 /*
510 * Next, the S/G list.
511 */
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400512 ahci_sg = pp->cmd_tbl_sg;
513 ata_for_each_sg(sg, qc) {
514 dma_addr_t addr = sg_dma_address(sg);
515 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400517 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
518 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
519 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -0500520
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400521 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500522 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 }
Jeff Garzik828d09d2005-11-12 01:27:07 -0500524
525 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526}
527
528static void ahci_qc_prep(struct ata_queued_cmd *qc)
529{
Jeff Garzika0ea7322005-06-04 01:13:15 -0400530 struct ata_port *ap = qc->ap;
531 struct ahci_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532 u32 opts;
533 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -0500534 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535
536 /*
537 * Fill in command slot information (currently only one slot,
538 * slot 0, is currently since we don't do queueing)
539 */
540
Jeff Garzik828d09d2005-11-12 01:27:07 -0500541 opts = cmd_fis_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 if (qc->tf.flags & ATA_TFLAG_WRITE)
543 opts |= AHCI_CMD_WRITE;
Jeff Garzika0ea7322005-06-04 01:13:15 -0400544 if (is_atapi_taskfile(&qc->tf))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 opts |= AHCI_CMD_ATAPI;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546
547 pp->cmd_slot[0].opts = cpu_to_le32(opts);
548 pp->cmd_slot[0].status = 0;
549 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
550 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
551
552 /*
553 * Fill in command table information. First, the header,
554 * a SATA Register - Host to Device command FIS.
555 */
556 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
Jeff Garzika0ea7322005-06-04 01:13:15 -0400557 if (opts & AHCI_CMD_ATAPI) {
558 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
559 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
560 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
562 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
563 return;
564
Jeff Garzik828d09d2005-11-12 01:27:07 -0500565 n_elem = ahci_fill_sg(qc);
566
567 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568}
569
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500570static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400572 void __iomem *mmio = ap->host_set->mmio_base;
573 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574 u32 tmp;
575 int work;
576
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500577 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
578 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
579 printk(KERN_WARNING "ata%u: port reset, "
580 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
581 ap->id,
582 irq_stat,
583 readl(mmio + HOST_IRQ_STAT),
584 readl(port_mmio + PORT_IRQ_STAT),
585 readl(port_mmio + PORT_CMD),
586 readl(port_mmio + PORT_TFDATA),
587 readl(port_mmio + PORT_SCR_STAT),
588 readl(port_mmio + PORT_SCR_ERR));
Jeff Garzik9f68a242005-11-15 14:03:47 -0500589
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 /* stop DMA */
591 tmp = readl(port_mmio + PORT_CMD);
592 tmp &= ~PORT_CMD_START;
593 writel(tmp, port_mmio + PORT_CMD);
594
595 /* wait for engine to stop. TODO: this could be
596 * as long as 500 msec
597 */
598 work = 1000;
599 while (work-- > 0) {
600 tmp = readl(port_mmio + PORT_CMD);
601 if ((tmp & PORT_CMD_LIST_ON) == 0)
602 break;
603 udelay(10);
604 }
605
606 /* clear SATA phy error, if any */
607 tmp = readl(port_mmio + PORT_SCR_ERR);
608 writel(tmp, port_mmio + PORT_SCR_ERR);
609
610 /* if DRQ/BSY is set, device needs to be reset.
611 * if so, issue COMRESET
612 */
613 tmp = readl(port_mmio + PORT_TFDATA);
614 if (tmp & (ATA_BUSY | ATA_DRQ)) {
615 writel(0x301, port_mmio + PORT_SCR_CTL);
616 readl(port_mmio + PORT_SCR_CTL); /* flush */
617 udelay(10);
618 writel(0x300, port_mmio + PORT_SCR_CTL);
619 readl(port_mmio + PORT_SCR_CTL); /* flush */
620 }
621
622 /* re-start DMA */
623 tmp = readl(port_mmio + PORT_CMD);
624 tmp |= PORT_CMD_START;
625 writel(tmp, port_mmio + PORT_CMD);
626 readl(port_mmio + PORT_CMD); /* flush */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627}
628
629static void ahci_eng_timeout(struct ata_port *ap)
630{
Jeff Garzikb8f61532005-08-25 22:01:20 -0400631 struct ata_host_set *host_set = ap->host_set;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400632 void __iomem *mmio = host_set->mmio_base;
633 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 struct ata_queued_cmd *qc;
Jeff Garzikb8f61532005-08-25 22:01:20 -0400635 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
Jeff Garzik9f68a242005-11-15 14:03:47 -0500637 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638
Jeff Garzikb8f61532005-08-25 22:01:20 -0400639 spin_lock_irqsave(&host_set->lock, flags);
640
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 qc = ata_qc_from_tag(ap, ap->active_tag);
642 if (!qc) {
643 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
644 ap->id);
645 } else {
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500646 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
Jeff Garzikad36d1a2005-11-14 13:56:37 -0500647
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 /* hack alert! We cannot use the supplied completion
649 * function from inside the ->eh_strategy_handler() thread.
650 * libata is the only user of ->eh_strategy_handler() in
651 * any kernel, so the default scsi_done() assumes it is
652 * not being called from the SCSI EH.
653 */
654 qc->scsidone = scsi_finish_command;
Albert Leea22e2eb2005-12-05 15:38:02 +0800655 qc->err_mask |= AC_ERR_OTHER;
656 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 }
658
Jeff Garzikb8f61532005-08-25 22:01:20 -0400659 spin_unlock_irqrestore(&host_set->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660}
661
662static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
663{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400664 void __iomem *mmio = ap->host_set->mmio_base;
665 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 u32 status, serr, ci;
667
668 serr = readl(port_mmio + PORT_SCR_ERR);
669 writel(serr, port_mmio + PORT_SCR_ERR);
670
671 status = readl(port_mmio + PORT_IRQ_STAT);
672 writel(status, port_mmio + PORT_IRQ_STAT);
673
674 ci = readl(port_mmio + PORT_CMD_ISSUE);
675 if (likely((ci & 0x1) == 0)) {
676 if (qc) {
Albert Leea22e2eb2005-12-05 15:38:02 +0800677 assert(qc->err_mask == 0);
678 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 qc = NULL;
680 }
681 }
682
683 if (status & PORT_IRQ_FATAL) {
Jeff Garzikad36d1a2005-11-14 13:56:37 -0500684 unsigned int err_mask;
685 if (status & PORT_IRQ_TF_ERR)
686 err_mask = AC_ERR_DEV;
687 else if (status & PORT_IRQ_IF_ERR)
688 err_mask = AC_ERR_ATA_BUS;
689 else
690 err_mask = AC_ERR_HOST_BUS;
691
Jeff Garzik9f68a242005-11-15 14:03:47 -0500692 /* command processing has stopped due to error; restart */
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500693 ahci_restart_port(ap, status);
Jeff Garzik9f68a242005-11-15 14:03:47 -0500694
Albert Leea22e2eb2005-12-05 15:38:02 +0800695 if (qc) {
696 qc->err_mask |= AC_ERR_OTHER;
697 ata_qc_complete(qc);
698 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 }
700
701 return 1;
702}
703
704static void ahci_irq_clear(struct ata_port *ap)
705{
706 /* TODO */
707}
708
709static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
710{
711 struct ata_host_set *host_set = dev_instance;
712 struct ahci_host_priv *hpriv;
713 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400714 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 u32 irq_stat, irq_ack = 0;
716
717 VPRINTK("ENTER\n");
718
719 hpriv = host_set->private_data;
720 mmio = host_set->mmio_base;
721
722 /* sigh. 0xffffffff is a valid return from h/w */
723 irq_stat = readl(mmio + HOST_IRQ_STAT);
724 irq_stat &= hpriv->port_map;
725 if (!irq_stat)
726 return IRQ_NONE;
727
728 spin_lock(&host_set->lock);
729
730 for (i = 0; i < host_set->n_ports; i++) {
731 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732
Jeff Garzik67846b32005-10-05 02:58:32 -0400733 if (!(irq_stat & (1 << i)))
734 continue;
735
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 ap = host_set->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -0400737 if (ap) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 struct ata_queued_cmd *qc;
739 qc = ata_qc_from_tag(ap, ap->active_tag);
Jeff Garzik67846b32005-10-05 02:58:32 -0400740 if (!ahci_host_intr(ap, qc))
741 if (ata_ratelimit()) {
742 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500743 to_pci_dev(ap->host_set->dev);
744 dev_printk(KERN_WARNING, &pdev->dev,
745 "unhandled interrupt on port %u\n",
746 i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400747 }
748
749 VPRINTK("port %u\n", i);
750 } else {
751 VPRINTK("port %u (no irq)\n", i);
752 if (ata_ratelimit()) {
753 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500754 to_pci_dev(ap->host_set->dev);
755 dev_printk(KERN_WARNING, &pdev->dev,
756 "interrupt on disabled port %u\n", i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400757 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 }
Jeff Garzik67846b32005-10-05 02:58:32 -0400759
760 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 }
762
763 if (irq_ack) {
764 writel(irq_ack, mmio + HOST_IRQ_STAT);
765 handled = 1;
766 }
767
768 spin_unlock(&host_set->lock);
769
770 VPRINTK("EXIT\n");
771
772 return IRQ_RETVAL(handled);
773}
774
775static int ahci_qc_issue(struct ata_queued_cmd *qc)
776{
777 struct ata_port *ap = qc->ap;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400778 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 writel(1, port_mmio + PORT_CMD_ISSUE);
781 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
782
783 return 0;
784}
785
786static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
787 unsigned int port_idx)
788{
789 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
790 base = ahci_port_base_ul(base, port_idx);
791 VPRINTK("base now==0x%lx\n", base);
792
793 port->cmd_addr = base;
794 port->scr_addr = base + PORT_SCR;
795
796 VPRINTK("EXIT\n");
797}
798
799static int ahci_host_init(struct ata_probe_ent *probe_ent)
800{
801 struct ahci_host_priv *hpriv = probe_ent->private_data;
802 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
803 void __iomem *mmio = probe_ent->mmio_base;
804 u32 tmp, cap_save;
805 u16 tmp16;
806 unsigned int i, j, using_dac;
807 int rc;
808 void __iomem *port_mmio;
809
810 cap_save = readl(mmio + HOST_CAP);
811 cap_save &= ( (1<<28) | (1<<17) );
812 cap_save |= (1 << 27);
813
814 /* global controller reset */
815 tmp = readl(mmio + HOST_CTL);
816 if ((tmp & HOST_RESET) == 0) {
817 writel(tmp | HOST_RESET, mmio + HOST_CTL);
818 readl(mmio + HOST_CTL); /* flush */
819 }
820
821 /* reset must complete within 1 second, or
822 * the hardware should be considered fried.
823 */
824 ssleep(1);
825
826 tmp = readl(mmio + HOST_CTL);
827 if (tmp & HOST_RESET) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500828 dev_printk(KERN_ERR, &pdev->dev,
829 "controller reset failed (0x%x)\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 return -EIO;
831 }
832
833 writel(HOST_AHCI_EN, mmio + HOST_CTL);
834 (void) readl(mmio + HOST_CTL); /* flush */
835 writel(cap_save, mmio + HOST_CAP);
836 writel(0xf, mmio + HOST_PORTS_IMPL);
837 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
838
839 pci_read_config_word(pdev, 0x92, &tmp16);
840 tmp16 |= 0xf;
841 pci_write_config_word(pdev, 0x92, tmp16);
842
843 hpriv->cap = readl(mmio + HOST_CAP);
844 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
845 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
846
847 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
848 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
849
850 using_dac = hpriv->cap & HOST_CAP_64;
851 if (using_dac &&
852 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
853 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
854 if (rc) {
855 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
856 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500857 dev_printk(KERN_ERR, &pdev->dev,
858 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 return rc;
860 }
861 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 } else {
863 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
864 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500865 dev_printk(KERN_ERR, &pdev->dev,
866 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 return rc;
868 }
869 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
870 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500871 dev_printk(KERN_ERR, &pdev->dev,
872 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 return rc;
874 }
875 }
876
877 for (i = 0; i < probe_ent->n_ports; i++) {
878#if 0 /* BIOSen initialize this incorrectly */
879 if (!(hpriv->port_map & (1 << i)))
880 continue;
881#endif
882
883 port_mmio = ahci_port_base(mmio, i);
884 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
885
886 ahci_setup_port(&probe_ent->port[i],
887 (unsigned long) mmio, i);
888
889 /* make sure port is not active */
890 tmp = readl(port_mmio + PORT_CMD);
891 VPRINTK("PORT_CMD 0x%x\n", tmp);
892 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
893 PORT_CMD_FIS_RX | PORT_CMD_START)) {
894 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
895 PORT_CMD_FIS_RX | PORT_CMD_START);
896 writel(tmp, port_mmio + PORT_CMD);
897 readl(port_mmio + PORT_CMD); /* flush */
898
899 /* spec says 500 msecs for each bit, so
900 * this is slightly incorrect.
901 */
902 msleep(500);
903 }
904
905 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
906
907 j = 0;
908 while (j < 100) {
909 msleep(10);
910 tmp = readl(port_mmio + PORT_SCR_STAT);
911 if ((tmp & 0xf) == 0x3)
912 break;
913 j++;
914 }
915
916 tmp = readl(port_mmio + PORT_SCR_ERR);
917 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
918 writel(tmp, port_mmio + PORT_SCR_ERR);
919
920 /* ack any pending irq events for this port */
921 tmp = readl(port_mmio + PORT_IRQ_STAT);
922 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
923 if (tmp)
924 writel(tmp, port_mmio + PORT_IRQ_STAT);
925
926 writel(1 << i, mmio + HOST_IRQ_STAT);
927
928 /* set irq mask (enables interrupts) */
929 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
930 }
931
932 tmp = readl(mmio + HOST_CTL);
933 VPRINTK("HOST_CTL 0x%x\n", tmp);
934 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
935 tmp = readl(mmio + HOST_CTL);
936 VPRINTK("HOST_CTL 0x%x\n", tmp);
937
938 pci_set_master(pdev);
939
940 return 0;
941}
942
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943static void ahci_print_info(struct ata_probe_ent *probe_ent)
944{
945 struct ahci_host_priv *hpriv = probe_ent->private_data;
946 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
Jeff Garzikea6ba102005-08-30 05:18:18 -0400947 void __iomem *mmio = probe_ent->mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 u32 vers, cap, impl, speed;
949 const char *speed_s;
950 u16 cc;
951 const char *scc_s;
952
953 vers = readl(mmio + HOST_VERSION);
954 cap = hpriv->cap;
955 impl = hpriv->port_map;
956
957 speed = (cap >> 20) & 0xf;
958 if (speed == 1)
959 speed_s = "1.5";
960 else if (speed == 2)
961 speed_s = "3";
962 else
963 speed_s = "?";
964
965 pci_read_config_word(pdev, 0x0a, &cc);
966 if (cc == 0x0101)
967 scc_s = "IDE";
968 else if (cc == 0x0106)
969 scc_s = "SATA";
970 else if (cc == 0x0104)
971 scc_s = "RAID";
972 else
973 scc_s = "unknown";
974
Jeff Garzika9524a72005-10-30 14:39:11 -0500975 dev_printk(KERN_INFO, &pdev->dev,
976 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
978 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979
980 (vers >> 24) & 0xff,
981 (vers >> 16) & 0xff,
982 (vers >> 8) & 0xff,
983 vers & 0xff,
984
985 ((cap >> 8) & 0x1f) + 1,
986 (cap & 0x1f) + 1,
987 speed_s,
988 impl,
989 scc_s);
990
Jeff Garzika9524a72005-10-30 14:39:11 -0500991 dev_printk(KERN_INFO, &pdev->dev,
992 "flags: "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 "%s%s%s%s%s%s"
994 "%s%s%s%s%s%s%s\n"
995 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996
997 cap & (1 << 31) ? "64bit " : "",
998 cap & (1 << 30) ? "ncq " : "",
999 cap & (1 << 28) ? "ilck " : "",
1000 cap & (1 << 27) ? "stag " : "",
1001 cap & (1 << 26) ? "pm " : "",
1002 cap & (1 << 25) ? "led " : "",
1003
1004 cap & (1 << 24) ? "clo " : "",
1005 cap & (1 << 19) ? "nz " : "",
1006 cap & (1 << 18) ? "only " : "",
1007 cap & (1 << 17) ? "pmp " : "",
1008 cap & (1 << 15) ? "pio " : "",
1009 cap & (1 << 14) ? "slum " : "",
1010 cap & (1 << 13) ? "part " : ""
1011 );
1012}
1013
1014static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1015{
1016 static int printed_version;
1017 struct ata_probe_ent *probe_ent = NULL;
1018 struct ahci_host_priv *hpriv;
1019 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001020 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 unsigned int board_idx = (unsigned int) ent->driver_data;
Jeff Garzik907f4672005-05-12 15:03:42 -04001022 int have_msi, pci_dev_busy = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 int rc;
1024
1025 VPRINTK("ENTER\n");
1026
1027 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001028 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029
1030 rc = pci_enable_device(pdev);
1031 if (rc)
1032 return rc;
1033
1034 rc = pci_request_regions(pdev, DRV_NAME);
1035 if (rc) {
1036 pci_dev_busy = 1;
1037 goto err_out;
1038 }
1039
Jeff Garzik907f4672005-05-12 15:03:42 -04001040 if (pci_enable_msi(pdev) == 0)
1041 have_msi = 1;
1042 else {
1043 pci_intx(pdev, 1);
1044 have_msi = 0;
1045 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046
1047 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1048 if (probe_ent == NULL) {
1049 rc = -ENOMEM;
Jeff Garzik907f4672005-05-12 15:03:42 -04001050 goto err_out_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 }
1052
1053 memset(probe_ent, 0, sizeof(*probe_ent));
1054 probe_ent->dev = pci_dev_to_dev(pdev);
1055 INIT_LIST_HEAD(&probe_ent->node);
1056
Jeff Garzik374b1872005-08-30 05:42:52 -04001057 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058 if (mmio_base == NULL) {
1059 rc = -ENOMEM;
1060 goto err_out_free_ent;
1061 }
1062 base = (unsigned long) mmio_base;
1063
1064 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1065 if (!hpriv) {
1066 rc = -ENOMEM;
1067 goto err_out_iounmap;
1068 }
1069 memset(hpriv, 0, sizeof(*hpriv));
1070
1071 probe_ent->sht = ahci_port_info[board_idx].sht;
1072 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1073 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1074 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1075 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1076
1077 probe_ent->irq = pdev->irq;
1078 probe_ent->irq_flags = SA_SHIRQ;
1079 probe_ent->mmio_base = mmio_base;
1080 probe_ent->private_data = hpriv;
1081
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001082 if (have_msi)
1083 hpriv->flags |= AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001084
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085 /* initialize adapter */
1086 rc = ahci_host_init(probe_ent);
1087 if (rc)
1088 goto err_out_hpriv;
1089
1090 ahci_print_info(probe_ent);
1091
1092 /* FIXME: check ata_device_add return value */
1093 ata_device_add(probe_ent);
1094 kfree(probe_ent);
1095
1096 return 0;
1097
1098err_out_hpriv:
1099 kfree(hpriv);
1100err_out_iounmap:
Jeff Garzik374b1872005-08-30 05:42:52 -04001101 pci_iounmap(pdev, mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102err_out_free_ent:
1103 kfree(probe_ent);
Jeff Garzik907f4672005-05-12 15:03:42 -04001104err_out_msi:
1105 if (have_msi)
1106 pci_disable_msi(pdev);
1107 else
1108 pci_intx(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 pci_release_regions(pdev);
1110err_out:
1111 if (!pci_dev_busy)
1112 pci_disable_device(pdev);
1113 return rc;
1114}
1115
Jeff Garzik907f4672005-05-12 15:03:42 -04001116static void ahci_remove_one (struct pci_dev *pdev)
1117{
1118 struct device *dev = pci_dev_to_dev(pdev);
1119 struct ata_host_set *host_set = dev_get_drvdata(dev);
1120 struct ahci_host_priv *hpriv = host_set->private_data;
1121 struct ata_port *ap;
1122 unsigned int i;
1123 int have_msi;
1124
1125 for (i = 0; i < host_set->n_ports; i++) {
1126 ap = host_set->ports[i];
1127
1128 scsi_remove_host(ap->host);
1129 }
1130
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001131 have_msi = hpriv->flags & AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001132 free_irq(host_set->irq, host_set);
Jeff Garzik907f4672005-05-12 15:03:42 -04001133
1134 for (i = 0; i < host_set->n_ports; i++) {
1135 ap = host_set->ports[i];
1136
1137 ata_scsi_release(ap->host);
1138 scsi_host_put(ap->host);
1139 }
1140
Jeff Garzike005f012005-08-30 04:18:28 -04001141 kfree(hpriv);
Jeff Garzik374b1872005-08-30 05:42:52 -04001142 pci_iounmap(pdev, host_set->mmio_base);
Jeff Garzikead5de92005-05-31 11:53:57 -04001143 kfree(host_set);
1144
Jeff Garzik907f4672005-05-12 15:03:42 -04001145 if (have_msi)
1146 pci_disable_msi(pdev);
1147 else
1148 pci_intx(pdev, 0);
1149 pci_release_regions(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001150 pci_disable_device(pdev);
1151 dev_set_drvdata(dev, NULL);
1152}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153
1154static int __init ahci_init(void)
1155{
1156 return pci_module_init(&ahci_pci_driver);
1157}
1158
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159static void __exit ahci_exit(void)
1160{
1161 pci_unregister_driver(&ahci_pci_driver);
1162}
1163
1164
1165MODULE_AUTHOR("Jeff Garzik");
1166MODULE_DESCRIPTION("AHCI SATA low-level driver");
1167MODULE_LICENSE("GPL");
1168MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001169MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170
1171module_init(ahci_init);
1172module_exit(ahci_exit);