blob: f8c6771e66d861488bd12fc69d51346a0fedebb6 [file] [log] [blame]
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include "net_driver.h"
16#include "bitfield.h"
17#include "efx.h"
18#include "nic.h"
19#include "mac.h"
20#include "spi.h"
21#include "regs.h"
22#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
27
28/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
29
30static void siena_init_wol(struct efx_nic *efx);
31
32
33static void siena_push_irq_moderation(struct efx_channel *channel)
34{
35 efx_dword_t timer_cmd;
36
37 if (channel->irq_moderation)
38 EFX_POPULATE_DWORD_2(timer_cmd,
39 FRF_CZ_TC_TIMER_MODE,
40 FFE_CZ_TIMER_MODE_INT_HLDOFF,
41 FRF_CZ_TC_TIMER_VAL,
42 channel->irq_moderation - 1);
43 else
44 EFX_POPULATE_DWORD_2(timer_cmd,
45 FRF_CZ_TC_TIMER_MODE,
46 FFE_CZ_TIMER_MODE_DIS,
47 FRF_CZ_TC_TIMER_VAL, 0);
48 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
49 channel->channel);
50}
51
52static void siena_push_multicast_hash(struct efx_nic *efx)
53{
54 WARN_ON(!mutex_is_locked(&efx->mac_lock));
55
56 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
57 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
58 NULL, 0, NULL);
59}
60
61static int siena_mdio_write(struct net_device *net_dev,
62 int prtad, int devad, u16 addr, u16 value)
63{
64 struct efx_nic *efx = netdev_priv(net_dev);
65 uint32_t status;
66 int rc;
67
68 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
69 addr, value, &status);
70 if (rc)
71 return rc;
72 if (status != MC_CMD_MDIO_STATUS_GOOD)
73 return -EIO;
74
75 return 0;
76}
77
78static int siena_mdio_read(struct net_device *net_dev,
79 int prtad, int devad, u16 addr)
80{
81 struct efx_nic *efx = netdev_priv(net_dev);
82 uint16_t value;
83 uint32_t status;
84 int rc;
85
86 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
87 addr, &value, &status);
88 if (rc)
89 return rc;
90 if (status != MC_CMD_MDIO_STATUS_GOOD)
91 return -EIO;
92
93 return (int)value;
94}
95
96/* This call is responsible for hooking in the MAC and PHY operations */
97static int siena_probe_port(struct efx_nic *efx)
98{
99 int rc;
100
101 /* Hook in PHY operations table */
102 efx->phy_op = &efx_mcdi_phy_ops;
103
104 /* Set up MDIO structure for PHY */
105 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
106 efx->mdio.mdio_read = siena_mdio_read;
107 efx->mdio.mdio_write = siena_mdio_write;
108
109 /* Fill out MDIO structure and loopback modes */
110 rc = efx->phy_op->probe(efx);
111 if (rc != 0)
112 return rc;
113
114 /* Initial assumption */
115 efx->link_state.speed = 10000;
116 efx->link_state.fd = true;
117 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
118
119 /* Allocate buffer for stats */
120 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
121 MC_CMD_MAC_NSTATS * sizeof(u64));
122 if (rc)
123 return rc;
124 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
125 (u64)efx->stats_buffer.dma_addr,
126 efx->stats_buffer.addr,
127 (u64)virt_to_phys(efx->stats_buffer.addr));
128
129 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
130
131 return 0;
132}
133
134void siena_remove_port(struct efx_nic *efx)
135{
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000136 efx->phy_op->remove(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000137 efx_nic_free_buffer(efx, &efx->stats_buffer);
138}
139
140static const struct efx_nic_register_test siena_register_tests[] = {
141 { FR_AZ_ADR_REGION,
142 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
143 { FR_CZ_USR_EV_CFG,
144 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
145 { FR_AZ_RX_CFG,
146 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
147 { FR_AZ_TX_CFG,
148 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
149 { FR_AZ_TX_RESERVED,
150 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
151 { FR_AZ_SRM_TX_DC_CFG,
152 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_CFG,
154 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_AZ_RX_DC_PF_WM,
156 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_DP_CTRL,
158 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
159 { FR_BZ_RX_RSS_TKEY,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG1,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG2,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
165 { FR_CZ_RX_RSS_IPV6_REG3,
166 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
167};
168
169static int siena_test_registers(struct efx_nic *efx)
170{
171 return efx_nic_test_registers(efx, siena_register_tests,
172 ARRAY_SIZE(siena_register_tests));
173}
174
175/**************************************************************************
176 *
177 * Device reset
178 *
179 **************************************************************************
180 */
181
182static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
183{
184
185 if (method == RESET_TYPE_WORLD)
186 return efx_mcdi_reset_mc(efx);
187 else
188 return efx_mcdi_reset_port(efx);
189}
190
191static int siena_probe_nvconfig(struct efx_nic *efx)
192{
193 int rc;
194
195 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
196 if (rc)
197 return rc;
198
199 return 0;
200}
201
202static int siena_probe_nic(struct efx_nic *efx)
203{
204 struct siena_nic_data *nic_data;
205 bool already_attached = 0;
206 int rc;
207
208 /* Allocate storage for hardware specific data */
209 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
210 if (!nic_data)
211 return -ENOMEM;
212 efx->nic_data = nic_data;
213
214 if (efx_nic_fpga_ver(efx) != 0) {
215 EFX_ERR(efx, "Siena FPGA not supported\n");
216 rc = -ENODEV;
217 goto fail1;
218 }
219
220 efx_mcdi_init(efx);
221
222 /* Recover from a failed assertion before probing */
223 rc = efx_mcdi_handle_assertion(efx);
224 if (rc)
225 goto fail1;
226
227 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
228 if (rc) {
229 EFX_ERR(efx, "Failed to read MCPU firmware version - "
230 "rc %d\n", rc);
231 goto fail1; /* MCPU absent? */
232 }
233
234 /* Let the BMC know that the driver is now in charge of link and
235 * filter settings. We must do this before we reset the NIC */
236 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
237 if (rc) {
238 EFX_ERR(efx, "Unable to register driver with MCPU\n");
239 goto fail2;
240 }
241 if (already_attached)
242 /* Not a fatal error */
243 EFX_ERR(efx, "Host already registered with MCPU\n");
244
245 /* Now we can reset the NIC */
246 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
247 if (rc) {
248 EFX_ERR(efx, "failed to reset NIC\n");
249 goto fail3;
250 }
251
252 siena_init_wol(efx);
253
254 /* Allocate memory for INT_KER */
255 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
256 if (rc)
257 goto fail4;
258 BUG_ON(efx->irq_status.dma_addr & 0x0f);
259
260 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
261 (unsigned long long)efx->irq_status.dma_addr,
262 efx->irq_status.addr,
263 (unsigned long long)virt_to_phys(efx->irq_status.addr));
264
265 /* Read in the non-volatile configuration */
266 rc = siena_probe_nvconfig(efx);
267 if (rc == -EINVAL) {
268 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
269 efx->phy_type = PHY_TYPE_NONE;
270 efx->mdio.prtad = MDIO_PRTAD_NONE;
271 } else if (rc) {
272 goto fail5;
273 }
274
275 return 0;
276
277fail5:
278 efx_nic_free_buffer(efx, &efx->irq_status);
279fail4:
280fail3:
281 efx_mcdi_drv_attach(efx, false, NULL);
282fail2:
283fail1:
284 kfree(efx->nic_data);
285 return rc;
286}
287
288/* This call performs hardware-specific global initialisation, such as
289 * defining the descriptor cache sizes and number of RSS channels.
290 * It does not set up any buffers, descriptor rings or event queues.
291 */
292static int siena_init_nic(struct efx_nic *efx)
293{
294 efx_oword_t temp;
295 int rc;
296
297 /* Recover from a failed assertion post-reset */
298 rc = efx_mcdi_handle_assertion(efx);
299 if (rc)
300 return rc;
301
302 /* Squash TX of packets of 16 bytes or less */
303 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
304 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
305 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
306
307 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
308 * descriptors (which is bad).
309 */
310 efx_reado(efx, &temp, FR_AZ_TX_CFG);
311 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
312 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
313 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
314
315 efx_reado(efx, &temp, FR_AZ_RX_CFG);
316 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
317 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
318 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
319
320 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
321 /* No MCDI operation has been defined to set thresholds */
322 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
323
324 /* Enable event logging */
325 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
326 if (rc)
327 return rc;
328
329 /* Set destination of both TX and RX Flush events */
330 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
331 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
332
333 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
334 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
335
336 efx_nic_init_common(efx);
337 return 0;
338}
339
340static void siena_remove_nic(struct efx_nic *efx)
341{
342 efx_nic_free_buffer(efx, &efx->irq_status);
343
344 siena_reset_hw(efx, RESET_TYPE_ALL);
345
346 /* Relinquish the device back to the BMC */
347 if (efx_nic_has_mc(efx))
348 efx_mcdi_drv_attach(efx, false, NULL);
349
350 /* Tear down the private nic state */
351 kfree(efx->nic_data);
352 efx->nic_data = NULL;
353}
354
355#define STATS_GENERATION_INVALID ((u64)(-1))
356
357static int siena_try_update_nic_stats(struct efx_nic *efx)
358{
359 u64 *dma_stats;
360 struct efx_mac_stats *mac_stats;
361 u64 generation_start;
362 u64 generation_end;
363
364 mac_stats = &efx->mac_stats;
365 dma_stats = (u64 *)efx->stats_buffer.addr;
366
367 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
368 if (generation_end == STATS_GENERATION_INVALID)
369 return 0;
370 rmb();
371
372#define MAC_STAT(M, D) \
373 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
374
375 MAC_STAT(tx_bytes, TX_BYTES);
376 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
377 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
378 mac_stats->tx_bad_bytes);
379 MAC_STAT(tx_packets, TX_PKTS);
380 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
381 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
382 MAC_STAT(tx_control, TX_CONTROL_PKTS);
383 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
384 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
385 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
386 MAC_STAT(tx_lt64, TX_LT64_PKTS);
387 MAC_STAT(tx_64, TX_64_PKTS);
388 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
389 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
390 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
391 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
392 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
393 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
394 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
395 mac_stats->tx_collision = 0;
396 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
397 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
398 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
399 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
400 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
401 mac_stats->tx_collision = (mac_stats->tx_single_collision +
402 mac_stats->tx_multiple_collision +
403 mac_stats->tx_excessive_collision +
404 mac_stats->tx_late_collision);
405 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
406 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
407 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
408 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
409 MAC_STAT(rx_bytes, RX_BYTES);
410 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
411 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
412 mac_stats->rx_bad_bytes);
413 MAC_STAT(rx_packets, RX_PKTS);
414 MAC_STAT(rx_good, RX_GOOD_PKTS);
415 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
416 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
417 MAC_STAT(rx_control, RX_CONTROL_PKTS);
418 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
419 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
420 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
421 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
422 MAC_STAT(rx_64, RX_64_PKTS);
423 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
424 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
425 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
426 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
427 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
428 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
429 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
430 mac_stats->rx_bad_lt64 = 0;
431 mac_stats->rx_bad_64_to_15xx = 0;
432 mac_stats->rx_bad_15xx_to_jumbo = 0;
433 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
434 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
435 mac_stats->rx_missed = 0;
436 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
437 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
438 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
439 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
440 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
441 mac_stats->rx_good_lt64 = 0;
442
443 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
444
445#undef MAC_STAT
446
447 rmb();
448 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
449 if (generation_end != generation_start)
450 return -EAGAIN;
451
452 return 0;
453}
454
455static void siena_update_nic_stats(struct efx_nic *efx)
456{
457 while (siena_try_update_nic_stats(efx) == -EAGAIN)
458 cpu_relax();
459}
460
461static void siena_start_nic_stats(struct efx_nic *efx)
462{
463 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
464
465 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
466
467 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
468 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
469}
470
471static void siena_stop_nic_stats(struct efx_nic *efx)
472{
473 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
474}
475
476void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
477{
478 struct siena_nic_data *nic_data = efx->nic_data;
479 snprintf(buf, len, "%u.%u.%u.%u",
480 (unsigned int)(nic_data->fw_version >> 48),
481 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
482 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
483 (unsigned int)(nic_data->fw_version & 0xffff));
484}
485
486/**************************************************************************
487 *
488 * Wake on LAN
489 *
490 **************************************************************************
491 */
492
493static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
494{
495 struct siena_nic_data *nic_data = efx->nic_data;
496
497 wol->supported = WAKE_MAGIC;
498 if (nic_data->wol_filter_id != -1)
499 wol->wolopts = WAKE_MAGIC;
500 else
501 wol->wolopts = 0;
502 memset(&wol->sopass, 0, sizeof(wol->sopass));
503}
504
505
506static int siena_set_wol(struct efx_nic *efx, u32 type)
507{
508 struct siena_nic_data *nic_data = efx->nic_data;
509 int rc;
510
511 if (type & ~WAKE_MAGIC)
512 return -EINVAL;
513
514 if (type & WAKE_MAGIC) {
515 if (nic_data->wol_filter_id != -1)
516 efx_mcdi_wol_filter_remove(efx,
517 nic_data->wol_filter_id);
518 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
519 &nic_data->wol_filter_id);
520 if (rc)
521 goto fail;
522
523 pci_wake_from_d3(efx->pci_dev, true);
524 } else {
525 rc = efx_mcdi_wol_filter_reset(efx);
526 nic_data->wol_filter_id = -1;
527 pci_wake_from_d3(efx->pci_dev, false);
528 if (rc)
529 goto fail;
530 }
531
532 return 0;
533 fail:
534 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
535 return rc;
536}
537
538
539static void siena_init_wol(struct efx_nic *efx)
540{
541 struct siena_nic_data *nic_data = efx->nic_data;
542 int rc;
543
544 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
545
546 if (rc != 0) {
547 /* If it failed, attempt to get into a synchronised
548 * state with MC by resetting any set WoL filters */
549 efx_mcdi_wol_filter_reset(efx);
550 nic_data->wol_filter_id = -1;
551 } else if (nic_data->wol_filter_id != -1) {
552 pci_wake_from_d3(efx->pci_dev, true);
553 }
554}
555
556
557/**************************************************************************
558 *
559 * Revision-dependent attributes used by efx.c and nic.c
560 *
561 **************************************************************************
562 */
563
564struct efx_nic_type siena_a0_nic_type = {
565 .probe = siena_probe_nic,
566 .remove = siena_remove_nic,
567 .init = siena_init_nic,
568 .fini = efx_port_dummy_op_void,
569 .monitor = NULL,
570 .reset = siena_reset_hw,
571 .probe_port = siena_probe_port,
572 .remove_port = siena_remove_port,
573 .prepare_flush = efx_port_dummy_op_void,
574 .update_stats = siena_update_nic_stats,
575 .start_stats = siena_start_nic_stats,
576 .stop_stats = siena_stop_nic_stats,
577 .set_id_led = efx_mcdi_set_id_led,
578 .push_irq_moderation = siena_push_irq_moderation,
579 .push_multicast_hash = siena_push_multicast_hash,
580 .reconfigure_port = efx_mcdi_phy_reconfigure,
581 .get_wol = siena_get_wol,
582 .set_wol = siena_set_wol,
583 .resume_wol = siena_init_wol,
584 .test_registers = siena_test_registers,
585 .default_mac_ops = &efx_mcdi_mac_operations,
586
587 .revision = EFX_REV_SIENA_A0,
588 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
589 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
590 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
591 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
592 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
593 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
594 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
595 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
596 .rx_buffer_padding = 0,
597 .max_interrupt_mode = EFX_INT_MODE_MSIX,
598 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
599 * interrupt handler only supports 32
600 * channels */
601 .tx_dc_base = 0x88000,
602 .rx_dc_base = 0x68000,
603 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
604 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
605};