Rabin Vincent | f066439 | 2010-09-13 12:39:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010 |
| 3 | * |
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson |
| 5 | * License terms: GNU General Public License (GPL) version 2 |
| 6 | * |
| 7 | * DB5500-SoC-specific configuration for DMA40 |
| 8 | */ |
| 9 | |
| 10 | #ifndef STE_DMA40_DB5500_H |
| 11 | #define STE_DMA40_DB5500_H |
| 12 | |
| 13 | #define DB5500_DMA_NR_DEV 64 |
| 14 | |
| 15 | enum dma_src_dev_type { |
| 16 | DB5500_DMA_DEV0_SPI0_RX = 0, |
| 17 | DB5500_DMA_DEV1_SPI1_RX = 1, |
| 18 | DB5500_DMA_DEV2_SPI2_RX = 2, |
| 19 | DB5500_DMA_DEV3_SPI3_RX = 3, |
| 20 | DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4, |
| 21 | DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5, |
| 22 | DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6, |
| 23 | DB5500_DMA_DEV7_IRDA_RFS = 7, |
| 24 | DB5500_DMA_DEV8_IRDA_FIFO_RX = 8, |
| 25 | DB5500_DMA_DEV9_MSP0_RX = 9, |
| 26 | DB5500_DMA_DEV10_MSP1_RX = 10, |
| 27 | DB5500_DMA_DEV11_MSP2_RX = 11, |
| 28 | DB5500_DMA_DEV12_UART0_RX = 12, |
| 29 | DB5500_DMA_DEV13_UART1_RX = 13, |
| 30 | DB5500_DMA_DEV14_UART2_RX = 14, |
| 31 | DB5500_DMA_DEV15_UART3_RX = 15, |
| 32 | DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16, |
| 33 | DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17, |
| 34 | DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18, |
| 35 | DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19, |
| 36 | DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20, |
| 37 | DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21, |
| 38 | DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22, |
| 39 | DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23, |
| 40 | DB5500_DMA_DEV24_SDMMC0_RX = 24, |
| 41 | DB5500_DMA_DEV25_SDMMC1_RX = 25, |
| 42 | DB5500_DMA_DEV26_SDMMC2_RX = 26, |
| 43 | DB5500_DMA_DEV27_SDMMC3_RX = 27, |
| 44 | DB5500_DMA_DEV28_SDMMC4_RX = 28, |
| 45 | /* 29 - 32 not used */ |
| 46 | DB5500_DMA_DEV33_SDMMC0_RX = 33, |
| 47 | DB5500_DMA_DEV34_SDMMC1_RX = 34, |
| 48 | DB5500_DMA_DEV35_SDMMC2_RX = 35, |
| 49 | DB5500_DMA_DEV36_SDMMC3_RX = 36, |
| 50 | DB5500_DMA_DEV37_SDMMC4_RX = 37, |
| 51 | DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38, |
| 52 | DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39, |
| 53 | DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40, |
| 54 | DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41, |
| 55 | DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42, |
| 56 | DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43, |
| 57 | DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44, |
| 58 | DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45, |
| 59 | /* 46 not used */ |
| 60 | DB5500_DMA_DEV47_MCDE_RX = 47, |
| 61 | DB5500_DMA_DEV48_CRYPTO1_RX = 48, |
| 62 | /* 49, 50 not used */ |
| 63 | DB5500_DMA_DEV49_I2C1_RX = 51, |
| 64 | DB5500_DMA_DEV50_I2C3_RX = 52, |
| 65 | DB5500_DMA_DEV51_I2C2_RX = 53, |
| 66 | /* 54 - 60 not used */ |
| 67 | DB5500_DMA_DEV61_CRYPTO0_RX = 61, |
| 68 | /* 62, 63 not used */ |
| 69 | }; |
| 70 | |
| 71 | enum dma_dest_dev_type { |
| 72 | DB5500_DMA_DEV0_SPI0_TX = 0, |
| 73 | DB5500_DMA_DEV1_SPI1_TX = 1, |
| 74 | DB5500_DMA_DEV2_SPI2_TX = 2, |
| 75 | DB5500_DMA_DEV3_SPI3_TX = 3, |
| 76 | DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4, |
| 77 | DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5, |
| 78 | DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6, |
| 79 | DB5500_DMA_DEV7_IRRC_TX = 7, |
| 80 | DB5500_DMA_DEV8_IRDA_FIFO_TX = 8, |
| 81 | DB5500_DMA_DEV9_MSP0_TX = 9, |
| 82 | DB5500_DMA_DEV10_MSP1_TX = 10, |
| 83 | DB5500_DMA_DEV11_MSP2_TX = 11, |
| 84 | DB5500_DMA_DEV12_UART0_TX = 12, |
| 85 | DB5500_DMA_DEV13_UART1_TX = 13, |
| 86 | DB5500_DMA_DEV14_UART2_TX = 14, |
| 87 | DB5500_DMA_DEV15_UART3_TX = 15, |
| 88 | DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16, |
| 89 | DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17, |
| 90 | DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18, |
| 91 | DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19, |
| 92 | DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20, |
| 93 | DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21, |
| 94 | DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22, |
| 95 | DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23, |
| 96 | DB5500_DMA_DEV24_SDMMC0_TX = 24, |
| 97 | DB5500_DMA_DEV25_SDMMC1_TX = 25, |
| 98 | DB5500_DMA_DEV26_SDMMC2_TX = 26, |
| 99 | DB5500_DMA_DEV27_SDMMC3_TX = 27, |
| 100 | DB5500_DMA_DEV28_SDMMC4_TX = 28, |
| 101 | /* 29 - 31 not used */ |
| 102 | DB5500_DMA_DEV32_FSMC_TX = 32, |
| 103 | DB5500_DMA_DEV33_SDMMC0_TX = 33, |
| 104 | DB5500_DMA_DEV34_SDMMC1_TX = 34, |
| 105 | DB5500_DMA_DEV35_SDMMC2_TX = 35, |
| 106 | DB5500_DMA_DEV36_SDMMC3_TX = 36, |
| 107 | DB5500_DMA_DEV37_SDMMC4_TX = 37, |
| 108 | DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38, |
| 109 | DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39, |
| 110 | DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40, |
| 111 | DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41, |
| 112 | DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42, |
| 113 | DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43, |
| 114 | DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44, |
| 115 | DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45, |
| 116 | /* 46 not used */ |
| 117 | DB5500_DMA_DEV47_STM_TX = 47, |
| 118 | DB5500_DMA_DEV48_CRYPTO1_TX = 48, |
| 119 | DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49, |
| 120 | DB5500_DMA_DEV50_HASH1_TX = 50, |
| 121 | DB5500_DMA_DEV51_I2C1_TX = 51, |
| 122 | DB5500_DMA_DEV52_I2C3_TX = 52, |
| 123 | DB5500_DMA_DEV53_I2C2_TX = 53, |
| 124 | /* 54, 55 not used */ |
| 125 | DB5500_DMA_MEMCPY_TX_1 = 56, |
| 126 | DB5500_DMA_MEMCPY_TX_2 = 57, |
| 127 | DB5500_DMA_MEMCPY_TX_3 = 58, |
| 128 | DB5500_DMA_MEMCPY_TX_4 = 59, |
| 129 | DB5500_DMA_MEMCPY_TX_5 = 60, |
| 130 | DB5500_DMA_DEV61_CRYPTO0_TX = 61, |
| 131 | DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62, |
| 132 | DB5500_DMA_DEV63_HASH0_TX = 63, |
| 133 | }; |
| 134 | |
| 135 | #endif |