blob: fbc1940da92599999066dbf9318f0ea7428db99a [file] [log] [blame]
Olav Haugan54166782013-01-28 16:59:51 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/ {
14 lpass_iommu: qcom,iommu@fd000000 {
15 compatible = "qcom,msm-smmu-v1";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19 reg = <0xfd000000 0x10000>;
20 qcom,glb-offset = <0xF000>;
21 label = "lpass_iommu";
22 status = "disabled";
23
24 lpass_q6_fw: qcom,iommu-ctx@fd000000 {
25 reg = <0xfd000000 0x1000>;
26 interrupts = <0 250 0>;
27 qcom,iommu-ctx-mids = <0 15>;
28 label = "q6_fw";
29 };
30
31 lpass_audio_shared: qcom,iommu-ctx@fd001000 {
32 reg = <0xfd001000 0x1000>;
33 interrupts = <0 250 0>;
34 qcom,iommu-ctx-mids = <1>;
35 label = "audio_shared";
36 };
37
38 lpass_video_shared: qcom,iommu-ctx@fd002000 {
39 reg = <0xfd002000 0x1000>;
40 interrupts = <0 250 0>;
41 qcom,iommu-ctx-mids = <2>;
42 label = "video_shared";
43 };
44
45 lpass_q6_spare: qcom,iommu-ctx@fd003000 {
46 reg = <0xfd003000 0x1000>;
47 interrupts = <0 250 0>;
48 qcom,iommu-ctx-mids = <3 4 5 6 7 8 9 10 11 12 13 14>;
49 label = "q6_spare";
50 };
51 };
52
53 copss_iommu: qcom,iommu@fd010000 {
54 compatible = "qcom,msm-smmu-v1";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58 reg = <0xfd010000 0x10000>;
59 qcom,glb-offset = <0xF000>;
60 label = "copss_iommu";
61 status = "disabled";
62
63 qcom,iommu-ctx@fd010000 {
64 reg = <0xfd010000 0x1000>;
65 interrupts = <0 254 0>;
66 qcom,iommu-ctx-mids = <0>;
67 label = "copss_0";
68 };
69
70 qcom,iommu-ctx@fd011000 {
71 reg = <0xfd011000 0x1000>;
72 interrupts = <0 254 0>;
73 qcom,iommu-ctx-mids = <1>;
74 label = "copss_1";
75 };
76
77 qcom,iommu-ctx@fd012000 {
78 reg = <0xfd012000 0x1000>;
79 interrupts = <0 254 0>;
80 qcom,iommu-ctx-mids = <2>;
81 label = "copss_2";
82 };
83
84 qcom,iommu-ctx@fd013000 {
85 reg = <0xfd013000 0x1000>;
86 interrupts = <0 254 0>;
87 qcom,iommu-ctx-mids = <3>;
88 label = "copss_3";
89 };
90
91 qcom,iommu-ctx@fd014000 {
92 reg = <0xfd014000 0x1000>;
93 interrupts = <0 254 0>;
94 qcom,iommu-ctx-mids = <4>;
95 label = "copss_4";
96 };
97
98 qcom,iommu-ctx@fd015000 {
99 reg = <0xfd015000 0x1000>;
100 interrupts = <0 254 0>;
101 qcom,iommu-ctx-mids = <5>;
102 label = "copss_5";
103 };
104
105 qcom,iommu-ctx@fd016000 {
106 reg = <0xfd016000 0x1000>;
107 interrupts = <0 254 0>;
108 qcom,iommu-ctx-mids = <6>;
109 label = "copss_6";
110 };
111
112 qcom,iommu-ctx@fd017000 {
113 reg = <0xfd017000 0x1000>;
114 interrupts = <0 254 0>;
115 qcom,iommu-ctx-mids = <7>;
116 label = "copss_7";
117 };
118 };
119
120 mdpe_iommu: qcom,iommu@fd860000 {
121 compatible = "qcom,msm-smmu-v1";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges;
125 reg = <0xfd860000 0x10000>;
126 qcom,glb-offset = <0xF000>;
127 label = "mdpe_iommu";
128 status = "disabled";
129
130 qcom,iommu-ctx@fd860000 {
131 reg = <0xfd860000 0x1000>;
132 interrupts = <0 247 0>;
133 qcom,iommu-ctx-mids = <>;
134 label = "mdpe_0";
135 };
136
137 qcom,iommu-ctx@fd861000 {
138 reg = <0xfd861000 0x1000>;
139 interrupts = <0 247 0>;
140 qcom,iommu-ctx-mids = <>;
141 label = "mdpe_1";
142 };
143 };
144
145 mdps_iommu: qcom,iommu@fd870000 {
146 compatible = "qcom,msm-smmu-v1";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges;
150 reg = <0xfd870000 0x10000>;
151 qcom,glb-offset = <0xF000>;
152 label = "mdps_iommu";
153 status = "disabled";
154
155 qcom,iommu-ctx@fd870000 {
156 reg = <0xfd870000 0x1000>;
157 interrupts = <0 247 0>;
158 qcom,iommu-ctx-mids = <>;
159 label = "mdps_0";
160 };
161
162 qcom,iommu-ctx@fd871000 {
163 reg = <0xfd871000 0x1000>;
164 interrupts = <0 247 0>;
165 qcom,iommu-ctx-mids = <>;
166 label = "mdps_1";
167 };
168 };
169
170 gfx_iommu: qcom,iommu@fd880000 {
171 compatible = "qcom,msm-smmu-v1";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175 reg = <0xfd880000 0x10000>;
176 qcom,glb-offset = <0xF000>;
177 label = "gfx_iommu";
178 status = "disabled";
179
180 qcom,iommu-ctx@fd880000 {
181 reg = <0xfd880000 0x1000>;
182 interrupts = <0 241 0>;
183 qcom,iommu-ctx-mids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13
184 14 15>;
185 label = "gfx3d_user";
186 };
187
188 qcom,iommu-ctx@fd881000 {
189 reg = <0xfd881000 0x1000>;
190 interrupts = <0 241 0>;
191 qcom,iommu-ctx-mids = <16 17 18 19 20 21 22 23 24 25
192 26 27 28 29 30 31>;
193 label = "gfx3d_priv";
194 };
195
196 qcom,iommu-ctx@fd882000 {
197 reg = <0xfd882000 0x1000>;
198 interrupts = <0 241 0>;
199 qcom,iommu-ctx-mids = <>;
200 label = "gfx3d_spare";
201 };
202 };
203
204 vfe_iommu: qcom,iommu@fd890000 {
205 compatible = "qcom,msm-smmu-v1";
206 #address-cells = <1>;
207 #size-cells = <1>;
208 ranges;
209 reg = <0xfd890000 0x10000>;
210 qcom,glb-offset = <0xF000>;
211 label = "vfe_iommu";
212 status = "disabled";
213
214 qcom,iommu-ctx@fd890000 {
215 reg = <0xfd890000 0x1000>;
216 interrupts = <0 65 0>;
217 qcom,iommu-ctx-mids = <0>;
218 label = "vfe0";
219 };
220
221 qcom,iommu-ctx@fd891000 {
222 reg = <0xfd891000 0x1000>;
223 interrupts = <0 65 0>;
224 qcom,iommu-ctx-mids = <1>;
225 label = "vfe1";
226 };
227 };
228};