Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 19 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 20 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 21 | #include <plat/mcspi.h> |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 22 | #include <plat/dmtimer.h> |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 23 | #include <plat/l3_2xxx.h> |
| 24 | #include <plat/l4_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 25 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 26 | #include "omap_hwmod_common_data.h" |
| 27 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 28 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 29 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 30 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 31 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 32 | /* |
| 33 | * OMAP2420 hardware module integration data |
| 34 | * |
| 35 | * ALl of the data in this section should be autogeneratable from the |
| 36 | * TI hardware database or other technical documentation. Data that |
| 37 | * is driver-specific or driver-kernel integration-specific belongs |
| 38 | * elsewhere. |
| 39 | */ |
| 40 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 41 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 42 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 43 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 44 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 45 | static struct omap_hwmod omap2420_dss_core_hwmod; |
| 46 | static struct omap_hwmod omap2420_dss_dispc_hwmod; |
| 47 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; |
| 48 | static struct omap_hwmod omap2420_dss_venc_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 49 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 50 | static struct omap_hwmod omap2420_gpio1_hwmod; |
| 51 | static struct omap_hwmod omap2420_gpio2_hwmod; |
| 52 | static struct omap_hwmod omap2420_gpio3_hwmod; |
| 53 | static struct omap_hwmod omap2420_gpio4_hwmod; |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 54 | static struct omap_hwmod omap2420_dma_system_hwmod; |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 55 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
| 56 | static struct omap_hwmod omap2420_mcspi2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 57 | |
| 58 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 59 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 60 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 61 | .slave = &omap2420_l4_core_hwmod, |
| 62 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 63 | }; |
| 64 | |
| 65 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 66 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 67 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 68 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 69 | .user = OCP_USER_MPU, |
| 70 | }; |
| 71 | |
| 72 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 73 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 74 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 75 | }; |
| 76 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 77 | /* DSS -> l3 */ |
| 78 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { |
| 79 | .master = &omap2420_dss_core_hwmod, |
| 80 | .slave = &omap2420_l3_main_hwmod, |
| 81 | .fw = { |
| 82 | .omap2 = { |
| 83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 84 | .flags = OMAP_FIREWALL_L3, |
| 85 | } |
| 86 | }, |
| 87 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 88 | }; |
| 89 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 90 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 91 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 92 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 96 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 97 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 98 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 99 | .masters = omap2420_l3_main_masters, |
| 100 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 101 | .slaves = omap2420_l3_main_slaves, |
| 102 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 104 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 108 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 109 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 110 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 111 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 112 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 113 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 114 | /* l4 core -> mcspi1 interface */ |
| 115 | static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { |
| 116 | { |
| 117 | .pa_start = 0x48098000, |
| 118 | .pa_end = 0x480980ff, |
| 119 | .flags = ADDR_TYPE_RT, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
| 124 | .master = &omap2420_l4_core_hwmod, |
| 125 | .slave = &omap2420_mcspi1_hwmod, |
| 126 | .clk = "mcspi1_ick", |
| 127 | .addr = omap2420_mcspi1_addr_space, |
| 128 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), |
| 129 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 130 | }; |
| 131 | |
| 132 | /* l4 core -> mcspi2 interface */ |
| 133 | static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { |
| 134 | { |
| 135 | .pa_start = 0x4809a000, |
| 136 | .pa_end = 0x4809a0ff, |
| 137 | .flags = ADDR_TYPE_RT, |
| 138 | }, |
| 139 | }; |
| 140 | |
| 141 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
| 142 | .master = &omap2420_l4_core_hwmod, |
| 143 | .slave = &omap2420_mcspi2_hwmod, |
| 144 | .clk = "mcspi2_ick", |
| 145 | .addr = omap2420_mcspi2_addr_space, |
| 146 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), |
| 147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 148 | }; |
| 149 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 150 | /* L4_CORE -> L4_WKUP interface */ |
| 151 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 152 | .master = &omap2420_l4_core_hwmod, |
| 153 | .slave = &omap2420_l4_wkup_hwmod, |
| 154 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 155 | }; |
| 156 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 157 | /* L4 CORE -> UART1 interface */ |
| 158 | static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { |
| 159 | { |
| 160 | .pa_start = OMAP2_UART1_BASE, |
| 161 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 162 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 163 | }, |
| 164 | }; |
| 165 | |
| 166 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 167 | .master = &omap2420_l4_core_hwmod, |
| 168 | .slave = &omap2420_uart1_hwmod, |
| 169 | .clk = "uart1_ick", |
| 170 | .addr = omap2420_uart1_addr_space, |
| 171 | .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), |
| 172 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 173 | }; |
| 174 | |
| 175 | /* L4 CORE -> UART2 interface */ |
| 176 | static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { |
| 177 | { |
| 178 | .pa_start = OMAP2_UART2_BASE, |
| 179 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 180 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 181 | }, |
| 182 | }; |
| 183 | |
| 184 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 185 | .master = &omap2420_l4_core_hwmod, |
| 186 | .slave = &omap2420_uart2_hwmod, |
| 187 | .clk = "uart2_ick", |
| 188 | .addr = omap2420_uart2_addr_space, |
| 189 | .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), |
| 190 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 191 | }; |
| 192 | |
| 193 | /* L4 PER -> UART3 interface */ |
| 194 | static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { |
| 195 | { |
| 196 | .pa_start = OMAP2_UART3_BASE, |
| 197 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 198 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 199 | }, |
| 200 | }; |
| 201 | |
| 202 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 203 | .master = &omap2420_l4_core_hwmod, |
| 204 | .slave = &omap2420_uart3_hwmod, |
| 205 | .clk = "uart3_ick", |
| 206 | .addr = omap2420_uart3_addr_space, |
| 207 | .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), |
| 208 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 209 | }; |
| 210 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 211 | /* I2C IP block address space length (in bytes) */ |
| 212 | #define OMAP2_I2C_AS_LEN 128 |
| 213 | |
| 214 | /* L4 CORE -> I2C1 interface */ |
| 215 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { |
| 216 | { |
| 217 | .pa_start = 0x48070000, |
| 218 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 219 | .flags = ADDR_TYPE_RT, |
| 220 | }, |
| 221 | }; |
| 222 | |
| 223 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 224 | .master = &omap2420_l4_core_hwmod, |
| 225 | .slave = &omap2420_i2c1_hwmod, |
| 226 | .clk = "i2c1_ick", |
| 227 | .addr = omap2420_i2c1_addr_space, |
| 228 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), |
| 229 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 230 | }; |
| 231 | |
| 232 | /* L4 CORE -> I2C2 interface */ |
| 233 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { |
| 234 | { |
| 235 | .pa_start = 0x48072000, |
| 236 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 237 | .flags = ADDR_TYPE_RT, |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 242 | .master = &omap2420_l4_core_hwmod, |
| 243 | .slave = &omap2420_i2c2_hwmod, |
| 244 | .clk = "i2c2_ick", |
| 245 | .addr = omap2420_i2c2_addr_space, |
| 246 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), |
| 247 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 248 | }; |
| 249 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 250 | /* Slave interfaces on the L4_CORE interconnect */ |
| 251 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 252 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | /* Master interfaces on the L4_CORE interconnect */ |
| 256 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 257 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 258 | &omap2_l4_core__uart1, |
| 259 | &omap2_l4_core__uart2, |
| 260 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 261 | &omap2420_l4_core__i2c1, |
| 262 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 263 | }; |
| 264 | |
| 265 | /* L4 CORE */ |
| 266 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 267 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 268 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 269 | .masters = omap2420_l4_core_masters, |
| 270 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 271 | .slaves = omap2420_l4_core_slaves, |
| 272 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 273 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 274 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 275 | }; |
| 276 | |
| 277 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 278 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 279 | &omap2420_l4_core__l4_wkup, |
| 280 | }; |
| 281 | |
| 282 | /* Master interfaces on the L4_WKUP interconnect */ |
| 283 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 284 | }; |
| 285 | |
| 286 | /* L4 WKUP */ |
| 287 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 288 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 289 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 290 | .masters = omap2420_l4_wkup_masters, |
| 291 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 292 | .slaves = omap2420_l4_wkup_slaves, |
| 293 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 294 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 295 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 296 | }; |
| 297 | |
| 298 | /* Master interfaces on the MPU device */ |
| 299 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 300 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | /* MPU */ |
| 304 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 305 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 306 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 307 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 308 | .masters = omap2420_mpu_masters, |
| 309 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 311 | }; |
| 312 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 313 | /* |
| 314 | * IVA1 interface data |
| 315 | */ |
| 316 | |
| 317 | /* IVA <- L3 interface */ |
| 318 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 319 | .master = &omap2420_l3_main_hwmod, |
| 320 | .slave = &omap2420_iva_hwmod, |
| 321 | .clk = "iva1_ifck", |
| 322 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 323 | }; |
| 324 | |
| 325 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 326 | &omap2420_l3__iva, |
| 327 | }; |
| 328 | |
| 329 | /* |
| 330 | * IVA2 (IVA2) |
| 331 | */ |
| 332 | |
| 333 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 334 | .name = "iva", |
| 335 | .class = &iva_hwmod_class, |
| 336 | .masters = omap2420_iva_masters, |
| 337 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 339 | }; |
| 340 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 341 | /* Timer Common */ |
| 342 | static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { |
| 343 | .rev_offs = 0x0000, |
| 344 | .sysc_offs = 0x0010, |
| 345 | .syss_offs = 0x0014, |
| 346 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
| 347 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 348 | SYSC_HAS_AUTOIDLE), |
| 349 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 350 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 351 | }; |
| 352 | |
| 353 | static struct omap_hwmod_class omap2420_timer_hwmod_class = { |
| 354 | .name = "timer", |
| 355 | .sysc = &omap2420_timer_sysc, |
| 356 | .rev = OMAP_TIMER_IP_VERSION_1, |
| 357 | }; |
| 358 | |
| 359 | /* timer1 */ |
| 360 | static struct omap_hwmod omap2420_timer1_hwmod; |
| 361 | static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { |
| 362 | { .irq = 37, }, |
| 363 | }; |
| 364 | |
| 365 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { |
| 366 | { |
| 367 | .pa_start = 0x48028000, |
| 368 | .pa_end = 0x48028000 + SZ_1K - 1, |
| 369 | .flags = ADDR_TYPE_RT |
| 370 | }, |
| 371 | }; |
| 372 | |
| 373 | /* l4_wkup -> timer1 */ |
| 374 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { |
| 375 | .master = &omap2420_l4_wkup_hwmod, |
| 376 | .slave = &omap2420_timer1_hwmod, |
| 377 | .clk = "gpt1_ick", |
| 378 | .addr = omap2420_timer1_addrs, |
| 379 | .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), |
| 380 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 381 | }; |
| 382 | |
| 383 | /* timer1 slave port */ |
| 384 | static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { |
| 385 | &omap2420_l4_wkup__timer1, |
| 386 | }; |
| 387 | |
| 388 | /* timer1 hwmod */ |
| 389 | static struct omap_hwmod omap2420_timer1_hwmod = { |
| 390 | .name = "timer1", |
| 391 | .mpu_irqs = omap2420_timer1_mpu_irqs, |
| 392 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), |
| 393 | .main_clk = "gpt1_fck", |
| 394 | .prcm = { |
| 395 | .omap2 = { |
| 396 | .prcm_reg_id = 1, |
| 397 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 398 | .module_offs = WKUP_MOD, |
| 399 | .idlest_reg_id = 1, |
| 400 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, |
| 401 | }, |
| 402 | }, |
| 403 | .slaves = omap2420_timer1_slaves, |
| 404 | .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), |
| 405 | .class = &omap2420_timer_hwmod_class, |
| 406 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 407 | }; |
| 408 | |
| 409 | /* timer2 */ |
| 410 | static struct omap_hwmod omap2420_timer2_hwmod; |
| 411 | static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { |
| 412 | { .irq = 38, }, |
| 413 | }; |
| 414 | |
| 415 | static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { |
| 416 | { |
| 417 | .pa_start = 0x4802a000, |
| 418 | .pa_end = 0x4802a000 + SZ_1K - 1, |
| 419 | .flags = ADDR_TYPE_RT |
| 420 | }, |
| 421 | }; |
| 422 | |
| 423 | /* l4_core -> timer2 */ |
| 424 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { |
| 425 | .master = &omap2420_l4_core_hwmod, |
| 426 | .slave = &omap2420_timer2_hwmod, |
| 427 | .clk = "gpt2_ick", |
| 428 | .addr = omap2420_timer2_addrs, |
| 429 | .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), |
| 430 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 431 | }; |
| 432 | |
| 433 | /* timer2 slave port */ |
| 434 | static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { |
| 435 | &omap2420_l4_core__timer2, |
| 436 | }; |
| 437 | |
| 438 | /* timer2 hwmod */ |
| 439 | static struct omap_hwmod omap2420_timer2_hwmod = { |
| 440 | .name = "timer2", |
| 441 | .mpu_irqs = omap2420_timer2_mpu_irqs, |
| 442 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), |
| 443 | .main_clk = "gpt2_fck", |
| 444 | .prcm = { |
| 445 | .omap2 = { |
| 446 | .prcm_reg_id = 1, |
| 447 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 448 | .module_offs = CORE_MOD, |
| 449 | .idlest_reg_id = 1, |
| 450 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, |
| 451 | }, |
| 452 | }, |
| 453 | .slaves = omap2420_timer2_slaves, |
| 454 | .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), |
| 455 | .class = &omap2420_timer_hwmod_class, |
| 456 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 457 | }; |
| 458 | |
| 459 | /* timer3 */ |
| 460 | static struct omap_hwmod omap2420_timer3_hwmod; |
| 461 | static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { |
| 462 | { .irq = 39, }, |
| 463 | }; |
| 464 | |
| 465 | static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { |
| 466 | { |
| 467 | .pa_start = 0x48078000, |
| 468 | .pa_end = 0x48078000 + SZ_1K - 1, |
| 469 | .flags = ADDR_TYPE_RT |
| 470 | }, |
| 471 | }; |
| 472 | |
| 473 | /* l4_core -> timer3 */ |
| 474 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { |
| 475 | .master = &omap2420_l4_core_hwmod, |
| 476 | .slave = &omap2420_timer3_hwmod, |
| 477 | .clk = "gpt3_ick", |
| 478 | .addr = omap2420_timer3_addrs, |
| 479 | .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), |
| 480 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 481 | }; |
| 482 | |
| 483 | /* timer3 slave port */ |
| 484 | static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { |
| 485 | &omap2420_l4_core__timer3, |
| 486 | }; |
| 487 | |
| 488 | /* timer3 hwmod */ |
| 489 | static struct omap_hwmod omap2420_timer3_hwmod = { |
| 490 | .name = "timer3", |
| 491 | .mpu_irqs = omap2420_timer3_mpu_irqs, |
| 492 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), |
| 493 | .main_clk = "gpt3_fck", |
| 494 | .prcm = { |
| 495 | .omap2 = { |
| 496 | .prcm_reg_id = 1, |
| 497 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 498 | .module_offs = CORE_MOD, |
| 499 | .idlest_reg_id = 1, |
| 500 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, |
| 501 | }, |
| 502 | }, |
| 503 | .slaves = omap2420_timer3_slaves, |
| 504 | .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), |
| 505 | .class = &omap2420_timer_hwmod_class, |
| 506 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 507 | }; |
| 508 | |
| 509 | /* timer4 */ |
| 510 | static struct omap_hwmod omap2420_timer4_hwmod; |
| 511 | static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { |
| 512 | { .irq = 40, }, |
| 513 | }; |
| 514 | |
| 515 | static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { |
| 516 | { |
| 517 | .pa_start = 0x4807a000, |
| 518 | .pa_end = 0x4807a000 + SZ_1K - 1, |
| 519 | .flags = ADDR_TYPE_RT |
| 520 | }, |
| 521 | }; |
| 522 | |
| 523 | /* l4_core -> timer4 */ |
| 524 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { |
| 525 | .master = &omap2420_l4_core_hwmod, |
| 526 | .slave = &omap2420_timer4_hwmod, |
| 527 | .clk = "gpt4_ick", |
| 528 | .addr = omap2420_timer4_addrs, |
| 529 | .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), |
| 530 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 531 | }; |
| 532 | |
| 533 | /* timer4 slave port */ |
| 534 | static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { |
| 535 | &omap2420_l4_core__timer4, |
| 536 | }; |
| 537 | |
| 538 | /* timer4 hwmod */ |
| 539 | static struct omap_hwmod omap2420_timer4_hwmod = { |
| 540 | .name = "timer4", |
| 541 | .mpu_irqs = omap2420_timer4_mpu_irqs, |
| 542 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), |
| 543 | .main_clk = "gpt4_fck", |
| 544 | .prcm = { |
| 545 | .omap2 = { |
| 546 | .prcm_reg_id = 1, |
| 547 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 548 | .module_offs = CORE_MOD, |
| 549 | .idlest_reg_id = 1, |
| 550 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, |
| 551 | }, |
| 552 | }, |
| 553 | .slaves = omap2420_timer4_slaves, |
| 554 | .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), |
| 555 | .class = &omap2420_timer_hwmod_class, |
| 556 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 557 | }; |
| 558 | |
| 559 | /* timer5 */ |
| 560 | static struct omap_hwmod omap2420_timer5_hwmod; |
| 561 | static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { |
| 562 | { .irq = 41, }, |
| 563 | }; |
| 564 | |
| 565 | static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { |
| 566 | { |
| 567 | .pa_start = 0x4807c000, |
| 568 | .pa_end = 0x4807c000 + SZ_1K - 1, |
| 569 | .flags = ADDR_TYPE_RT |
| 570 | }, |
| 571 | }; |
| 572 | |
| 573 | /* l4_core -> timer5 */ |
| 574 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { |
| 575 | .master = &omap2420_l4_core_hwmod, |
| 576 | .slave = &omap2420_timer5_hwmod, |
| 577 | .clk = "gpt5_ick", |
| 578 | .addr = omap2420_timer5_addrs, |
| 579 | .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), |
| 580 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 581 | }; |
| 582 | |
| 583 | /* timer5 slave port */ |
| 584 | static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { |
| 585 | &omap2420_l4_core__timer5, |
| 586 | }; |
| 587 | |
| 588 | /* timer5 hwmod */ |
| 589 | static struct omap_hwmod omap2420_timer5_hwmod = { |
| 590 | .name = "timer5", |
| 591 | .mpu_irqs = omap2420_timer5_mpu_irqs, |
| 592 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), |
| 593 | .main_clk = "gpt5_fck", |
| 594 | .prcm = { |
| 595 | .omap2 = { |
| 596 | .prcm_reg_id = 1, |
| 597 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 598 | .module_offs = CORE_MOD, |
| 599 | .idlest_reg_id = 1, |
| 600 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, |
| 601 | }, |
| 602 | }, |
| 603 | .slaves = omap2420_timer5_slaves, |
| 604 | .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), |
| 605 | .class = &omap2420_timer_hwmod_class, |
| 606 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 607 | }; |
| 608 | |
| 609 | |
| 610 | /* timer6 */ |
| 611 | static struct omap_hwmod omap2420_timer6_hwmod; |
| 612 | static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { |
| 613 | { .irq = 42, }, |
| 614 | }; |
| 615 | |
| 616 | static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { |
| 617 | { |
| 618 | .pa_start = 0x4807e000, |
| 619 | .pa_end = 0x4807e000 + SZ_1K - 1, |
| 620 | .flags = ADDR_TYPE_RT |
| 621 | }, |
| 622 | }; |
| 623 | |
| 624 | /* l4_core -> timer6 */ |
| 625 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { |
| 626 | .master = &omap2420_l4_core_hwmod, |
| 627 | .slave = &omap2420_timer6_hwmod, |
| 628 | .clk = "gpt6_ick", |
| 629 | .addr = omap2420_timer6_addrs, |
| 630 | .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), |
| 631 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 632 | }; |
| 633 | |
| 634 | /* timer6 slave port */ |
| 635 | static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { |
| 636 | &omap2420_l4_core__timer6, |
| 637 | }; |
| 638 | |
| 639 | /* timer6 hwmod */ |
| 640 | static struct omap_hwmod omap2420_timer6_hwmod = { |
| 641 | .name = "timer6", |
| 642 | .mpu_irqs = omap2420_timer6_mpu_irqs, |
| 643 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), |
| 644 | .main_clk = "gpt6_fck", |
| 645 | .prcm = { |
| 646 | .omap2 = { |
| 647 | .prcm_reg_id = 1, |
| 648 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 649 | .module_offs = CORE_MOD, |
| 650 | .idlest_reg_id = 1, |
| 651 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, |
| 652 | }, |
| 653 | }, |
| 654 | .slaves = omap2420_timer6_slaves, |
| 655 | .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), |
| 656 | .class = &omap2420_timer_hwmod_class, |
| 657 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 658 | }; |
| 659 | |
| 660 | /* timer7 */ |
| 661 | static struct omap_hwmod omap2420_timer7_hwmod; |
| 662 | static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { |
| 663 | { .irq = 43, }, |
| 664 | }; |
| 665 | |
| 666 | static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { |
| 667 | { |
| 668 | .pa_start = 0x48080000, |
| 669 | .pa_end = 0x48080000 + SZ_1K - 1, |
| 670 | .flags = ADDR_TYPE_RT |
| 671 | }, |
| 672 | }; |
| 673 | |
| 674 | /* l4_core -> timer7 */ |
| 675 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { |
| 676 | .master = &omap2420_l4_core_hwmod, |
| 677 | .slave = &omap2420_timer7_hwmod, |
| 678 | .clk = "gpt7_ick", |
| 679 | .addr = omap2420_timer7_addrs, |
| 680 | .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), |
| 681 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 682 | }; |
| 683 | |
| 684 | /* timer7 slave port */ |
| 685 | static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { |
| 686 | &omap2420_l4_core__timer7, |
| 687 | }; |
| 688 | |
| 689 | /* timer7 hwmod */ |
| 690 | static struct omap_hwmod omap2420_timer7_hwmod = { |
| 691 | .name = "timer7", |
| 692 | .mpu_irqs = omap2420_timer7_mpu_irqs, |
| 693 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), |
| 694 | .main_clk = "gpt7_fck", |
| 695 | .prcm = { |
| 696 | .omap2 = { |
| 697 | .prcm_reg_id = 1, |
| 698 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 699 | .module_offs = CORE_MOD, |
| 700 | .idlest_reg_id = 1, |
| 701 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, |
| 702 | }, |
| 703 | }, |
| 704 | .slaves = omap2420_timer7_slaves, |
| 705 | .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), |
| 706 | .class = &omap2420_timer_hwmod_class, |
| 707 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 708 | }; |
| 709 | |
| 710 | /* timer8 */ |
| 711 | static struct omap_hwmod omap2420_timer8_hwmod; |
| 712 | static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { |
| 713 | { .irq = 44, }, |
| 714 | }; |
| 715 | |
| 716 | static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { |
| 717 | { |
| 718 | .pa_start = 0x48082000, |
| 719 | .pa_end = 0x48082000 + SZ_1K - 1, |
| 720 | .flags = ADDR_TYPE_RT |
| 721 | }, |
| 722 | }; |
| 723 | |
| 724 | /* l4_core -> timer8 */ |
| 725 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { |
| 726 | .master = &omap2420_l4_core_hwmod, |
| 727 | .slave = &omap2420_timer8_hwmod, |
| 728 | .clk = "gpt8_ick", |
| 729 | .addr = omap2420_timer8_addrs, |
| 730 | .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), |
| 731 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 732 | }; |
| 733 | |
| 734 | /* timer8 slave port */ |
| 735 | static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { |
| 736 | &omap2420_l4_core__timer8, |
| 737 | }; |
| 738 | |
| 739 | /* timer8 hwmod */ |
| 740 | static struct omap_hwmod omap2420_timer8_hwmod = { |
| 741 | .name = "timer8", |
| 742 | .mpu_irqs = omap2420_timer8_mpu_irqs, |
| 743 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), |
| 744 | .main_clk = "gpt8_fck", |
| 745 | .prcm = { |
| 746 | .omap2 = { |
| 747 | .prcm_reg_id = 1, |
| 748 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 749 | .module_offs = CORE_MOD, |
| 750 | .idlest_reg_id = 1, |
| 751 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, |
| 752 | }, |
| 753 | }, |
| 754 | .slaves = omap2420_timer8_slaves, |
| 755 | .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), |
| 756 | .class = &omap2420_timer_hwmod_class, |
| 757 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 758 | }; |
| 759 | |
| 760 | /* timer9 */ |
| 761 | static struct omap_hwmod omap2420_timer9_hwmod; |
| 762 | static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { |
| 763 | { .irq = 45, }, |
| 764 | }; |
| 765 | |
| 766 | static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { |
| 767 | { |
| 768 | .pa_start = 0x48084000, |
| 769 | .pa_end = 0x48084000 + SZ_1K - 1, |
| 770 | .flags = ADDR_TYPE_RT |
| 771 | }, |
| 772 | }; |
| 773 | |
| 774 | /* l4_core -> timer9 */ |
| 775 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { |
| 776 | .master = &omap2420_l4_core_hwmod, |
| 777 | .slave = &omap2420_timer9_hwmod, |
| 778 | .clk = "gpt9_ick", |
| 779 | .addr = omap2420_timer9_addrs, |
| 780 | .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), |
| 781 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 782 | }; |
| 783 | |
| 784 | /* timer9 slave port */ |
| 785 | static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { |
| 786 | &omap2420_l4_core__timer9, |
| 787 | }; |
| 788 | |
| 789 | /* timer9 hwmod */ |
| 790 | static struct omap_hwmod omap2420_timer9_hwmod = { |
| 791 | .name = "timer9", |
| 792 | .mpu_irqs = omap2420_timer9_mpu_irqs, |
| 793 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), |
| 794 | .main_clk = "gpt9_fck", |
| 795 | .prcm = { |
| 796 | .omap2 = { |
| 797 | .prcm_reg_id = 1, |
| 798 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 799 | .module_offs = CORE_MOD, |
| 800 | .idlest_reg_id = 1, |
| 801 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, |
| 802 | }, |
| 803 | }, |
| 804 | .slaves = omap2420_timer9_slaves, |
| 805 | .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), |
| 806 | .class = &omap2420_timer_hwmod_class, |
| 807 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 808 | }; |
| 809 | |
| 810 | /* timer10 */ |
| 811 | static struct omap_hwmod omap2420_timer10_hwmod; |
| 812 | static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { |
| 813 | { .irq = 46, }, |
| 814 | }; |
| 815 | |
| 816 | static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { |
| 817 | { |
| 818 | .pa_start = 0x48086000, |
| 819 | .pa_end = 0x48086000 + SZ_1K - 1, |
| 820 | .flags = ADDR_TYPE_RT |
| 821 | }, |
| 822 | }; |
| 823 | |
| 824 | /* l4_core -> timer10 */ |
| 825 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { |
| 826 | .master = &omap2420_l4_core_hwmod, |
| 827 | .slave = &omap2420_timer10_hwmod, |
| 828 | .clk = "gpt10_ick", |
| 829 | .addr = omap2420_timer10_addrs, |
| 830 | .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), |
| 831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 832 | }; |
| 833 | |
| 834 | /* timer10 slave port */ |
| 835 | static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { |
| 836 | &omap2420_l4_core__timer10, |
| 837 | }; |
| 838 | |
| 839 | /* timer10 hwmod */ |
| 840 | static struct omap_hwmod omap2420_timer10_hwmod = { |
| 841 | .name = "timer10", |
| 842 | .mpu_irqs = omap2420_timer10_mpu_irqs, |
| 843 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), |
| 844 | .main_clk = "gpt10_fck", |
| 845 | .prcm = { |
| 846 | .omap2 = { |
| 847 | .prcm_reg_id = 1, |
| 848 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 849 | .module_offs = CORE_MOD, |
| 850 | .idlest_reg_id = 1, |
| 851 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, |
| 852 | }, |
| 853 | }, |
| 854 | .slaves = omap2420_timer10_slaves, |
| 855 | .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), |
| 856 | .class = &omap2420_timer_hwmod_class, |
| 857 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 858 | }; |
| 859 | |
| 860 | /* timer11 */ |
| 861 | static struct omap_hwmod omap2420_timer11_hwmod; |
| 862 | static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { |
| 863 | { .irq = 47, }, |
| 864 | }; |
| 865 | |
| 866 | static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { |
| 867 | { |
| 868 | .pa_start = 0x48088000, |
| 869 | .pa_end = 0x48088000 + SZ_1K - 1, |
| 870 | .flags = ADDR_TYPE_RT |
| 871 | }, |
| 872 | }; |
| 873 | |
| 874 | /* l4_core -> timer11 */ |
| 875 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { |
| 876 | .master = &omap2420_l4_core_hwmod, |
| 877 | .slave = &omap2420_timer11_hwmod, |
| 878 | .clk = "gpt11_ick", |
| 879 | .addr = omap2420_timer11_addrs, |
| 880 | .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), |
| 881 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 882 | }; |
| 883 | |
| 884 | /* timer11 slave port */ |
| 885 | static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { |
| 886 | &omap2420_l4_core__timer11, |
| 887 | }; |
| 888 | |
| 889 | /* timer11 hwmod */ |
| 890 | static struct omap_hwmod omap2420_timer11_hwmod = { |
| 891 | .name = "timer11", |
| 892 | .mpu_irqs = omap2420_timer11_mpu_irqs, |
| 893 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), |
| 894 | .main_clk = "gpt11_fck", |
| 895 | .prcm = { |
| 896 | .omap2 = { |
| 897 | .prcm_reg_id = 1, |
| 898 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 899 | .module_offs = CORE_MOD, |
| 900 | .idlest_reg_id = 1, |
| 901 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, |
| 902 | }, |
| 903 | }, |
| 904 | .slaves = omap2420_timer11_slaves, |
| 905 | .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), |
| 906 | .class = &omap2420_timer_hwmod_class, |
| 907 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 908 | }; |
| 909 | |
| 910 | /* timer12 */ |
| 911 | static struct omap_hwmod omap2420_timer12_hwmod; |
| 912 | static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { |
| 913 | { .irq = 48, }, |
| 914 | }; |
| 915 | |
| 916 | static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { |
| 917 | { |
| 918 | .pa_start = 0x4808a000, |
| 919 | .pa_end = 0x4808a000 + SZ_1K - 1, |
| 920 | .flags = ADDR_TYPE_RT |
| 921 | }, |
| 922 | }; |
| 923 | |
| 924 | /* l4_core -> timer12 */ |
| 925 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { |
| 926 | .master = &omap2420_l4_core_hwmod, |
| 927 | .slave = &omap2420_timer12_hwmod, |
| 928 | .clk = "gpt12_ick", |
| 929 | .addr = omap2420_timer12_addrs, |
| 930 | .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), |
| 931 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 932 | }; |
| 933 | |
| 934 | /* timer12 slave port */ |
| 935 | static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { |
| 936 | &omap2420_l4_core__timer12, |
| 937 | }; |
| 938 | |
| 939 | /* timer12 hwmod */ |
| 940 | static struct omap_hwmod omap2420_timer12_hwmod = { |
| 941 | .name = "timer12", |
| 942 | .mpu_irqs = omap2420_timer12_mpu_irqs, |
| 943 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), |
| 944 | .main_clk = "gpt12_fck", |
| 945 | .prcm = { |
| 946 | .omap2 = { |
| 947 | .prcm_reg_id = 1, |
| 948 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 949 | .module_offs = CORE_MOD, |
| 950 | .idlest_reg_id = 1, |
| 951 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, |
| 952 | }, |
| 953 | }, |
| 954 | .slaves = omap2420_timer12_slaves, |
| 955 | .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), |
| 956 | .class = &omap2420_timer_hwmod_class, |
| 957 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 958 | }; |
| 959 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 960 | /* l4_wkup -> wd_timer2 */ |
| 961 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 962 | { |
| 963 | .pa_start = 0x48022000, |
| 964 | .pa_end = 0x4802207f, |
| 965 | .flags = ADDR_TYPE_RT |
| 966 | }, |
| 967 | }; |
| 968 | |
| 969 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 970 | .master = &omap2420_l4_wkup_hwmod, |
| 971 | .slave = &omap2420_wd_timer2_hwmod, |
| 972 | .clk = "mpu_wdt_ick", |
| 973 | .addr = omap2420_wd_timer2_addrs, |
| 974 | .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), |
| 975 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 976 | }; |
| 977 | |
| 978 | /* |
| 979 | * 'wd_timer' class |
| 980 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 981 | * overflow condition |
| 982 | */ |
| 983 | |
| 984 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 985 | .rev_offs = 0x0000, |
| 986 | .sysc_offs = 0x0010, |
| 987 | .syss_offs = 0x0014, |
| 988 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 989 | SYSC_HAS_AUTOIDLE), |
| 990 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 991 | }; |
| 992 | |
| 993 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 994 | .name = "wd_timer", |
| 995 | .sysc = &omap2420_wd_timer_sysc, |
| 996 | .pre_shutdown = &omap2_wd_timer_disable |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 997 | }; |
| 998 | |
| 999 | /* wd_timer2 */ |
| 1000 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 1001 | &omap2420_l4_wkup__wd_timer2, |
| 1002 | }; |
| 1003 | |
| 1004 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 1005 | .name = "wd_timer2", |
| 1006 | .class = &omap2420_wd_timer_hwmod_class, |
| 1007 | .main_clk = "mpu_wdt_fck", |
| 1008 | .prcm = { |
| 1009 | .omap2 = { |
| 1010 | .prcm_reg_id = 1, |
| 1011 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1012 | .module_offs = WKUP_MOD, |
| 1013 | .idlest_reg_id = 1, |
| 1014 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 1015 | }, |
| 1016 | }, |
| 1017 | .slaves = omap2420_wd_timer2_slaves, |
| 1018 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 1019 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1020 | }; |
| 1021 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1022 | /* UART */ |
| 1023 | |
| 1024 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 1025 | .rev_offs = 0x50, |
| 1026 | .sysc_offs = 0x54, |
| 1027 | .syss_offs = 0x58, |
| 1028 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 1029 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1030 | SYSC_HAS_AUTOIDLE), |
| 1031 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1032 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1033 | }; |
| 1034 | |
| 1035 | static struct omap_hwmod_class uart_class = { |
| 1036 | .name = "uart", |
| 1037 | .sysc = &uart_sysc, |
| 1038 | }; |
| 1039 | |
| 1040 | /* UART1 */ |
| 1041 | |
| 1042 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 1043 | { .irq = INT_24XX_UART1_IRQ, }, |
| 1044 | }; |
| 1045 | |
| 1046 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 1047 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 1048 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 1049 | }; |
| 1050 | |
| 1051 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 1052 | &omap2_l4_core__uart1, |
| 1053 | }; |
| 1054 | |
| 1055 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 1056 | .name = "uart1", |
| 1057 | .mpu_irqs = uart1_mpu_irqs, |
| 1058 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 1059 | .sdma_reqs = uart1_sdma_reqs, |
| 1060 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 1061 | .main_clk = "uart1_fck", |
| 1062 | .prcm = { |
| 1063 | .omap2 = { |
| 1064 | .module_offs = CORE_MOD, |
| 1065 | .prcm_reg_id = 1, |
| 1066 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1067 | .idlest_reg_id = 1, |
| 1068 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1069 | }, |
| 1070 | }, |
| 1071 | .slaves = omap2420_uart1_slaves, |
| 1072 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 1073 | .class = &uart_class, |
| 1074 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1075 | }; |
| 1076 | |
| 1077 | /* UART2 */ |
| 1078 | |
| 1079 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 1080 | { .irq = INT_24XX_UART2_IRQ, }, |
| 1081 | }; |
| 1082 | |
| 1083 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 1084 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 1085 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 1086 | }; |
| 1087 | |
| 1088 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 1089 | &omap2_l4_core__uart2, |
| 1090 | }; |
| 1091 | |
| 1092 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 1093 | .name = "uart2", |
| 1094 | .mpu_irqs = uart2_mpu_irqs, |
| 1095 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 1096 | .sdma_reqs = uart2_sdma_reqs, |
| 1097 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 1098 | .main_clk = "uart2_fck", |
| 1099 | .prcm = { |
| 1100 | .omap2 = { |
| 1101 | .module_offs = CORE_MOD, |
| 1102 | .prcm_reg_id = 1, |
| 1103 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1104 | .idlest_reg_id = 1, |
| 1105 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1106 | }, |
| 1107 | }, |
| 1108 | .slaves = omap2420_uart2_slaves, |
| 1109 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 1110 | .class = &uart_class, |
| 1111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1112 | }; |
| 1113 | |
| 1114 | /* UART3 */ |
| 1115 | |
| 1116 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 1117 | { .irq = INT_24XX_UART3_IRQ, }, |
| 1118 | }; |
| 1119 | |
| 1120 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 1121 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 1122 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 1123 | }; |
| 1124 | |
| 1125 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 1126 | &omap2_l4_core__uart3, |
| 1127 | }; |
| 1128 | |
| 1129 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 1130 | .name = "uart3", |
| 1131 | .mpu_irqs = uart3_mpu_irqs, |
| 1132 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 1133 | .sdma_reqs = uart3_sdma_reqs, |
| 1134 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 1135 | .main_clk = "uart3_fck", |
| 1136 | .prcm = { |
| 1137 | .omap2 = { |
| 1138 | .module_offs = CORE_MOD, |
| 1139 | .prcm_reg_id = 2, |
| 1140 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1141 | .idlest_reg_id = 2, |
| 1142 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1143 | }, |
| 1144 | }, |
| 1145 | .slaves = omap2420_uart3_slaves, |
| 1146 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 1147 | .class = &uart_class, |
| 1148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1149 | }; |
| 1150 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1151 | /* |
| 1152 | * 'dss' class |
| 1153 | * display sub-system |
| 1154 | */ |
| 1155 | |
| 1156 | static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { |
| 1157 | .rev_offs = 0x0000, |
| 1158 | .sysc_offs = 0x0010, |
| 1159 | .syss_offs = 0x0014, |
| 1160 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1161 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1162 | }; |
| 1163 | |
| 1164 | static struct omap_hwmod_class omap2420_dss_hwmod_class = { |
| 1165 | .name = "dss", |
| 1166 | .sysc = &omap2420_dss_sysc, |
| 1167 | }; |
| 1168 | |
| 1169 | /* dss */ |
| 1170 | static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { |
| 1171 | { .irq = 25 }, |
| 1172 | }; |
| 1173 | |
| 1174 | static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { |
| 1175 | { .name = "dispc", .dma_req = 5 }, |
| 1176 | }; |
| 1177 | |
| 1178 | /* dss */ |
| 1179 | /* dss master ports */ |
| 1180 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { |
| 1181 | &omap2420_dss__l3, |
| 1182 | }; |
| 1183 | |
| 1184 | static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { |
| 1185 | { |
| 1186 | .pa_start = 0x48050000, |
| 1187 | .pa_end = 0x480503FF, |
| 1188 | .flags = ADDR_TYPE_RT |
| 1189 | }, |
| 1190 | }; |
| 1191 | |
| 1192 | /* l4_core -> dss */ |
| 1193 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { |
| 1194 | .master = &omap2420_l4_core_hwmod, |
| 1195 | .slave = &omap2420_dss_core_hwmod, |
| 1196 | .clk = "dss_ick", |
| 1197 | .addr = omap2420_dss_addrs, |
| 1198 | .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), |
| 1199 | .fw = { |
| 1200 | .omap2 = { |
| 1201 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 1202 | .flags = OMAP_FIREWALL_L4, |
| 1203 | } |
| 1204 | }, |
| 1205 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1206 | }; |
| 1207 | |
| 1208 | /* dss slave ports */ |
| 1209 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { |
| 1210 | &omap2420_l4_core__dss, |
| 1211 | }; |
| 1212 | |
| 1213 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
| 1214 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
| 1215 | { .role = "sys_clk", .clk = "dss2_fck" }, |
| 1216 | }; |
| 1217 | |
| 1218 | static struct omap_hwmod omap2420_dss_core_hwmod = { |
| 1219 | .name = "dss_core", |
| 1220 | .class = &omap2420_dss_hwmod_class, |
| 1221 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
| 1222 | .mpu_irqs = omap2420_dss_irqs, |
| 1223 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), |
| 1224 | .sdma_reqs = omap2420_dss_sdma_chs, |
| 1225 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), |
| 1226 | .prcm = { |
| 1227 | .omap2 = { |
| 1228 | .prcm_reg_id = 1, |
| 1229 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1230 | .module_offs = CORE_MOD, |
| 1231 | .idlest_reg_id = 1, |
| 1232 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 1233 | }, |
| 1234 | }, |
| 1235 | .opt_clks = dss_opt_clks, |
| 1236 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
| 1237 | .slaves = omap2420_dss_slaves, |
| 1238 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), |
| 1239 | .masters = omap2420_dss_masters, |
| 1240 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), |
| 1241 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1242 | .flags = HWMOD_NO_IDLEST, |
| 1243 | }; |
| 1244 | |
| 1245 | /* |
| 1246 | * 'dispc' class |
| 1247 | * display controller |
| 1248 | */ |
| 1249 | |
| 1250 | static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { |
| 1251 | .rev_offs = 0x0000, |
| 1252 | .sysc_offs = 0x0010, |
| 1253 | .syss_offs = 0x0014, |
| 1254 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 1255 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1256 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1257 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1258 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1259 | }; |
| 1260 | |
| 1261 | static struct omap_hwmod_class omap2420_dispc_hwmod_class = { |
| 1262 | .name = "dispc", |
| 1263 | .sysc = &omap2420_dispc_sysc, |
| 1264 | }; |
| 1265 | |
| 1266 | static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { |
| 1267 | { |
| 1268 | .pa_start = 0x48050400, |
| 1269 | .pa_end = 0x480507FF, |
| 1270 | .flags = ADDR_TYPE_RT |
| 1271 | }, |
| 1272 | }; |
| 1273 | |
| 1274 | /* l4_core -> dss_dispc */ |
| 1275 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { |
| 1276 | .master = &omap2420_l4_core_hwmod, |
| 1277 | .slave = &omap2420_dss_dispc_hwmod, |
| 1278 | .clk = "dss_ick", |
| 1279 | .addr = omap2420_dss_dispc_addrs, |
| 1280 | .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), |
| 1281 | .fw = { |
| 1282 | .omap2 = { |
| 1283 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 1284 | .flags = OMAP_FIREWALL_L4, |
| 1285 | } |
| 1286 | }, |
| 1287 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1288 | }; |
| 1289 | |
| 1290 | /* dss_dispc slave ports */ |
| 1291 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { |
| 1292 | &omap2420_l4_core__dss_dispc, |
| 1293 | }; |
| 1294 | |
| 1295 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { |
| 1296 | .name = "dss_dispc", |
| 1297 | .class = &omap2420_dispc_hwmod_class, |
| 1298 | .main_clk = "dss1_fck", |
| 1299 | .prcm = { |
| 1300 | .omap2 = { |
| 1301 | .prcm_reg_id = 1, |
| 1302 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1303 | .module_offs = CORE_MOD, |
| 1304 | .idlest_reg_id = 1, |
| 1305 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 1306 | }, |
| 1307 | }, |
| 1308 | .slaves = omap2420_dss_dispc_slaves, |
| 1309 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), |
| 1310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1311 | .flags = HWMOD_NO_IDLEST, |
| 1312 | }; |
| 1313 | |
| 1314 | /* |
| 1315 | * 'rfbi' class |
| 1316 | * remote frame buffer interface |
| 1317 | */ |
| 1318 | |
| 1319 | static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { |
| 1320 | .rev_offs = 0x0000, |
| 1321 | .sysc_offs = 0x0010, |
| 1322 | .syss_offs = 0x0014, |
| 1323 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 1324 | SYSC_HAS_AUTOIDLE), |
| 1325 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1326 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1327 | }; |
| 1328 | |
| 1329 | static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { |
| 1330 | .name = "rfbi", |
| 1331 | .sysc = &omap2420_rfbi_sysc, |
| 1332 | }; |
| 1333 | |
| 1334 | static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { |
| 1335 | { |
| 1336 | .pa_start = 0x48050800, |
| 1337 | .pa_end = 0x48050BFF, |
| 1338 | .flags = ADDR_TYPE_RT |
| 1339 | }, |
| 1340 | }; |
| 1341 | |
| 1342 | /* l4_core -> dss_rfbi */ |
| 1343 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { |
| 1344 | .master = &omap2420_l4_core_hwmod, |
| 1345 | .slave = &omap2420_dss_rfbi_hwmod, |
| 1346 | .clk = "dss_ick", |
| 1347 | .addr = omap2420_dss_rfbi_addrs, |
| 1348 | .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), |
| 1349 | .fw = { |
| 1350 | .omap2 = { |
| 1351 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 1352 | .flags = OMAP_FIREWALL_L4, |
| 1353 | } |
| 1354 | }, |
| 1355 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1356 | }; |
| 1357 | |
| 1358 | /* dss_rfbi slave ports */ |
| 1359 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { |
| 1360 | &omap2420_l4_core__dss_rfbi, |
| 1361 | }; |
| 1362 | |
| 1363 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { |
| 1364 | .name = "dss_rfbi", |
| 1365 | .class = &omap2420_rfbi_hwmod_class, |
| 1366 | .main_clk = "dss1_fck", |
| 1367 | .prcm = { |
| 1368 | .omap2 = { |
| 1369 | .prcm_reg_id = 1, |
| 1370 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1371 | .module_offs = CORE_MOD, |
| 1372 | }, |
| 1373 | }, |
| 1374 | .slaves = omap2420_dss_rfbi_slaves, |
| 1375 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), |
| 1376 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1377 | .flags = HWMOD_NO_IDLEST, |
| 1378 | }; |
| 1379 | |
| 1380 | /* |
| 1381 | * 'venc' class |
| 1382 | * video encoder |
| 1383 | */ |
| 1384 | |
| 1385 | static struct omap_hwmod_class omap2420_venc_hwmod_class = { |
| 1386 | .name = "venc", |
| 1387 | }; |
| 1388 | |
| 1389 | /* dss_venc */ |
| 1390 | static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { |
| 1391 | { |
| 1392 | .pa_start = 0x48050C00, |
| 1393 | .pa_end = 0x48050FFF, |
| 1394 | .flags = ADDR_TYPE_RT |
| 1395 | }, |
| 1396 | }; |
| 1397 | |
| 1398 | /* l4_core -> dss_venc */ |
| 1399 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { |
| 1400 | .master = &omap2420_l4_core_hwmod, |
| 1401 | .slave = &omap2420_dss_venc_hwmod, |
| 1402 | .clk = "dss_54m_fck", |
| 1403 | .addr = omap2420_dss_venc_addrs, |
| 1404 | .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), |
| 1405 | .fw = { |
| 1406 | .omap2 = { |
| 1407 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 1408 | .flags = OMAP_FIREWALL_L4, |
| 1409 | } |
| 1410 | }, |
| 1411 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1412 | }; |
| 1413 | |
| 1414 | /* dss_venc slave ports */ |
| 1415 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { |
| 1416 | &omap2420_l4_core__dss_venc, |
| 1417 | }; |
| 1418 | |
| 1419 | static struct omap_hwmod omap2420_dss_venc_hwmod = { |
| 1420 | .name = "dss_venc", |
| 1421 | .class = &omap2420_venc_hwmod_class, |
| 1422 | .main_clk = "dss1_fck", |
| 1423 | .prcm = { |
| 1424 | .omap2 = { |
| 1425 | .prcm_reg_id = 1, |
| 1426 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1427 | .module_offs = CORE_MOD, |
| 1428 | }, |
| 1429 | }, |
| 1430 | .slaves = omap2420_dss_venc_slaves, |
| 1431 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), |
| 1432 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1433 | .flags = HWMOD_NO_IDLEST, |
| 1434 | }; |
| 1435 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1436 | /* I2C common */ |
| 1437 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 1438 | .rev_offs = 0x00, |
| 1439 | .sysc_offs = 0x20, |
| 1440 | .syss_offs = 0x10, |
| 1441 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 1442 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1443 | }; |
| 1444 | |
| 1445 | static struct omap_hwmod_class i2c_class = { |
| 1446 | .name = "i2c", |
| 1447 | .sysc = &i2c_sysc, |
| 1448 | }; |
| 1449 | |
| 1450 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 1451 | |
| 1452 | /* I2C1 */ |
| 1453 | |
| 1454 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 1455 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 1456 | }; |
| 1457 | |
| 1458 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 1459 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 1460 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 1461 | }; |
| 1462 | |
| 1463 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 1464 | &omap2420_l4_core__i2c1, |
| 1465 | }; |
| 1466 | |
| 1467 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 1468 | .name = "i2c1", |
| 1469 | .mpu_irqs = i2c1_mpu_irqs, |
| 1470 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 1471 | .sdma_reqs = i2c1_sdma_reqs, |
| 1472 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 1473 | .main_clk = "i2c1_fck", |
| 1474 | .prcm = { |
| 1475 | .omap2 = { |
| 1476 | .module_offs = CORE_MOD, |
| 1477 | .prcm_reg_id = 1, |
| 1478 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1479 | .idlest_reg_id = 1, |
| 1480 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 1481 | }, |
| 1482 | }, |
| 1483 | .slaves = omap2420_i2c1_slaves, |
| 1484 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 1485 | .class = &i2c_class, |
| 1486 | .dev_attr = &i2c_dev_attr, |
| 1487 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1488 | .flags = HWMOD_16BIT_REG, |
| 1489 | }; |
| 1490 | |
| 1491 | /* I2C2 */ |
| 1492 | |
| 1493 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 1494 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 1495 | }; |
| 1496 | |
| 1497 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 1498 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 1499 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 1500 | }; |
| 1501 | |
| 1502 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 1503 | &omap2420_l4_core__i2c2, |
| 1504 | }; |
| 1505 | |
| 1506 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 1507 | .name = "i2c2", |
| 1508 | .mpu_irqs = i2c2_mpu_irqs, |
| 1509 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 1510 | .sdma_reqs = i2c2_sdma_reqs, |
| 1511 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 1512 | .main_clk = "i2c2_fck", |
| 1513 | .prcm = { |
| 1514 | .omap2 = { |
| 1515 | .module_offs = CORE_MOD, |
| 1516 | .prcm_reg_id = 1, |
| 1517 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1518 | .idlest_reg_id = 1, |
| 1519 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 1520 | }, |
| 1521 | }, |
| 1522 | .slaves = omap2420_i2c2_slaves, |
| 1523 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 1524 | .class = &i2c_class, |
| 1525 | .dev_attr = &i2c_dev_attr, |
| 1526 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1527 | .flags = HWMOD_16BIT_REG, |
| 1528 | }; |
| 1529 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1530 | /* l4_wkup -> gpio1 */ |
| 1531 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 1532 | { |
| 1533 | .pa_start = 0x48018000, |
| 1534 | .pa_end = 0x480181ff, |
| 1535 | .flags = ADDR_TYPE_RT |
| 1536 | }, |
| 1537 | }; |
| 1538 | |
| 1539 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 1540 | .master = &omap2420_l4_wkup_hwmod, |
| 1541 | .slave = &omap2420_gpio1_hwmod, |
| 1542 | .clk = "gpios_ick", |
| 1543 | .addr = omap2420_gpio1_addr_space, |
| 1544 | .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), |
| 1545 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1546 | }; |
| 1547 | |
| 1548 | /* l4_wkup -> gpio2 */ |
| 1549 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 1550 | { |
| 1551 | .pa_start = 0x4801a000, |
| 1552 | .pa_end = 0x4801a1ff, |
| 1553 | .flags = ADDR_TYPE_RT |
| 1554 | }, |
| 1555 | }; |
| 1556 | |
| 1557 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 1558 | .master = &omap2420_l4_wkup_hwmod, |
| 1559 | .slave = &omap2420_gpio2_hwmod, |
| 1560 | .clk = "gpios_ick", |
| 1561 | .addr = omap2420_gpio2_addr_space, |
| 1562 | .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), |
| 1563 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1564 | }; |
| 1565 | |
| 1566 | /* l4_wkup -> gpio3 */ |
| 1567 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 1568 | { |
| 1569 | .pa_start = 0x4801c000, |
| 1570 | .pa_end = 0x4801c1ff, |
| 1571 | .flags = ADDR_TYPE_RT |
| 1572 | }, |
| 1573 | }; |
| 1574 | |
| 1575 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 1576 | .master = &omap2420_l4_wkup_hwmod, |
| 1577 | .slave = &omap2420_gpio3_hwmod, |
| 1578 | .clk = "gpios_ick", |
| 1579 | .addr = omap2420_gpio3_addr_space, |
| 1580 | .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), |
| 1581 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1582 | }; |
| 1583 | |
| 1584 | /* l4_wkup -> gpio4 */ |
| 1585 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 1586 | { |
| 1587 | .pa_start = 0x4801e000, |
| 1588 | .pa_end = 0x4801e1ff, |
| 1589 | .flags = ADDR_TYPE_RT |
| 1590 | }, |
| 1591 | }; |
| 1592 | |
| 1593 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 1594 | .master = &omap2420_l4_wkup_hwmod, |
| 1595 | .slave = &omap2420_gpio4_hwmod, |
| 1596 | .clk = "gpios_ick", |
| 1597 | .addr = omap2420_gpio4_addr_space, |
| 1598 | .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), |
| 1599 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1600 | }; |
| 1601 | |
| 1602 | /* gpio dev_attr */ |
| 1603 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 1604 | .bank_width = 32, |
| 1605 | .dbck_flag = false, |
| 1606 | }; |
| 1607 | |
| 1608 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { |
| 1609 | .rev_offs = 0x0000, |
| 1610 | .sysc_offs = 0x0010, |
| 1611 | .syss_offs = 0x0014, |
| 1612 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 1613 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1614 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1615 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1616 | }; |
| 1617 | |
| 1618 | /* |
| 1619 | * 'gpio' class |
| 1620 | * general purpose io module |
| 1621 | */ |
| 1622 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { |
| 1623 | .name = "gpio", |
| 1624 | .sysc = &omap242x_gpio_sysc, |
| 1625 | .rev = 0, |
| 1626 | }; |
| 1627 | |
| 1628 | /* gpio1 */ |
| 1629 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { |
| 1630 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ |
| 1631 | }; |
| 1632 | |
| 1633 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
| 1634 | &omap2420_l4_wkup__gpio1, |
| 1635 | }; |
| 1636 | |
| 1637 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 1638 | .name = "gpio1", |
| 1639 | .mpu_irqs = omap242x_gpio1_irqs, |
| 1640 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), |
| 1641 | .main_clk = "gpios_fck", |
| 1642 | .prcm = { |
| 1643 | .omap2 = { |
| 1644 | .prcm_reg_id = 1, |
| 1645 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1646 | .module_offs = WKUP_MOD, |
| 1647 | .idlest_reg_id = 1, |
| 1648 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1649 | }, |
| 1650 | }, |
| 1651 | .slaves = omap2420_gpio1_slaves, |
| 1652 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), |
| 1653 | .class = &omap242x_gpio_hwmod_class, |
| 1654 | .dev_attr = &gpio_dev_attr, |
| 1655 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1656 | }; |
| 1657 | |
| 1658 | /* gpio2 */ |
| 1659 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { |
| 1660 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ |
| 1661 | }; |
| 1662 | |
| 1663 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
| 1664 | &omap2420_l4_wkup__gpio2, |
| 1665 | }; |
| 1666 | |
| 1667 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 1668 | .name = "gpio2", |
| 1669 | .mpu_irqs = omap242x_gpio2_irqs, |
| 1670 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), |
| 1671 | .main_clk = "gpios_fck", |
| 1672 | .prcm = { |
| 1673 | .omap2 = { |
| 1674 | .prcm_reg_id = 1, |
| 1675 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1676 | .module_offs = WKUP_MOD, |
| 1677 | .idlest_reg_id = 1, |
| 1678 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1679 | }, |
| 1680 | }, |
| 1681 | .slaves = omap2420_gpio2_slaves, |
| 1682 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), |
| 1683 | .class = &omap242x_gpio_hwmod_class, |
| 1684 | .dev_attr = &gpio_dev_attr, |
| 1685 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1686 | }; |
| 1687 | |
| 1688 | /* gpio3 */ |
| 1689 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { |
| 1690 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ |
| 1691 | }; |
| 1692 | |
| 1693 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
| 1694 | &omap2420_l4_wkup__gpio3, |
| 1695 | }; |
| 1696 | |
| 1697 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 1698 | .name = "gpio3", |
| 1699 | .mpu_irqs = omap242x_gpio3_irqs, |
| 1700 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), |
| 1701 | .main_clk = "gpios_fck", |
| 1702 | .prcm = { |
| 1703 | .omap2 = { |
| 1704 | .prcm_reg_id = 1, |
| 1705 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1706 | .module_offs = WKUP_MOD, |
| 1707 | .idlest_reg_id = 1, |
| 1708 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1709 | }, |
| 1710 | }, |
| 1711 | .slaves = omap2420_gpio3_slaves, |
| 1712 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), |
| 1713 | .class = &omap242x_gpio_hwmod_class, |
| 1714 | .dev_attr = &gpio_dev_attr, |
| 1715 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1716 | }; |
| 1717 | |
| 1718 | /* gpio4 */ |
| 1719 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { |
| 1720 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ |
| 1721 | }; |
| 1722 | |
| 1723 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
| 1724 | &omap2420_l4_wkup__gpio4, |
| 1725 | }; |
| 1726 | |
| 1727 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 1728 | .name = "gpio4", |
| 1729 | .mpu_irqs = omap242x_gpio4_irqs, |
| 1730 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), |
| 1731 | .main_clk = "gpios_fck", |
| 1732 | .prcm = { |
| 1733 | .omap2 = { |
| 1734 | .prcm_reg_id = 1, |
| 1735 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1736 | .module_offs = WKUP_MOD, |
| 1737 | .idlest_reg_id = 1, |
| 1738 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1739 | }, |
| 1740 | }, |
| 1741 | .slaves = omap2420_gpio4_slaves, |
| 1742 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), |
| 1743 | .class = &omap242x_gpio_hwmod_class, |
| 1744 | .dev_attr = &gpio_dev_attr, |
| 1745 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1746 | }; |
| 1747 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1748 | /* system dma */ |
| 1749 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { |
| 1750 | .rev_offs = 0x0000, |
| 1751 | .sysc_offs = 0x002c, |
| 1752 | .syss_offs = 0x0028, |
| 1753 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 1754 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
| 1755 | SYSC_HAS_AUTOIDLE), |
| 1756 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1757 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1758 | }; |
| 1759 | |
| 1760 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { |
| 1761 | .name = "dma", |
| 1762 | .sysc = &omap2420_dma_sysc, |
| 1763 | }; |
| 1764 | |
| 1765 | /* dma attributes */ |
| 1766 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 1767 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 1768 | IS_CSSA_32 | IS_CDSA_32, |
| 1769 | .lch_count = 32, |
| 1770 | }; |
| 1771 | |
| 1772 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { |
| 1773 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ |
| 1774 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ |
| 1775 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ |
| 1776 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ |
| 1777 | }; |
| 1778 | |
| 1779 | static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { |
| 1780 | { |
| 1781 | .pa_start = 0x48056000, |
| 1782 | .pa_end = 0x4a0560ff, |
| 1783 | .flags = ADDR_TYPE_RT |
| 1784 | }, |
| 1785 | }; |
| 1786 | |
| 1787 | /* dma_system -> L3 */ |
| 1788 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 1789 | .master = &omap2420_dma_system_hwmod, |
| 1790 | .slave = &omap2420_l3_main_hwmod, |
| 1791 | .clk = "core_l3_ck", |
| 1792 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1793 | }; |
| 1794 | |
| 1795 | /* dma_system master ports */ |
| 1796 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { |
| 1797 | &omap2420_dma_system__l3, |
| 1798 | }; |
| 1799 | |
| 1800 | /* l4_core -> dma_system */ |
| 1801 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
| 1802 | .master = &omap2420_l4_core_hwmod, |
| 1803 | .slave = &omap2420_dma_system_hwmod, |
| 1804 | .clk = "sdma_ick", |
| 1805 | .addr = omap2420_dma_system_addrs, |
| 1806 | .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), |
| 1807 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1808 | }; |
| 1809 | |
| 1810 | /* dma_system slave ports */ |
| 1811 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { |
| 1812 | &omap2420_l4_core__dma_system, |
| 1813 | }; |
| 1814 | |
| 1815 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 1816 | .name = "dma", |
| 1817 | .class = &omap2420_dma_hwmod_class, |
| 1818 | .mpu_irqs = omap2420_dma_system_irqs, |
| 1819 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), |
| 1820 | .main_clk = "core_l3_ck", |
| 1821 | .slaves = omap2420_dma_system_slaves, |
| 1822 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), |
| 1823 | .masters = omap2420_dma_system_masters, |
| 1824 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), |
| 1825 | .dev_attr = &dma_dev_attr, |
| 1826 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1827 | .flags = HWMOD_NO_IDLEST, |
| 1828 | }; |
| 1829 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1830 | /* |
| 1831 | * 'mcspi' class |
| 1832 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 1833 | * bus |
| 1834 | */ |
| 1835 | |
| 1836 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { |
| 1837 | .rev_offs = 0x0000, |
| 1838 | .sysc_offs = 0x0010, |
| 1839 | .syss_offs = 0x0014, |
| 1840 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1841 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1842 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 1843 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1844 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1845 | }; |
| 1846 | |
| 1847 | static struct omap_hwmod_class omap2420_mcspi_class = { |
| 1848 | .name = "mcspi", |
| 1849 | .sysc = &omap2420_mcspi_sysc, |
| 1850 | .rev = OMAP2_MCSPI_REV, |
| 1851 | }; |
| 1852 | |
| 1853 | /* mcspi1 */ |
| 1854 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { |
| 1855 | { .irq = 65 }, |
| 1856 | }; |
| 1857 | |
| 1858 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { |
| 1859 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 1860 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 1861 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 1862 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 1863 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 1864 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 1865 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 1866 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 1867 | }; |
| 1868 | |
| 1869 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { |
| 1870 | &omap2420_l4_core__mcspi1, |
| 1871 | }; |
| 1872 | |
| 1873 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 1874 | .num_chipselect = 4, |
| 1875 | }; |
| 1876 | |
| 1877 | static struct omap_hwmod omap2420_mcspi1_hwmod = { |
| 1878 | .name = "mcspi1_hwmod", |
| 1879 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, |
| 1880 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), |
| 1881 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, |
| 1882 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), |
| 1883 | .main_clk = "mcspi1_fck", |
| 1884 | .prcm = { |
| 1885 | .omap2 = { |
| 1886 | .module_offs = CORE_MOD, |
| 1887 | .prcm_reg_id = 1, |
| 1888 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1889 | .idlest_reg_id = 1, |
| 1890 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 1891 | }, |
| 1892 | }, |
| 1893 | .slaves = omap2420_mcspi1_slaves, |
| 1894 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), |
| 1895 | .class = &omap2420_mcspi_class, |
| 1896 | .dev_attr = &omap_mcspi1_dev_attr, |
| 1897 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1898 | }; |
| 1899 | |
| 1900 | /* mcspi2 */ |
| 1901 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { |
| 1902 | { .irq = 66 }, |
| 1903 | }; |
| 1904 | |
| 1905 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { |
| 1906 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 1907 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 1908 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 1909 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 1910 | }; |
| 1911 | |
| 1912 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { |
| 1913 | &omap2420_l4_core__mcspi2, |
| 1914 | }; |
| 1915 | |
| 1916 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 1917 | .num_chipselect = 2, |
| 1918 | }; |
| 1919 | |
| 1920 | static struct omap_hwmod omap2420_mcspi2_hwmod = { |
| 1921 | .name = "mcspi2_hwmod", |
| 1922 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, |
| 1923 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), |
| 1924 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, |
| 1925 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), |
| 1926 | .main_clk = "mcspi2_fck", |
| 1927 | .prcm = { |
| 1928 | .omap2 = { |
| 1929 | .module_offs = CORE_MOD, |
| 1930 | .prcm_reg_id = 1, |
| 1931 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1932 | .idlest_reg_id = 1, |
| 1933 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 1934 | }, |
| 1935 | }, |
| 1936 | .slaves = omap2420_mcspi2_slaves, |
| 1937 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), |
| 1938 | .class = &omap2420_mcspi_class, |
| 1939 | .dev_attr = &omap_mcspi2_dev_attr, |
| 1940 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1941 | }; |
| 1942 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1943 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1944 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1945 | &omap2420_l4_core_hwmod, |
| 1946 | &omap2420_l4_wkup_hwmod, |
| 1947 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 1948 | &omap2420_iva_hwmod, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 1949 | |
| 1950 | &omap2420_timer1_hwmod, |
| 1951 | &omap2420_timer2_hwmod, |
| 1952 | &omap2420_timer3_hwmod, |
| 1953 | &omap2420_timer4_hwmod, |
| 1954 | &omap2420_timer5_hwmod, |
| 1955 | &omap2420_timer6_hwmod, |
| 1956 | &omap2420_timer7_hwmod, |
| 1957 | &omap2420_timer8_hwmod, |
| 1958 | &omap2420_timer9_hwmod, |
| 1959 | &omap2420_timer10_hwmod, |
| 1960 | &omap2420_timer11_hwmod, |
| 1961 | &omap2420_timer12_hwmod, |
| 1962 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 1963 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1964 | &omap2420_uart1_hwmod, |
| 1965 | &omap2420_uart2_hwmod, |
| 1966 | &omap2420_uart3_hwmod, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1967 | /* dss class */ |
| 1968 | &omap2420_dss_core_hwmod, |
| 1969 | &omap2420_dss_dispc_hwmod, |
| 1970 | &omap2420_dss_rfbi_hwmod, |
| 1971 | &omap2420_dss_venc_hwmod, |
| 1972 | /* i2c class */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1973 | &omap2420_i2c1_hwmod, |
| 1974 | &omap2420_i2c2_hwmod, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1975 | |
| 1976 | /* gpio class */ |
| 1977 | &omap2420_gpio1_hwmod, |
| 1978 | &omap2420_gpio2_hwmod, |
| 1979 | &omap2420_gpio3_hwmod, |
| 1980 | &omap2420_gpio4_hwmod, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1981 | |
| 1982 | /* dma_system class*/ |
| 1983 | &omap2420_dma_system_hwmod, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1984 | |
| 1985 | /* mcspi class */ |
| 1986 | &omap2420_mcspi1_hwmod, |
| 1987 | &omap2420_mcspi2_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1988 | NULL, |
| 1989 | }; |
| 1990 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1991 | int __init omap2420_hwmod_init(void) |
| 1992 | { |
Paul Walmsley | 550c809 | 2011-02-28 11:58:14 -0700 | [diff] [blame^] | 1993 | return omap_hwmod_register(omap2420_hwmods); |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1994 | } |