blob: 15f1b0f0d0702c7ca6a9e4a5643761ce957f65e9 [file] [log] [blame]
Vasanthakumar Thiagarajanae3bb6d2010-04-15 17:38:27 -04001/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include "hw.h"
17
18static void ar9003_hw_rx_enable(struct ath_hw *hw)
19{
20 REG_WRITE(hw, AR_CR, 0);
21}
22
Vasanthakumar Thiagarajan87d5efb2010-04-15 17:38:43 -040023static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
24{
25 ((struct ar9003_txc *) ds)->link = ds_link;
26}
27
28static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
29{
30 *ds_link = &((struct ar9003_txc *) ds)->link;
31}
32
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -040033static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
34{
35 return true;
36}
37
Vasanthakumar Thiagarajanae3bb6d2010-04-15 17:38:27 -040038void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
39{
40 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
41
42 ops->rx_enable = ar9003_hw_rx_enable;
Vasanthakumar Thiagarajan87d5efb2010-04-15 17:38:43 -040043 ops->set_desc_link = ar9003_hw_set_desc_link;
44 ops->get_desc_link = ar9003_hw_get_desc_link;
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -040045 ops->get_isr = ar9003_hw_get_isr;
Vasanthakumar Thiagarajanae3bb6d2010-04-15 17:38:27 -040046}
Vasanthakumar Thiagarajanad7b8062010-04-15 17:38:28 -040047
48void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
49{
50 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
51}
52EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
53
54void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
55 enum ath9k_rx_qtype qtype)
56{
57 if (qtype == ATH9K_RX_QUEUE_HP)
58 REG_WRITE(ah, AR_HP_RXDP, rxdp);
59 else
60 REG_WRITE(ah, AR_LP_RXDP, rxdp);
61}
62EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
63
64int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
65 void *buf_addr)
66{
67 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
68 unsigned int phyerr;
69
70 /* TODO: byte swap on big endian for ar9300_10 */
71
72 if ((rxsp->status11 & AR_RxDone) == 0)
73 return -EINPROGRESS;
74
75 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
76 return -EINVAL;
77
78 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
79 return -EINPROGRESS;
80
Felix Fietkaub5c804752010-04-15 17:38:48 -040081 if (!rxs)
82 return 0;
83
Vasanthakumar Thiagarajanad7b8062010-04-15 17:38:28 -040084 rxs->rs_status = 0;
85 rxs->rs_flags = 0;
86
87 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
88 rxs->rs_tstamp = rxsp->status3;
89
90 /* XXX: Keycache */
91 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
92 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
93 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
94 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
95 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
96 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
97 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
98
99 if (rxsp->status11 & AR_RxKeyIdxValid)
100 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
101 else
102 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
103
104 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
105 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
106
107 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
108 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
109 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
110 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
111 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
112
113 rxs->evm0 = rxsp->status6;
114 rxs->evm1 = rxsp->status7;
115 rxs->evm2 = rxsp->status8;
116 rxs->evm3 = rxsp->status9;
117 rxs->evm4 = (rxsp->status10 & 0xffff);
118
119 if (rxsp->status11 & AR_PreDelimCRCErr)
120 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
121
122 if (rxsp->status11 & AR_PostDelimCRCErr)
123 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
124
125 if (rxsp->status11 & AR_DecryptBusyErr)
126 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
127
128 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
129 if (rxsp->status11 & AR_CRCErr) {
130 rxs->rs_status |= ATH9K_RXERR_CRC;
131 } else if (rxsp->status11 & AR_PHYErr) {
132 rxs->rs_status |= ATH9K_RXERR_PHY;
133 phyerr = MS(rxsp->status11, AR_PHYErrCode);
134 rxs->rs_phyerr = phyerr;
135 } else if (rxsp->status11 & AR_DecryptCRCErr) {
136 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
137 } else if (rxsp->status11 & AR_MichaelErr) {
138 rxs->rs_status |= ATH9K_RXERR_MIC;
139 }
140 }
141
142 return 0;
143}
144EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);