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gerrit-public.fairphone.software / kernel / msm / 566d84d172161cb6c0c4dd834c34abbac6bf7b38 / . / drivers / gpu / drm / radeon / radeon_drv.h
blob: ee484b61bc5cf39833494a357c81853d70ce9b2a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
Ben Hutchings70967ab2009-08-29 14:53:51 +0100[diff] [blame]34#include <linux/firmware.h>
35#include <linux/platform_device.h>
36
Dave Airliec2142712009-09-22 08:50:10 +1000[diff] [blame]37#include "radeon_family.h"
38
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]39/* General customization:
40 */
41
42#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
43
44#define DRIVER_NAME "radeon"
45#define DRIVER_DESC "ATI Radeon"
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]46#define DRIVER_DATE "20080528"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]47
48/* Interface history:
49 *
50 * 1.1 - ??
51 * 1.2 - Add vertex2 ioctl (keith)
52 * - Add stencil capability to clear ioctl (gareth, keith)
53 * - Increase MAX_TEXTURE_LEVELS (brian)
54 * 1.3 - Add cmdbuf ioctl (keith)
55 * - Add support for new radeon packets (keith)
56 * - Add getparam ioctl (keith)
57 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
58 * 1.4 - Add scratch registers to get_param ioctl.
59 * 1.5 - Add r200 packets to cmdbuf ioctl
60 * - Add r200 function to init ioctl
61 * - Add 'scalar2' instruction to cmdbuf
62 * 1.6 - Add static GART memory manager
63 * Add irq handler (won't be turned on unless X server knows to)
64 * Add irq ioctls and irq_active getparam.
65 * Add wait command for cmdbuf ioctl
66 * Add GART offset query for getparam
67 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
68 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
69 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
70 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
71 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
72 * Add 'GET' queries for starting additional clients on different VT's.
73 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
74 * Add texture rectangle support for r100.
75 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]76 * clients use to tell the DRM where they think the framebuffer is
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]77 * located in the card's address space
78 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
79 * and GL_EXT_blend_[func|equation]_separate on r200
80 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]81 * (No 3D support yet - just microcode loading).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]82 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
83 * - Add hyperz support, add hyperz flags to clear ioctl.
84 * 1.14- Add support for color tiling
85 * - Add R100/R200 surface allocation/free support
86 * 1.15- Add support for texture micro tiling
87 * - Add support for r100 cube maps
88 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
89 * texture filtering on r200
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]90 * 1.17- Add initial support for R300 (3D).
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]91 * 1.18- Add support for GL_ATI_fragment_shader, new packets
92 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
93 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
94 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]95 * 1.19- Add support for gart table in FB memory and PCIE r300
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]96 * 1.20- Add support for r300 texrect
97 * 1.21- Add support for card type getparam
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100[diff] [blame]98 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
Dave Airlied5ea7022006-03-19 19:37:55 +1100[diff] [blame]99 * 1.23- Add new radeon memory map work from benh
Dave Airlieee4621f2006-03-19 19:45:26 +1100[diff] [blame]100 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
Dave Airlied6fece02006-06-24 17:04:07 +1000[diff] [blame]101 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
102 * new packet type)
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]103 * 1.26- Add support for variable size PCI(E) gart aperture
104 * 1.27- Add support for IGP GART
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]105 * 1.28- Add support for VBL on CRTC2
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]106 * 1.29- R500 3D cmd buffer support
Maciej Cencorae8a13442009-04-17 15:55:09 +0200[diff] [blame]107 * 1.30- Add support for occlusion queries
Alex Deucherf779b3e2009-08-19 19:11:39 -0400[diff] [blame]108 * 1.31- Add support for num Z pipes from GET_PARAM
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]109 */
110#define DRIVER_MAJOR 1
Alex Deucherf779b3e2009-08-19 19:11:39 -0400[diff] [blame]111#define DRIVER_MINOR 31
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]112#define DRIVER_PATCHLEVEL 0
113
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]114enum radeon_cp_microcode_version {
115 UCODE_R100,
116 UCODE_R200,
117 UCODE_R300,
118};
119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]120typedef struct drm_radeon_freelist {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]121 unsigned int age;
Dave Airlie056219e2007-07-11 16:17:42 +1000[diff] [blame]122 struct drm_buf *buf;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]123 struct drm_radeon_freelist *next;
124 struct drm_radeon_freelist *prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]125} drm_radeon_freelist_t;
126
127typedef struct drm_radeon_ring_buffer {
128 u32 *start;
129 u32 *end;
130 int size;
131 int size_l2qw;
132
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]133 int rptr_update; /* Double Words */
134 int rptr_update_l2qw; /* log2 Quad Words */
135
136 int fetch_size; /* Double Words */
137 int fetch_size_l2ow; /* log2 Oct Words */
138
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]139 u32 tail;
140 u32 tail_mask;
141 int space;
142
143 int high_mark;
144} drm_radeon_ring_buffer_t;
145
146typedef struct drm_radeon_depth_clear_t {
147 u32 rb3d_cntl;
148 u32 rb3d_zstencilcntl;
149 u32 se_cntl;
150} drm_radeon_depth_clear_t;
151
152struct drm_radeon_driver_file_fields {
153 int64_t radeon_fb_delta;
154};
155
156struct mem_block {
157 struct mem_block *next;
158 struct mem_block *prev;
159 int start;
160 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]161 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]162};
163
164struct radeon_surface {
165 int refcount;
166 u32 lower;
167 u32 upper;
168 u32 flags;
169};
170
171struct radeon_virt_surface {
172 int surface_index;
173 u32 lower;
174 u32 upper;
175 u32 flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]176 struct drm_file *file_priv;
David Miller6abf6bb2009-02-14 01:51:07 -0800[diff] [blame]177#define PCIGART_FILE_PRIV ((void *) -1L)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]178};
179
David Millerb2665032009-02-12 02:15:39 -0800[diff] [blame]180#define RADEON_FLUSH_EMITED (1 << 0)
181#define RADEON_PURGE_EMITED (1 << 1)
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]182
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]183struct drm_radeon_master_private {
184 drm_local_map_t *sarea;
185 drm_radeon_sarea_t *sarea_priv;
186};
187
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]188typedef struct drm_radeon_private {
189 drm_radeon_ring_buffer_t ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]190
191 u32 fb_location;
Dave Airlied5ea7022006-03-19 19:37:55 +1100[diff] [blame]192 u32 fb_size;
193 int new_memmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]194
195 int gart_size;
196 u32 gart_vm_start;
197 unsigned long gart_buffers_offset;
198
199 int cp_mode;
200 int cp_running;
201
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]202 drm_radeon_freelist_t *head;
203 drm_radeon_freelist_t *tail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]204 int last_buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]205 int writeback_works;
206
207 int usec_timeout;
208
209 int microcode_version;
210
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]211 struct {
212 u32 boxes;
213 int freelist_timeouts;
214 int freelist_loops;
215 int requested_bufs;
216 int last_frame_reads;
217 int last_clear_reads;
218 int clears;
219 int texture_uploads;
220 } stats;
221
222 int do_boxes;
223 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]224
225 u32 color_fmt;
226 unsigned int front_offset;
227 unsigned int front_pitch;
228 unsigned int back_offset;
229 unsigned int back_pitch;
230
231 u32 depth_fmt;
232 unsigned int depth_offset;
233 unsigned int depth_pitch;
234
235 u32 front_pitch_offset;
236 u32 back_pitch_offset;
237 u32 depth_pitch_offset;
238
239 drm_radeon_depth_clear_t depth_clear;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]240
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]241 unsigned long ring_offset;
242 unsigned long ring_rptr_offset;
243 unsigned long buffers_offset;
244 unsigned long gart_textures_offset;
245
246 drm_local_map_t *sarea;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]247 drm_local_map_t *cp_ring;
248 drm_local_map_t *ring_rptr;
249 drm_local_map_t *gart_textures;
250
251 struct mem_block *gart_heap;
252 struct mem_block *fb_heap;
253
254 /* SW interrupt */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]255 wait_queue_head_t swi_queue;
256 atomic_t swi_emitted;
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]257 int vblank_crtc;
258 uint32_t irq_enable_reg;
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]259 uint32_t r500_disp_irq_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]260
261 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]262 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]263
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]264 unsigned long pcigart_offset;
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]265 unsigned int pcigart_offset_set;
Dave Airlie55910512007-07-11 16:53:40 +1000[diff] [blame]266 struct drm_ati_pcigart_info gart_info;
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]267
Dave Airlieee4621f2006-03-19 19:45:26 +1100[diff] [blame]268 u32 scratch_ages[5];
269
Dave Airlie566d84d2010-02-24 17:17:13 +1000[diff] [blame^]270 int have_z_offset;
271
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]272 /* starting from here on, data is preserved accross an open */
273 uint32_t flags; /* see radeon_chip_flags */
Benjamin Herrenschmidtd883f7f2009-02-02 16:55:45 +1100[diff] [blame]274 resource_size_t fb_aper_offset;
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]275
276 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400[diff] [blame]277 int num_z_pipes;
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]278 int track_flush;
Dave Airlie78538bf2008-11-11 17:56:16 +1000[diff] [blame]279 drm_local_map_t *mmio;
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]280
281 /* r6xx/r7xx pipe/shader config */
282 int r600_max_pipes;
283 int r600_max_tile_pipes;
284 int r600_max_simds;
285 int r600_max_backends;
286 int r600_max_gprs;
287 int r600_max_threads;
288 int r600_max_stack_entries;
289 int r600_max_hw_contexts;
290 int r600_max_gs_threads;
291 int r600_sx_max_export_size;
292 int r600_sx_max_export_pos_size;
293 int r600_sx_max_export_smx_size;
294 int r600_sq_num_cf_insts;
295 int r700_sx_num_of_sets;
296 int r700_sc_prim_fifo_size;
297 int r700_sc_hiz_tile_fifo_size;
298 int r700_sc_earlyz_tile_fifo_fize;
Jerome Glisse961fb592010-02-10 22:30:05 +0000[diff] [blame]299 int r600_group_size;
300 int r600_npipes;
301 int r600_nbanks;
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]302
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]303 struct mutex cs_mutex;
304 u32 cs_id_scnt;
305 u32 cs_id_wcnt;
306 /* r6xx/r7xx drm blit vertex buffer */
307 struct drm_buf *blit_vb;
308
Ben Hutchings70967ab2009-08-29 14:53:51 +0100[diff] [blame]309 /* firmware */
310 const struct firmware *me_fw, *pfp_fw;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]311} drm_radeon_private_t;
312
313typedef struct drm_radeon_buf_priv {
314 u32 age;
315} drm_radeon_buf_priv_t;
316
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200[diff] [blame]317struct drm_buffer;
318
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]319typedef struct drm_radeon_kcmd_buffer {
320 int bufsz;
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200[diff] [blame]321 struct drm_buffer *buffer;
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]322 int nbox;
Dave Airliec60ce622007-07-11 15:27:12 +1000[diff] [blame]323 struct drm_clip_rect __user *boxes;
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]324} drm_radeon_kcmd_buffer_t;
325
Dave Airlie689b9d72005-09-30 17:09:07 +1000[diff] [blame]326extern int radeon_no_wb;
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]327extern struct drm_ioctl_desc radeon_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]328extern int radeon_max_ioctl;
329
David Millerb07fa022009-02-12 02:15:37 -0800[diff] [blame]330extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
331extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
332
333#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
334#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
335
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100[diff] [blame]336/* Check whether the given hardware address is inside the framebuffer or the
337 * GART area.
338 */
339static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
340 u64 off)
341{
342 u32 fb_start = dev_priv->fb_location;
343 u32 fb_end = fb_start + dev_priv->fb_size - 1;
344 u32 gart_start = dev_priv->gart_vm_start;
345 u32 gart_end = gart_start + dev_priv->gart_size - 1;
346
347 return ((off >= fb_start && off <= fb_end) ||
348 (off >= gart_start && off <= gart_end));
349}
350
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]351/* radeon_state.c */
352extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
353
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]354 /* radeon_cp.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]355extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
356extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
357extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
358extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
360extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
361extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
362extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
363extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]364extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]365extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
366extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]367extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]368
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]369extern void radeon_freelist_reset(struct drm_device * dev);
Dave Airlie056219e2007-07-11 16:17:42 +1000[diff] [blame]370extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]371
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]372extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]373
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]374extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]375
376extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
Dave Airlie836cf042005-07-10 19:27:04 +1000[diff] [blame]377extern int radeon_presetup(struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]378extern int radeon_driver_postcleanup(struct drm_device *dev);
379
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]380extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
381extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
382extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]383extern void radeon_mem_takedown(struct mem_block **heap);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]384extern void radeon_mem_release(struct drm_file *file_priv,
385 struct mem_block *heap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]386
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]387extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
388extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
389extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
390
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]391 /* radeon_irq.c */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]392extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]393extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
394extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]395
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]396extern void radeon_do_release(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]397extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
398extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
399extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]400extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]401extern void radeon_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]402extern int radeon_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]403extern void radeon_driver_irq_uninstall(struct drm_device * dev);
Dennis Kasprzyk7ecabc52008-06-19 12:36:55 +1000[diff] [blame]404extern void radeon_enable_interrupt(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]405extern int radeon_vblank_crtc_get(struct drm_device *dev);
406extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]407
Dave Airlie22eae942005-11-10 22:16:34 +1100[diff] [blame]408extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
409extern int radeon_driver_unload(struct drm_device *dev);
410extern int radeon_driver_firstopen(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]411extern void radeon_driver_preclose(struct drm_device *dev,
412 struct drm_file *file_priv);
413extern void radeon_driver_postclose(struct drm_device *dev,
414 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]415extern void radeon_driver_lastclose(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]416extern int radeon_driver_open(struct drm_device *dev,
417 struct drm_file *file_priv);
Dave Airlie9a186642005-06-23 21:29:18 +1000[diff] [blame]418extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
419 unsigned long arg);
Dave Airlie70ba2a32009-09-15 09:03:43 +1000[diff] [blame]420extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
421 unsigned long arg);
Dave Airlie9a186642005-06-23 21:29:18 +1000[diff] [blame]422
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]423extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
424extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
425extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]426/* r300_cmdbuf.c */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]427extern void r300_init_reg_flags(struct drm_device *dev);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]428
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]429extern int r300_do_cp_cmdbuf(struct drm_device *dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]430 struct drm_file *file_priv,
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]431 drm_radeon_kcmd_buffer_t *cmdbuf);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]432
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]433/* r600_cp.c */
434extern int r600_do_engine_reset(struct drm_device *dev);
435extern int r600_do_cleanup_cp(struct drm_device *dev);
436extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
437 struct drm_file *file_priv);
438extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
439extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
440extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
441extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
442extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
443extern int r600_cp_dispatch_indirect(struct drm_device *dev,
444 struct drm_buf *buf, int start, int end);
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]445extern int r600_page_table_init(struct drm_device *dev);
446extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]447extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
448extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
449extern int r600_cp_dispatch_texture(struct drm_device *dev,
450 struct drm_file *file_priv,
451 drm_radeon_texture_t *tex,
452 drm_radeon_tex_image_t *image);
453/* r600_blit.c */
454extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
455extern void r600_done_blit_copy(struct drm_device *dev);
456extern void r600_blit_copy(struct drm_device *dev,
457 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
458 int size_bytes);
459extern void r600_blit_swap(struct drm_device *dev,
460 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
461 int sx, int sy, int dx, int dy,
462 int w, int h, int src_pitch, int dst_pitch, int cpp);
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]463
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]464/* Flags for stats.boxes
465 */
466#define RADEON_BOX_DMA_IDLE 0x1
467#define RADEON_BOX_RING_FULL 0x2
468#define RADEON_BOX_FLIP 0x4
469#define RADEON_BOX_WAIT_IDLE 0x8
470#define RADEON_BOX_TEXTURE_LOAD 0x10
471
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]472/* Register definitions, register access macros and drmAddMap constants
473 * for Radeon kernel driver.
474 */
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]475#define RADEON_MM_INDEX 0x0000
476#define RADEON_MM_DATA 0x0004
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]477
478#define RADEON_AGP_COMMAND 0x0f60
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]479#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
480# define RADEON_AGP_ENABLE (1<<8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]481#define RADEON_AUX_SCISSOR_CNTL 0x26f0
482# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
483# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
484# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
485# define RADEON_SCISSOR_0_ENABLE (1 << 28)
486# define RADEON_SCISSOR_1_ENABLE (1 << 29)
487# define RADEON_SCISSOR_2_ENABLE (1 << 30)
488
Alex Deucheredc6f382008-10-17 09:21:45 +1000[diff] [blame]489/*
490 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
491 * don't have an explicit bus mastering disable bit. It's handled
492 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
493 * handling, not bus mastering itself.
494 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]495#define RADEON_BUS_CNTL 0x0030
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]496/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]497# define RADEON_BUS_MASTER_DIS (1 << 6)
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]498/* rs600/rs690/rs740 */
499# define RS600_BUS_MASTER_DIS (1 << 14)
500# define RS600_MSI_REARM (1 << 20)
501/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
Alex Deucheredc6f382008-10-17 09:21:45 +1000[diff] [blame]502
503#define RADEON_BUS_CNTL1 0x0034
504# define RADEON_PMI_BM_DIS (1 << 2)
505# define RADEON_PMI_INT_DIS (1 << 3)
506
507#define RV370_BUS_CNTL 0x004c
508# define RV370_PMI_BM_DIS (1 << 5)
509# define RV370_PMI_INT_DIS (1 << 6)
510
511#define RADEON_MSI_REARM_EN 0x0160
512/* rv370/rv380, rv410, r423/r430/r480, r5xx */
513# define RV370_MSI_REARM_EN (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]514
515#define RADEON_CLOCK_CNTL_DATA 0x000c
516# define RADEON_PLL_WR_EN (1 << 7)
517#define RADEON_CLOCK_CNTL_INDEX 0x0008
518#define RADEON_CONFIG_APER_SIZE 0x0108
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]519#define RADEON_CONFIG_MEMSIZE 0x00f8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]520#define RADEON_CRTC_OFFSET 0x0224
521#define RADEON_CRTC_OFFSET_CNTL 0x0228
522# define RADEON_CRTC_TILE_EN (1 << 15)
523# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
524#define RADEON_CRTC2_OFFSET 0x0324
525#define RADEON_CRTC2_OFFSET_CNTL 0x0328
526
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]527#define RADEON_PCIE_INDEX 0x0030
528#define RADEON_PCIE_DATA 0x0034
529#define RADEON_PCIE_TX_GART_CNTL 0x10
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]530# define RADEON_PCIE_TX_GART_EN (1 << 0)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]531# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
532# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
533# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
534# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
535# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
536# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
537# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]538#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
539#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]540#define RADEON_PCIE_TX_GART_BASE 0x13
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]541#define RADEON_PCIE_TX_GART_START_LO 0x14
542#define RADEON_PCIE_TX_GART_START_HI 0x15
543#define RADEON_PCIE_TX_GART_END_LO 0x16
544#define RADEON_PCIE_TX_GART_END_HI 0x17
545
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]546#define RS480_NB_MC_INDEX 0x168
547# define RS480_NB_MC_IND_WR_EN (1 << 8)
548#define RS480_NB_MC_DATA 0x16c
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]549
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]550#define RS690_MC_INDEX 0x78
551# define RS690_MC_INDEX_MASK 0x1ff
552# define RS690_MC_INDEX_WR_EN (1 << 9)
553# define RS690_MC_INDEX_WR_ACK 0x7f
554#define RS690_MC_DATA 0x7c
555
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]556/* MC indirect registers */
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]557#define RS480_MC_MISC_CNTL 0x18
558# define RS480_DISABLE_GTW (1 << 1)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]559/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]560# define RS480_GART_INDEX_REG_EN (1 << 12)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]561# define RS690_BLOCK_GFX_D3_EN (1 << 14)
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]562#define RS480_K8_FB_LOCATION 0x1e
563#define RS480_GART_FEATURE_ID 0x2b
564# define RS480_HANG_EN (1 << 11)
565# define RS480_TLB_ENABLE (1 << 18)
566# define RS480_P2P_ENABLE (1 << 19)
567# define RS480_GTW_LAC_EN (1 << 25)
568# define RS480_2LEVEL_GART (0 << 30)
569# define RS480_1LEVEL_GART (1 << 30)
570# define RS480_PDC_EN (1 << 31)
571#define RS480_GART_BASE 0x2c
572#define RS480_GART_CACHE_CNTRL 0x2e
573# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
574#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
575# define RS480_GART_EN (1 << 0)
576# define RS480_VA_SIZE_32MB (0 << 1)
577# define RS480_VA_SIZE_64MB (1 << 1)
578# define RS480_VA_SIZE_128MB (2 << 1)
579# define RS480_VA_SIZE_256MB (3 << 1)
580# define RS480_VA_SIZE_512MB (4 << 1)
581# define RS480_VA_SIZE_1GB (5 << 1)
582# define RS480_VA_SIZE_2GB (6 << 1)
583#define RS480_AGP_MODE_CNTL 0x39
584# define RS480_POST_GART_Q_SIZE (1 << 18)
585# define RS480_NONGART_SNOOP (1 << 19)
586# define RS480_AGP_RD_BUF_SIZE (1 << 20)
587# define RS480_REQ_TYPE_SNOOP_SHIFT 22
588# define RS480_REQ_TYPE_SNOOP_MASK 0x3
589# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
590#define RS480_MC_MISC_UMA_CNTL 0x5f
591#define RS480_MC_MCLK_CNTL 0x7a
592#define RS480_MC_UMA_DUALCH_CNTL 0x86
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]593
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]594#define RS690_MC_FB_LOCATION 0x100
595#define RS690_MC_AGP_LOCATION 0x101
596#define RS690_MC_AGP_BASE 0x102
Dave Airlie3722bfc2008-05-28 11:28:27 +1000[diff] [blame]597#define RS690_MC_AGP_BASE_2 0x103
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]598
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]599#define RS600_MC_INDEX 0x70
600# define RS600_MC_ADDR_MASK 0xffff
601# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
602# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
603# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
604# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
605# define RS600_MC_IND_AIC_RBS (1 << 20)
606# define RS600_MC_IND_CITF_ARB0 (1 << 21)
607# define RS600_MC_IND_CITF_ARB1 (1 << 22)
608# define RS600_MC_IND_WR_EN (1 << 23)
609#define RS600_MC_DATA 0x74
610
611#define RS600_MC_STATUS 0x0
612# define RS600_MC_IDLE (1 << 1)
613#define RS600_MC_FB_LOCATION 0x4
614#define RS600_MC_AGP_LOCATION 0x5
615#define RS600_AGP_BASE 0x6
616#define RS600_AGP_BASE_2 0x7
617#define RS600_MC_CNTL1 0x9
618# define RS600_ENABLE_PAGE_TABLES (1 << 26)
619#define RS600_MC_PT0_CNTL 0x100
620# define RS600_ENABLE_PT (1 << 0)
621# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
622# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
623# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
624# define RS600_INVALIDATE_L2_CACHE (1 << 29)
625#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
626# define RS600_ENABLE_PAGE_TABLE (1 << 0)
627# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
628#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
629#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
630#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
631#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
632#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
633#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
634#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
635# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
636# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
637# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
638# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
639# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
640# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
641# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
642# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
643# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
644# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
645# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
646# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
647# define RS600_INVALIDATE_L1_TLB (1 << 20)
648
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]649#define R520_MC_IND_INDEX 0x70
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]650#define R520_MC_IND_WR_EN (1 << 24)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]651#define R520_MC_IND_DATA 0x74
652
653#define RV515_MC_FB_LOCATION 0x01
654#define RV515_MC_AGP_LOCATION 0x02
Dave Airlie70b13d52008-06-19 11:40:44 +1000[diff] [blame]655#define RV515_MC_AGP_BASE 0x03
656#define RV515_MC_AGP_BASE_2 0x04
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]657
658#define R520_MC_FB_LOCATION 0x04
659#define R520_MC_AGP_LOCATION 0x05
Dave Airlie70b13d52008-06-19 11:40:44 +1000[diff] [blame]660#define R520_MC_AGP_BASE 0x06
661#define R520_MC_AGP_BASE_2 0x07
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]662
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]663#define RADEON_MPP_TB_CONFIG 0x01c0
664#define RADEON_MEM_CNTL 0x0140
665#define RADEON_MEM_SDRAM_MODE_REG 0x0158
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]666#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
667#define RS480_AGP_BASE_2 0x0164
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]668#define RADEON_AGP_BASE 0x0170
669
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]670/* pipe config regs */
671#define R400_GB_PIPE_SELECT 0x402c
Alex Deucherf779b3e2009-08-19 19:11:39 -0400[diff] [blame]672#define RV530_GB_PIPE_SELECT2 0x4124
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]673#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]674#define R300_GB_TILE_CONFIG 0x4018
675# define R300_ENABLE_TILING (1 << 0)
676# define R300_PIPE_COUNT_RV350 (0 << 1)
677# define R300_PIPE_COUNT_R300 (3 << 1)
678# define R300_PIPE_COUNT_R420_3P (6 << 1)
679# define R300_PIPE_COUNT_R420 (7 << 1)
680# define R300_TILE_SIZE_8 (0 << 4)
681# define R300_TILE_SIZE_16 (1 << 4)
682# define R300_TILE_SIZE_32 (2 << 4)
683# define R300_SUBPIXEL_1_12 (0 << 16)
684# define R300_SUBPIXEL_1_16 (1 << 16)
685#define R300_DST_PIPE_CONFIG 0x170c
686# define R300_PIPE_AUTO_CONFIG (1 << 31)
687#define R300_RB2D_DSTCACHE_MODE 0x3428
688# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
689# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
690
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]691#define RADEON_RB3D_COLOROFFSET 0x1c40
692#define RADEON_RB3D_COLORPITCH 0x1c48
693
Michel Daenzer3e14a282006-09-22 04:26:35 +1000[diff] [blame]694#define RADEON_SRC_X_Y 0x1590
695
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]696#define RADEON_DP_GUI_MASTER_CNTL 0x146c
697# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
698# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
699# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
700# define RADEON_GMC_BRUSH_NONE (15 << 4)
701# define RADEON_GMC_DST_16BPP (4 << 8)
702# define RADEON_GMC_DST_24BPP (5 << 8)
703# define RADEON_GMC_DST_32BPP (6 << 8)
704# define RADEON_GMC_DST_DATATYPE_SHIFT 8
705# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
706# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
707# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
708# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
709# define RADEON_GMC_WR_MSK_DIS (1 << 30)
710# define RADEON_ROP3_S 0x00cc0000
711# define RADEON_ROP3_P 0x00f00000
712#define RADEON_DP_WRITE_MASK 0x16cc
Michel Daenzer3e14a282006-09-22 04:26:35 +1000[diff] [blame]713#define RADEON_SRC_PITCH_OFFSET 0x1428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]714#define RADEON_DST_PITCH_OFFSET 0x142c
715#define RADEON_DST_PITCH_OFFSET_C 0x1c80
716# define RADEON_DST_TILE_LINEAR (0 << 30)
717# define RADEON_DST_TILE_MACRO (1 << 30)
718# define RADEON_DST_TILE_MICRO (2 << 30)
719# define RADEON_DST_TILE_BOTH (3 << 30)
720
721#define RADEON_SCRATCH_REG0 0x15e0
722#define RADEON_SCRATCH_REG1 0x15e4
723#define RADEON_SCRATCH_REG2 0x15e8
724#define RADEON_SCRATCH_REG3 0x15ec
725#define RADEON_SCRATCH_REG4 0x15f0
726#define RADEON_SCRATCH_REG5 0x15f4
727#define RADEON_SCRATCH_UMSK 0x0770
728#define RADEON_SCRATCH_ADDR 0x0774
729
730#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
731
David Millerb07fa022009-02-12 02:15:37 -0800[diff] [blame]732extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
733
734#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]735
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]736#define R600_SCRATCH_REG0 0x8500
737#define R600_SCRATCH_REG1 0x8504
738#define R600_SCRATCH_REG2 0x8508
739#define R600_SCRATCH_REG3 0x850c
740#define R600_SCRATCH_REG4 0x8510
741#define R600_SCRATCH_REG5 0x8514
742#define R600_SCRATCH_REG6 0x8518
743#define R600_SCRATCH_REG7 0x851c
744#define R600_SCRATCH_UMSK 0x8540
745#define R600_SCRATCH_ADDR 0x8544
746
747#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
748
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]749#define RADEON_GEN_INT_CNTL 0x0040
750# define RADEON_CRTC_VBLANK_MASK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]751# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]752# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
753# define RADEON_SW_INT_ENABLE (1 << 25)
754
755#define RADEON_GEN_INT_STATUS 0x0044
756# define RADEON_CRTC_VBLANK_STAT (1 << 0)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]757# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]758# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]759# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]760# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
761# define RADEON_SW_INT_TEST (1 << 25)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]762# define RADEON_SW_INT_TEST_ACK (1 << 25)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]763# define RADEON_SW_INT_FIRE (1 << 26)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]764# define R500_DISPLAY_INT_STATUS (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]765
766#define RADEON_HOST_PATH_CNTL 0x0130
767# define RADEON_HDP_SOFT_RESET (1 << 26)
768# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
769# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
770
771#define RADEON_ISYNC_CNTL 0x1724
772# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
773# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
774# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
775# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
776# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
777# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
778
779#define RADEON_RBBM_GUICNTL 0x172c
780# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
781# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
782# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
783# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
784
785#define RADEON_MC_AGP_LOCATION 0x014c
786#define RADEON_MC_FB_LOCATION 0x0148
787#define RADEON_MCLK_CNTL 0x0012
788# define RADEON_FORCEON_MCLKA (1 << 16)
789# define RADEON_FORCEON_MCLKB (1 << 17)
790# define RADEON_FORCEON_YCLKA (1 << 18)
791# define RADEON_FORCEON_YCLKB (1 << 19)
792# define RADEON_FORCEON_MC (1 << 20)
793# define RADEON_FORCEON_AIC (1 << 21)
794
795#define RADEON_PP_BORDER_COLOR_0 0x1d40
796#define RADEON_PP_BORDER_COLOR_1 0x1d44
797#define RADEON_PP_BORDER_COLOR_2 0x1d48
798#define RADEON_PP_CNTL 0x1c38
799# define RADEON_SCISSOR_ENABLE (1 << 1)
800#define RADEON_PP_LUM_MATRIX 0x1d00
801#define RADEON_PP_MISC 0x1c14
802#define RADEON_PP_ROT_MATRIX_0 0x1d58
803#define RADEON_PP_TXFILTER_0 0x1c54
804#define RADEON_PP_TXOFFSET_0 0x1c5c
805#define RADEON_PP_TXFILTER_1 0x1c6c
806#define RADEON_PP_TXFILTER_2 0x1c84
807
Alex Deucher5e35eff2008-06-19 12:39:23 +1000[diff] [blame]808#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
809#define R300_DSTCACHE_CTLSTAT 0x1714
810# define R300_RB2D_DC_FLUSH (3 << 0)
811# define R300_RB2D_DC_FREE (3 << 2)
812# define R300_RB2D_DC_FLUSH_ALL 0xf
813# define R300_RB2D_DC_BUSY (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]814#define RADEON_RB3D_CNTL 0x1c3c
815# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
816# define RADEON_PLANE_MASK_ENABLE (1 << 1)
817# define RADEON_DITHER_ENABLE (1 << 2)
818# define RADEON_ROUND_ENABLE (1 << 3)
819# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
820# define RADEON_DITHER_INIT (1 << 5)
821# define RADEON_ROP_ENABLE (1 << 6)
822# define RADEON_STENCIL_ENABLE (1 << 7)
823# define RADEON_Z_ENABLE (1 << 8)
824# define RADEON_ZBLOCK16 (1 << 15)
825#define RADEON_RB3D_DEPTHOFFSET 0x1c24
826#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
827#define RADEON_RB3D_DEPTHPITCH 0x1c28
828#define RADEON_RB3D_PLANEMASK 0x1d84
829#define RADEON_RB3D_STENCILREFMASK 0x1d7c
830#define RADEON_RB3D_ZCACHE_MODE 0x3250
831#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
832# define RADEON_RB3D_ZC_FLUSH (1 << 0)
833# define RADEON_RB3D_ZC_FREE (1 << 2)
834# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
835# define RADEON_RB3D_ZC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]836#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
837# define R300_ZC_FLUSH (1 << 0)
838# define R300_ZC_FREE (1 << 1)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]839# define R300_ZC_BUSY (1 << 31)
Michel Dänzerb9b603d2006-08-07 20:41:53 +1000[diff] [blame]840#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
841# define RADEON_RB3D_DC_FLUSH (3 << 0)
842# define RADEON_RB3D_DC_FREE (3 << 2)
843# define RADEON_RB3D_DC_FLUSH_ALL 0xf
844# define RADEON_RB3D_DC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]845#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]846# define R300_RB3D_DC_FLUSH (2 << 0)
847# define R300_RB3D_DC_FREE (2 << 2)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]848# define R300_RB3D_DC_FINISH (1 << 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]849#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
850# define RADEON_Z_TEST_MASK (7 << 4)
851# define RADEON_Z_TEST_ALWAYS (7 << 4)
852# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
853# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
854# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
855# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
856# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
857# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
858# define RADEON_FORCE_Z_DIRTY (1 << 29)
859# define RADEON_Z_WRITE_ENABLE (1 << 30)
860# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
861#define RADEON_RBBM_SOFT_RESET 0x00f0
862# define RADEON_SOFT_RESET_CP (1 << 0)
863# define RADEON_SOFT_RESET_HI (1 << 1)
864# define RADEON_SOFT_RESET_SE (1 << 2)
865# define RADEON_SOFT_RESET_RE (1 << 3)
866# define RADEON_SOFT_RESET_PP (1 << 4)
867# define RADEON_SOFT_RESET_E2 (1 << 5)
868# define RADEON_SOFT_RESET_RB (1 << 6)
869# define RADEON_SOFT_RESET_HDP (1 << 7)
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]870/*
871 * 6:0 Available slots in the FIFO
872 * 8 Host Interface active
873 * 9 CP request active
874 * 10 FIFO request active
875 * 11 Host Interface retry active
876 * 12 CP retry active
877 * 13 FIFO retry active
878 * 14 FIFO pipeline busy
879 * 15 Event engine busy
880 * 16 CP command stream busy
881 * 17 2D engine busy
882 * 18 2D portion of render backend busy
883 * 20 3D setup engine busy
884 * 26 GA engine busy
885 * 27 CBA 2D engine busy
886 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
887 * command stream queue not empty or Ring Buffer not empty
888 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]889#define RADEON_RBBM_STATUS 0x0e40
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]890/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
891/* #define RADEON_RBBM_STATUS 0x1740 */
892/* bits 6:0 are dword slots available in the cmd fifo */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]893# define RADEON_RBBM_FIFOCNT_MASK 0x007f
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]894# define RADEON_HIRQ_ON_RBB (1 << 8)
895# define RADEON_CPRQ_ON_RBB (1 << 9)
896# define RADEON_CFRQ_ON_RBB (1 << 10)
897# define RADEON_HIRQ_IN_RTBUF (1 << 11)
898# define RADEON_CPRQ_IN_RTBUF (1 << 12)
899# define RADEON_CFRQ_IN_RTBUF (1 << 13)
900# define RADEON_PIPE_BUSY (1 << 14)
901# define RADEON_ENG_EV_BUSY (1 << 15)
902# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
903# define RADEON_E2_BUSY (1 << 17)
904# define RADEON_RB2D_BUSY (1 << 18)
905# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
906# define RADEON_VAP_BUSY (1 << 20)
907# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
908# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
909# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
910# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
911# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
912# define RADEON_GA_BUSY (1 << 26)
913# define RADEON_CBA2D_BUSY (1 << 27)
914# define RADEON_RBBM_ACTIVE (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]915#define RADEON_RE_LINE_PATTERN 0x1cd0
916#define RADEON_RE_MISC 0x26c4
917#define RADEON_RE_TOP_LEFT 0x26c0
918#define RADEON_RE_WIDTH_HEIGHT 0x1c44
919#define RADEON_RE_STIPPLE_ADDR 0x1cc8
920#define RADEON_RE_STIPPLE_DATA 0x1ccc
921
922#define RADEON_SCISSOR_TL_0 0x1cd8
923#define RADEON_SCISSOR_BR_0 0x1cdc
924#define RADEON_SCISSOR_TL_1 0x1ce0
925#define RADEON_SCISSOR_BR_1 0x1ce4
926#define RADEON_SCISSOR_TL_2 0x1ce8
927#define RADEON_SCISSOR_BR_2 0x1cec
928#define RADEON_SE_COORD_FMT 0x1c50
929#define RADEON_SE_CNTL 0x1c4c
930# define RADEON_FFACE_CULL_CW (0 << 0)
931# define RADEON_BFACE_SOLID (3 << 1)
932# define RADEON_FFACE_SOLID (3 << 3)
933# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
934# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
935# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
936# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
937# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
938# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
939# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
940# define RADEON_FOG_SHADE_FLAT (1 << 14)
941# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
942# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
943# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
944# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
945# define RADEON_ROUND_MODE_TRUNC (0 << 28)
946# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
947#define RADEON_SE_CNTL_STATUS 0x2140
948#define RADEON_SE_LINE_WIDTH 0x1db8
949#define RADEON_SE_VPORT_XSCALE 0x1d98
950#define RADEON_SE_ZBIAS_FACTOR 0x1db0
951#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
952#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
953#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
954# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
955# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
956#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
957#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
958# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
959#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
960#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
961#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
962#define RADEON_SURFACE_CNTL 0x0b00
963# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
964# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
965# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
966# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
967# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
968# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
969# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
970# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
971# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
972#define RADEON_SURFACE0_INFO 0x0b0c
973# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
974# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
975# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
976# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
977# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
978# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
979#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
980#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
981# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
982#define RADEON_SURFACE1_INFO 0x0b1c
983#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
984#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
985#define RADEON_SURFACE2_INFO 0x0b2c
986#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
987#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
988#define RADEON_SURFACE3_INFO 0x0b3c
989#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
990#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
991#define RADEON_SURFACE4_INFO 0x0b4c
992#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
993#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
994#define RADEON_SURFACE5_INFO 0x0b5c
995#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
996#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
997#define RADEON_SURFACE6_INFO 0x0b6c
998#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
999#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1000#define RADEON_SURFACE7_INFO 0x0b7c
1001#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1002#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1003#define RADEON_SW_SEMAPHORE 0x013c
1004
1005#define RADEON_WAIT_UNTIL 0x1720
1006# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]1007# define RADEON_WAIT_2D_IDLE (1 << 14)
1008# define RADEON_WAIT_3D_IDLE (1 << 15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1009# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1010# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1011# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1012
1013#define RADEON_RB3D_ZMASKOFFSET 0x3234
1014#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1015# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1016# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1017
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1018/* CP registers */
1019#define RADEON_CP_ME_RAM_ADDR 0x07d4
1020#define RADEON_CP_ME_RAM_RADDR 0x07d8
1021#define RADEON_CP_ME_RAM_DATAH 0x07dc
1022#define RADEON_CP_ME_RAM_DATAL 0x07e0
1023
1024#define RADEON_CP_RB_BASE 0x0700
1025#define RADEON_CP_RB_CNTL 0x0704
1026# define RADEON_BUF_SWAP_32BIT (2 << 16)
Michel Dänzerae1b1a482006-08-07 20:37:46 +1000[diff] [blame]1027# define RADEON_RB_NO_UPDATE (1 << 27)
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1028# define RADEON_RB_RPTR_WR_ENA (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1029#define RADEON_CP_RB_RPTR_ADDR 0x070c
1030#define RADEON_CP_RB_RPTR 0x0710
1031#define RADEON_CP_RB_WPTR 0x0714
1032
1033#define RADEON_CP_RB_WPTR_DELAY 0x0718
1034# define RADEON_PRE_WRITE_TIMER_SHIFT 0
1035# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1036
1037#define RADEON_CP_IB_BASE 0x0738
1038
1039#define RADEON_CP_CSQ_CNTL 0x0740
1040# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1041# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1042# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1043# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1044# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1045# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1046# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1047
Alex Deucheraadd4e12009-09-21 14:48:45 +1000[diff] [blame]1048#define R300_CP_RESYNC_ADDR 0x0778
1049#define R300_CP_RESYNC_DATA 0x077c
1050
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1051#define RADEON_AIC_CNTL 0x01d0
1052# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]1053# define RS400_MSI_REARM (1 << 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1054#define RADEON_AIC_STAT 0x01d4
1055#define RADEON_AIC_PT_BASE 0x01d8
1056#define RADEON_AIC_LO_ADDR 0x01dc
1057#define RADEON_AIC_HI_ADDR 0x01e0
1058#define RADEON_AIC_TLB_ADDR 0x01e4
1059#define RADEON_AIC_TLB_DATA 0x01e8
1060
1061/* CP command packets */
1062#define RADEON_CP_PACKET0 0x00000000
1063# define RADEON_ONE_REG_WR (1 << 15)
1064#define RADEON_CP_PACKET1 0x40000000
1065#define RADEON_CP_PACKET2 0x80000000
1066#define RADEON_CP_PACKET3 0xC0000000
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1067# define RADEON_CP_NOP 0x00001000
1068# define RADEON_CP_NEXT_CHAR 0x00001900
1069# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1070# define RADEON_CP_SET_SCISSORS 0x00001E00
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1071 /* GEN_INDX_PRIM is unsupported starting with R300 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1072# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1073# define RADEON_WAIT_FOR_IDLE 0x00002600
1074# define RADEON_3D_DRAW_VBUF 0x00002800
1075# define RADEON_3D_DRAW_IMMD 0x00002900
1076# define RADEON_3D_DRAW_INDX 0x00002A00
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1077# define RADEON_CP_LOAD_PALETTE 0x00002C00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1078# define RADEON_3D_LOAD_VBPNTR 0x00002F00
1079# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1080# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1081# define RADEON_3D_CLEAR_ZMASK 0x00003200
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1082# define RADEON_CP_INDX_BUFFER 0x00003300
1083# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1084# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1085# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1086# define RADEON_3D_CLEAR_HIZ 0x00003700
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1087# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1088# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1089# define RADEON_CNTL_PAINT_MULTI 0x00009A00
1090# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1091# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1092
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1093# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1094# define R600_IT_SET_PREDICATION 0x00002000
1095# define R600_IT_REG_RMW 0x00002100
1096# define R600_IT_COND_EXEC 0x00002200
1097# define R600_IT_PRED_EXEC 0x00002300
1098# define R600_IT_START_3D_CMDBUF 0x00002400
1099# define R600_IT_DRAW_INDEX_2 0x00002700
1100# define R600_IT_CONTEXT_CONTROL 0x00002800
1101# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1102# define R600_IT_INDEX_TYPE 0x00002A00
1103# define R600_IT_DRAW_INDEX 0x00002B00
1104# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1105# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1106# define R600_IT_NUM_INSTANCES 0x00002F00
1107# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1108# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1109# define R600_IT_MEM_SEMAPHORE 0x00003900
1110# define R600_IT_MPEG_INDEX 0x00003A00
1111# define R600_IT_WAIT_REG_MEM 0x00003C00
1112# define R600_IT_MEM_WRITE 0x00003D00
1113# define R600_IT_INDIRECT_BUFFER 0x00003200
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1114# define R600_IT_SURFACE_SYNC 0x00004300
1115# define R600_CB0_DEST_BASE_ENA (1 << 6)
1116# define R600_TC_ACTION_ENA (1 << 23)
1117# define R600_VC_ACTION_ENA (1 << 24)
1118# define R600_CB_ACTION_ENA (1 << 25)
1119# define R600_DB_ACTION_ENA (1 << 26)
1120# define R600_SH_ACTION_ENA (1 << 27)
1121# define R600_SMX_ACTION_ENA (1 << 28)
1122# define R600_IT_ME_INITIALIZE 0x00004400
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1123# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1124# define R600_IT_COND_WRITE 0x00004500
1125# define R600_IT_EVENT_WRITE 0x00004600
1126# define R600_IT_EVENT_WRITE_EOP 0x00004700
1127# define R600_IT_ONE_REG_WRITE 0x00005700
1128# define R600_IT_SET_CONFIG_REG 0x00006800
1129# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1130# define R600_SET_CONFIG_REG_END 0x0000ac00
1131# define R600_IT_SET_CONTEXT_REG 0x00006900
1132# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1133# define R600_SET_CONTEXT_REG_END 0x00029000
1134# define R600_IT_SET_ALU_CONST 0x00006A00
1135# define R600_SET_ALU_CONST_OFFSET 0x00030000
1136# define R600_SET_ALU_CONST_END 0x00032000
1137# define R600_IT_SET_BOOL_CONST 0x00006B00
1138# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1139# define R600_SET_BOOL_CONST_END 0x00040000
1140# define R600_IT_SET_LOOP_CONST 0x00006C00
1141# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1142# define R600_SET_LOOP_CONST_END 0x0003e380
1143# define R600_IT_SET_RESOURCE 0x00006D00
1144# define R600_SET_RESOURCE_OFFSET 0x00038000
1145# define R600_SET_RESOURCE_END 0x0003c000
1146# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1147# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1148# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1149# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1150# define R600_IT_SET_SAMPLER 0x00006E00
1151# define R600_SET_SAMPLER_OFFSET 0x0003c000
1152# define R600_SET_SAMPLER_END 0x0003cff0
1153# define R600_IT_SET_CTL_CONST 0x00006F00
1154# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1155# define R600_SET_CTL_CONST_END 0x0003e200
1156# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1157
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1158#define RADEON_CP_PACKET_MASK 0xC0000000
1159#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1160#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1161#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1162#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1163
1164#define RADEON_VTX_Z_PRESENT (1 << 31)
1165#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1166
1167#define RADEON_PRIM_TYPE_NONE (0 << 0)
1168#define RADEON_PRIM_TYPE_POINT (1 << 0)
1169#define RADEON_PRIM_TYPE_LINE (2 << 0)
1170#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1171#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1172#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1173#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1174#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1175#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1176#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1177#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1178#define RADEON_PRIM_TYPE_MASK 0xf
1179#define RADEON_PRIM_WALK_IND (1 << 4)
1180#define RADEON_PRIM_WALK_LIST (2 << 4)
1181#define RADEON_PRIM_WALK_RING (3 << 4)
1182#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1183#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1184#define RADEON_MAOS_ENABLE (1 << 7)
1185#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1186#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1187#define RADEON_NUM_VERTICES_SHIFT 16
1188
1189#define RADEON_COLOR_FORMAT_CI8 2
1190#define RADEON_COLOR_FORMAT_ARGB1555 3
1191#define RADEON_COLOR_FORMAT_RGB565 4
1192#define RADEON_COLOR_FORMAT_ARGB8888 6
1193#define RADEON_COLOR_FORMAT_RGB332 7
1194#define RADEON_COLOR_FORMAT_RGB8 9
1195#define RADEON_COLOR_FORMAT_ARGB4444 15
1196
1197#define RADEON_TXFORMAT_I8 0
1198#define RADEON_TXFORMAT_AI88 1
1199#define RADEON_TXFORMAT_RGB332 2
1200#define RADEON_TXFORMAT_ARGB1555 3
1201#define RADEON_TXFORMAT_RGB565 4
1202#define RADEON_TXFORMAT_ARGB4444 5
1203#define RADEON_TXFORMAT_ARGB8888 6
1204#define RADEON_TXFORMAT_RGBA8888 7
1205#define RADEON_TXFORMAT_Y8 8
1206#define RADEON_TXFORMAT_VYUY422 10
1207#define RADEON_TXFORMAT_YVYU422 11
1208#define RADEON_TXFORMAT_DXT1 12
1209#define RADEON_TXFORMAT_DXT23 14
1210#define RADEON_TXFORMAT_DXT45 15
1211
1212#define R200_PP_TXCBLEND_0 0x2f00
1213#define R200_PP_TXCBLEND_1 0x2f10
1214#define R200_PP_TXCBLEND_2 0x2f20
1215#define R200_PP_TXCBLEND_3 0x2f30
1216#define R200_PP_TXCBLEND_4 0x2f40
1217#define R200_PP_TXCBLEND_5 0x2f50
1218#define R200_PP_TXCBLEND_6 0x2f60
1219#define R200_PP_TXCBLEND_7 0x2f70
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1220#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1221#define R200_PP_TFACTOR_0 0x2ee0
1222#define R200_SE_VTX_FMT_0 0x2088
1223#define R200_SE_VAP_CNTL 0x2080
1224#define R200_SE_TCL_MATRIX_SEL_0 0x2230
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1225#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1226#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1227#define R200_PP_TXFILTER_5 0x2ca0
1228#define R200_PP_TXFILTER_4 0x2c80
1229#define R200_PP_TXFILTER_3 0x2c60
1230#define R200_PP_TXFILTER_2 0x2c40
1231#define R200_PP_TXFILTER_1 0x2c20
1232#define R200_PP_TXFILTER_0 0x2c00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1233#define R200_PP_TXOFFSET_5 0x2d78
1234#define R200_PP_TXOFFSET_4 0x2d60
1235#define R200_PP_TXOFFSET_3 0x2d48
1236#define R200_PP_TXOFFSET_2 0x2d30
1237#define R200_PP_TXOFFSET_1 0x2d18
1238#define R200_PP_TXOFFSET_0 0x2d00
1239
1240#define R200_PP_CUBIC_FACES_0 0x2c18
1241#define R200_PP_CUBIC_FACES_1 0x2c38
1242#define R200_PP_CUBIC_FACES_2 0x2c58
1243#define R200_PP_CUBIC_FACES_3 0x2c78
1244#define R200_PP_CUBIC_FACES_4 0x2c98
1245#define R200_PP_CUBIC_FACES_5 0x2cb8
1246#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1247#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1248#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1249#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1250#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1251#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1252#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1253#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1254#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1255#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1256#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1257#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1258#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1259#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1260#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1261#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1262#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1263#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1264#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1265#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1266#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1267#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1268#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1269#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1270#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1271#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1272#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1273#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1274#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1275#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1276
1277#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1278#define R200_SE_VTE_CNTL 0x20b0
1279#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1280#define R200_PP_TAM_DEBUG3 0x2d9c
1281#define R200_PP_CNTL_X 0x2cc4
1282#define R200_SE_VAP_CNTL_STATUS 0x2140
1283#define R200_RE_SCISSOR_TL_0 0x1cd8
1284#define R200_RE_SCISSOR_TL_1 0x1ce0
1285#define R200_RE_SCISSOR_TL_2 0x1ce8
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1286#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1287#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1288#define R200_SE_VTX_STATE_CNTL 0x2180
1289#define R200_RE_POINTSIZE 0x2648
1290#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1291
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1292#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1293#define RADEON_PP_TEX_SIZE_1 0x1d0c
1294#define RADEON_PP_TEX_SIZE_2 0x1d14
1295
1296#define RADEON_PP_CUBIC_FACES_0 0x1d24
1297#define RADEON_PP_CUBIC_FACES_1 0x1d28
1298#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1299#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1300#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1301#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1302
Dave Airlief2a22792006-06-24 16:55:34 +1000[diff] [blame]1303#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1304
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1305#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1306#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1307#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1308#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1309#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1310#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1311#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1312#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1313#define R200_3D_DRAW_IMMD_2 0xC0003500
1314#define R200_SE_VTX_FMT_1 0x208c
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1315#define R200_RE_CNTL 0x1c50
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1316
1317#define R200_RB3D_BLENDCOLOR 0x3218
1318
1319#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1320
1321#define R200_PP_TRI_PERF 0x2cf8
1322
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]1323#define R200_PP_AFS_0 0x2f80
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1324#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]1325
Dave Airlied6fece02006-06-24 17:04:07 +1000[diff] [blame]1326#define R200_VAP_PVS_CNTL_1 0x22D0
1327
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]1328#define RADEON_CRTC_CRNT_FRAME 0x0214
1329#define RADEON_CRTC2_CRNT_FRAME 0x0314
1330
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]1331#define R500_D1CRTC_STATUS 0x609c
1332#define R500_D2CRTC_STATUS 0x689c
1333#define R500_CRTC_V_BLANK (1<<0)
1334
1335#define R500_D1CRTC_FRAME_COUNT 0x60a4
1336#define R500_D2CRTC_FRAME_COUNT 0x68a4
1337
1338#define R500_D1MODE_V_COUNTER 0x6530
1339#define R500_D2MODE_V_COUNTER 0x6d30
1340
1341#define R500_D1MODE_VBLANK_STATUS 0x6534
1342#define R500_D2MODE_VBLANK_STATUS 0x6d34
1343#define R500_VBLANK_OCCURED (1<<0)
1344#define R500_VBLANK_ACK (1<<4)
1345#define R500_VBLANK_STAT (1<<12)
1346#define R500_VBLANK_INT (1<<16)
1347
1348#define R500_DxMODE_INT_MASK 0x6540
1349#define R500_D1MODE_INT_MASK (1<<0)
1350#define R500_D2MODE_INT_MASK (1<<8)
1351
1352#define R500_DISP_INTERRUPT_STATUS 0x7edc
1353#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1354#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1355
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1356/* R6xx/R7xx registers */
1357#define R600_MC_VM_FB_LOCATION 0x2180
1358#define R600_MC_VM_AGP_TOP 0x2184
1359#define R600_MC_VM_AGP_BOT 0x2188
1360#define R600_MC_VM_AGP_BASE 0x218c
1361#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1362#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1363#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1364
1365#define R700_MC_VM_FB_LOCATION 0x2024
1366#define R700_MC_VM_AGP_TOP 0x2028
1367#define R700_MC_VM_AGP_BOT 0x202c
1368#define R700_MC_VM_AGP_BASE 0x2030
1369#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1370#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1371#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1372
1373#define R600_MCD_RD_A_CNTL 0x219c
1374#define R600_MCD_RD_B_CNTL 0x21a0
1375
1376#define R600_MCD_WR_A_CNTL 0x21a4
1377#define R600_MCD_WR_B_CNTL 0x21a8
1378
1379#define R600_MCD_RD_SYS_CNTL 0x2200
1380#define R600_MCD_WR_SYS_CNTL 0x2214
1381
1382#define R600_MCD_RD_GFX_CNTL 0x21fc
1383#define R600_MCD_RD_HDP_CNTL 0x2204
1384#define R600_MCD_RD_PDMA_CNTL 0x2208
1385#define R600_MCD_RD_SEM_CNTL 0x220c
1386#define R600_MCD_WR_GFX_CNTL 0x2210
1387#define R600_MCD_WR_HDP_CNTL 0x2218
1388#define R600_MCD_WR_PDMA_CNTL 0x221c
1389#define R600_MCD_WR_SEM_CNTL 0x2220
1390
1391# define R600_MCD_L1_TLB (1 << 0)
1392# define R600_MCD_L1_FRAG_PROC (1 << 1)
1393# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1394
1395# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1396# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1397# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1398# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1399# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1400
1401# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1402# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1403
1404# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1405# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1406# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1407# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1408
1409#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1410#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1411#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1412
1413#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1414#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1415#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1416#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1417
1418# define R700_ENABLE_L1_TLB (1 << 0)
1419# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1420# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1421# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1422# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1423# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1424
1425#define R700_MC_ARB_RAMCFG 0x2760
1426# define R700_NOOFBANK_SHIFT 0
1427# define R700_NOOFBANK_MASK 0x3
1428# define R700_NOOFRANK_SHIFT 2
1429# define R700_NOOFRANK_MASK 0x1
1430# define R700_NOOFROWS_SHIFT 3
1431# define R700_NOOFROWS_MASK 0x7
1432# define R700_NOOFCOLS_SHIFT 6
1433# define R700_NOOFCOLS_MASK 0x3
1434# define R700_CHANSIZE_SHIFT 8
1435# define R700_CHANSIZE_MASK 0x1
1436# define R700_BURSTLENGTH_SHIFT 9
1437# define R700_BURSTLENGTH_MASK 0x1
1438#define R600_RAMCFG 0x2408
1439# define R600_NOOFBANK_SHIFT 0
1440# define R600_NOOFBANK_MASK 0x1
1441# define R600_NOOFRANK_SHIFT 1
1442# define R600_NOOFRANK_MASK 0x1
1443# define R600_NOOFROWS_SHIFT 2
1444# define R600_NOOFROWS_MASK 0x7
1445# define R600_NOOFCOLS_SHIFT 5
1446# define R600_NOOFCOLS_MASK 0x3
1447# define R600_CHANSIZE_SHIFT 7
1448# define R600_CHANSIZE_MASK 0x1
1449# define R600_BURSTLENGTH_SHIFT 8
1450# define R600_BURSTLENGTH_MASK 0x1
1451
1452#define R600_VM_L2_CNTL 0x1400
1453# define R600_VM_L2_CACHE_EN (1 << 0)
1454# define R600_VM_L2_FRAG_PROC (1 << 1)
1455# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1456# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1457# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1458
1459#define R600_VM_L2_CNTL2 0x1404
1460# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1461# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1462#define R600_VM_L2_CNTL3 0x1408
1463# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1464# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1465# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1466# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1467# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1468
1469#define R600_VM_L2_STATUS 0x140c
1470
1471#define R600_VM_CONTEXT0_CNTL 0x1410
1472# define R600_VM_ENABLE_CONTEXT (1 << 0)
1473# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1474
1475#define R600_VM_CONTEXT0_CNTL2 0x1430
1476#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1477#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1478#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1479#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1480#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1481#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1482
1483#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1484#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1485#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1486
1487#define R600_HDP_HOST_PATH_CNTL 0x2c00
1488
1489#define R600_GRBM_CNTL 0x8000
1490# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1491
1492#define R600_GRBM_STATUS 0x8010
1493# define R600_CMDFIFO_AVAIL_MASK 0x1f
1494# define R700_CMDFIFO_AVAIL_MASK 0xf
1495# define R600_GUI_ACTIVE (1 << 31)
1496#define R600_GRBM_STATUS2 0x8014
1497#define R600_GRBM_SOFT_RESET 0x8020
1498# define R600_SOFT_RESET_CP (1 << 0)
1499#define R600_WAIT_UNTIL 0x8040
1500
1501#define R600_CP_SEM_WAIT_TIMER 0x85bc
1502#define R600_CP_ME_CNTL 0x86d8
1503# define R600_CP_ME_HALT (1 << 28)
1504#define R600_CP_QUEUE_THRESHOLDS 0x8760
1505# define R600_ROQ_IB1_START(x) ((x) << 0)
1506# define R600_ROQ_IB2_START(x) ((x) << 8)
1507#define R600_CP_MEQ_THRESHOLDS 0x8764
1508# define R700_STQ_SPLIT(x) ((x) << 0)
1509# define R600_MEQ_END(x) ((x) << 16)
1510# define R600_ROQ_END(x) ((x) << 24)
1511#define R600_CP_PERFMON_CNTL 0x87fc
1512#define R600_CP_RB_BASE 0xc100
1513#define R600_CP_RB_CNTL 0xc104
1514# define R600_RB_BUFSZ(x) ((x) << 0)
1515# define R600_RB_BLKSZ(x) ((x) << 8)
1516# define R600_RB_NO_UPDATE (1 << 27)
1517# define R600_RB_RPTR_WR_ENA (1 << 31)
1518#define R600_CP_RB_RPTR_WR 0xc108
1519#define R600_CP_RB_RPTR_ADDR 0xc10c
1520#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1521#define R600_CP_RB_WPTR 0xc114
1522#define R600_CP_RB_WPTR_ADDR 0xc118
1523#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1524#define R600_CP_RB_RPTR 0x8700
1525#define R600_CP_RB_WPTR_DELAY 0x8704
1526#define R600_CP_PFP_UCODE_ADDR 0xc150
1527#define R600_CP_PFP_UCODE_DATA 0xc154
1528#define R600_CP_ME_RAM_RADDR 0xc158
1529#define R600_CP_ME_RAM_WADDR 0xc15c
1530#define R600_CP_ME_RAM_DATA 0xc160
1531#define R600_CP_DEBUG 0xc1fc
1532
1533#define R600_PA_CL_ENHANCE 0x8a14
1534# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1535# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1536#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1537#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1538#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1539# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1540# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1541#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1542#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1543#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1544#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1545# define R600_S0_X(x) ((x) << 0)
1546# define R600_S0_Y(x) ((x) << 4)
1547# define R600_S1_X(x) ((x) << 8)
1548# define R600_S1_Y(x) ((x) << 12)
1549# define R600_S2_X(x) ((x) << 16)
1550# define R600_S2_Y(x) ((x) << 20)
1551# define R600_S3_X(x) ((x) << 24)
1552# define R600_S3_Y(x) ((x) << 28)
1553# define R600_S4_X(x) ((x) << 0)
1554# define R600_S4_Y(x) ((x) << 4)
1555# define R600_S5_X(x) ((x) << 8)
1556# define R600_S5_Y(x) ((x) << 12)
1557# define R600_S6_X(x) ((x) << 16)
1558# define R600_S6_Y(x) ((x) << 20)
1559# define R600_S7_X(x) ((x) << 24)
1560# define R600_S7_Y(x) ((x) << 28)
1561#define R600_PA_SC_FIFO_SIZE 0x8bd0
1562# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1563# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1564# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1565#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1566# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1567# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1568# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1569#define R600_PA_SC_ENHANCE 0x8bf0
1570# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1571# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1572#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1573#define R700_PA_SC_EDGERULE 0x28230
1574#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1575#define R600_PA_SC_MODE_CNTL 0x28a4c
1576#define R600_PA_SC_AA_CONFIG 0x28c04
1577
1578#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1579# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1580# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1581# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1582#define R600_SX_DEBUG_1 0x9054
1583# define R600_SMX_EVENT_RELEASE (1 << 0)
1584# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1585#define R700_SX_DEBUG_1 0x9058
1586# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1587#define R600_SX_MISC 0x28350
1588
1589#define R600_DB_DEBUG 0x9830
1590# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1591#define R600_DB_WATERMARKS 0x9838
1592# define R600_DEPTH_FREE(x) ((x) << 0)
1593# define R600_DEPTH_FLUSH(x) ((x) << 5)
1594# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1595# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1596#define R700_DB_DEBUG3 0x98b0
1597# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1598#define RV700_DB_DEBUG4 0x9b8c
1599# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1600
1601#define R600_VGT_CACHE_INVALIDATION 0x88c4
1602# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1603# define R600_VC_ONLY 0
1604# define R600_TC_ONLY 1
1605# define R600_VC_AND_TC 2
1606# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1607# define R700_NO_AUTO 0
1608# define R700_ES_AUTO 1
1609# define R700_GS_AUTO 2
1610# define R700_ES_AND_GS_AUTO 3
1611#define R600_VGT_GS_PER_ES 0x88c8
1612#define R600_VGT_ES_PER_GS 0x88cc
1613#define R600_VGT_GS_PER_VS 0x88e8
1614#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1615#define R600_VGT_NUM_INSTANCES 0x8974
1616#define R600_VGT_STRMOUT_EN 0x28ab0
1617#define R600_VGT_EVENT_INITIATOR 0x28a90
1618# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1619#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1620# define R600_VTX_REUSE_DEPTH_MASK 0xff
1621#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1622# define R600_DEALLOC_DIST_MASK 0x7f
1623
1624#define R600_CB_COLOR0_BASE 0x28040
1625#define R600_CB_COLOR1_BASE 0x28044
1626#define R600_CB_COLOR2_BASE 0x28048
1627#define R600_CB_COLOR3_BASE 0x2804c
1628#define R600_CB_COLOR4_BASE 0x28050
1629#define R600_CB_COLOR5_BASE 0x28054
1630#define R600_CB_COLOR6_BASE 0x28058
1631#define R600_CB_COLOR7_BASE 0x2805c
1632#define R600_CB_COLOR7_FRAG 0x280fc
1633
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1634#define R600_CB_COLOR0_SIZE 0x28060
1635#define R600_CB_COLOR0_VIEW 0x28080
1636#define R600_CB_COLOR0_INFO 0x280a0
1637#define R600_CB_COLOR0_TILE 0x280c0
1638#define R600_CB_COLOR0_FRAG 0x280e0
1639#define R600_CB_COLOR0_MASK 0x28100
1640
1641#define AVIVO_D1MODE_VLINE_START_END 0x6538
1642#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1643#define R600_CP_COHER_BASE 0x85f8
1644#define R600_DB_DEPTH_BASE 0x2800c
1645#define R600_SQ_PGM_START_FS 0x28894
1646#define R600_SQ_PGM_START_ES 0x28880
1647#define R600_SQ_PGM_START_VS 0x28858
1648#define R600_SQ_PGM_RESOURCES_VS 0x28868
1649#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1650#define R600_SQ_PGM_START_GS 0x2886c
1651#define R600_SQ_PGM_START_PS 0x28840
1652#define R600_SQ_PGM_RESOURCES_PS 0x28850
1653#define R600_SQ_PGM_EXPORTS_PS 0x28854
1654#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1655#define R600_VGT_DMA_BASE 0x287e8
1656#define R600_VGT_DMA_BASE_HI 0x287e4
1657#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1658#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1659#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1660#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1661#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1662#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1663#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1664#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1665#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1666#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1667#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1668#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1669#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1670#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1671#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1672#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1673
1674#define R600_VGT_PRIMITIVE_TYPE 0x8958
1675
1676#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1677#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1678#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1679
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1680#define R600_TC_CNTL 0x9608
1681# define R600_TC_L2_SIZE(x) ((x) << 5)
1682# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1683
1684#define R600_ARB_POP 0x2418
1685# define R600_ENABLE_TC128 (1 << 30)
1686#define R600_ARB_GDEC_RD_CNTL 0x246c
1687
1688#define R600_TA_CNTL_AUX 0x9508
1689# define R600_DISABLE_CUBE_WRAP (1 << 0)
1690# define R600_DISABLE_CUBE_ANISO (1 << 1)
1691# define R700_GETLOD_SELECT(x) ((x) << 2)
1692# define R600_SYNC_GRADIENT (1 << 24)
1693# define R600_SYNC_WALKER (1 << 25)
1694# define R600_SYNC_ALIGNER (1 << 26)
1695# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1696# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1697
1698#define R700_TCP_CNTL 0x9610
1699
1700#define R600_SMX_DC_CTL0 0xa020
1701# define R700_USE_HASH_FUNCTION (1 << 0)
1702# define R700_CACHE_DEPTH(x) ((x) << 1)
1703# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1704# define R700_STALL_ON_EVENT (1 << 11)
1705#define R700_SMX_EVENT_CTL 0xa02c
1706# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1707# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1708# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1709# define R700_SYNC_FLUSH_CTL (1 << 8)
1710
1711#define R600_SQ_CONFIG 0x8c00
1712# define R600_VC_ENABLE (1 << 0)
1713# define R600_EXPORT_SRC_C (1 << 1)
1714# define R600_DX9_CONSTS (1 << 2)
1715# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1716# define R600_DX10_CLAMP (1 << 4)
1717# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1718# define R600_PS_PRIO(x) ((x) << 24)
1719# define R600_VS_PRIO(x) ((x) << 26)
1720# define R600_GS_PRIO(x) ((x) << 28)
1721# define R600_ES_PRIO(x) ((x) << 30)
1722#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1723# define R600_NUM_PS_GPRS(x) ((x) << 0)
1724# define R600_NUM_VS_GPRS(x) ((x) << 16)
1725# define R700_DYN_GPR_ENABLE (1 << 27)
1726# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1727#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1728# define R600_NUM_GS_GPRS(x) ((x) << 0)
1729# define R600_NUM_ES_GPRS(x) ((x) << 16)
1730#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1731# define R600_NUM_PS_THREADS(x) ((x) << 0)
1732# define R600_NUM_VS_THREADS(x) ((x) << 8)
1733# define R600_NUM_GS_THREADS(x) ((x) << 16)
1734# define R600_NUM_ES_THREADS(x) ((x) << 24)
1735#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1736# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1737# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1738#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1739# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1740# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1741#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1742# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1743# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1744# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1745# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1746#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1747# define R700_SIMDA_RING0(x) ((x) << 0)
1748# define R700_SIMDA_RING1(x) ((x) << 8)
1749# define R700_SIMDB_RING0(x) ((x) << 16)
1750# define R700_SIMDB_RING1(x) ((x) << 24)
1751#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1752#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1753#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1754#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1755#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1756#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1757#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1758
1759#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1760# define R600_NUM_INTERP(x) ((x) << 0)
1761# define R600_POSITION_ENA (1 << 8)
1762# define R600_POSITION_CENTROID (1 << 9)
1763# define R600_POSITION_ADDR(x) ((x) << 10)
1764# define R600_PARAM_GEN(x) ((x) << 15)
1765# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1766# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1767# define R600_PERSP_GRADIENT_ENA (1 << 28)
1768# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1769# define R600_POSITION_SAMPLE (1 << 30)
1770# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1771#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1772# define R600_GEN_INDEX_PIX (1 << 0)
1773# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1774# define R600_FRONT_FACE_ENA (1 << 8)
1775# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1776# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1777# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1778# define R600_FOG_ADDR(x) ((x) << 17)
1779# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1780# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1781# define R700_POSITION_ULC (1 << 30)
1782#define R600_SPI_INPUT_Z 0x286d8
1783
1784#define R600_SPI_CONFIG_CNTL 0x9100
1785# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1786# define R600_DISABLE_INTERP_1 (1 << 5)
1787#define R600_SPI_CONFIG_CNTL_1 0x913c
1788# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1789# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1790
1791#define R600_GB_TILING_CONFIG 0x98f0
1792# define R600_PIPE_TILING(x) ((x) << 1)
1793# define R600_BANK_TILING(x) ((x) << 4)
1794# define R600_GROUP_SIZE(x) ((x) << 6)
1795# define R600_ROW_TILING(x) ((x) << 8)
1796# define R600_BANK_SWAPS(x) ((x) << 11)
1797# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1798# define R600_BACKEND_MAP(x) ((x) << 16)
1799#define R600_DCP_TILING_CONFIG 0x6ca0
1800#define R600_HDP_TILING_CONFIG 0x2f3c
1801
1802#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1803#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1804# define R600_BACKEND_DISABLE(x) ((x) << 16)
1805
1806#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1807#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1808# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1809# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1810# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1811# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1812
1813#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1814#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1815#define R700_CGTS_TCC_DISABLE 0x9148
1816#define R700_CGTS_USER_TCC_DISABLE 0x914c
1817
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1818/* Constants */
1819#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1820
1821#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1822#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1823#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1824#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1825#define RADEON_LAST_DISPATCH 1
1826
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1827#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1828#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1829#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1830#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1831
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1832#define RADEON_MAX_VB_AGE 0x7fffffff
1833#define RADEON_MAX_VB_VERTS (0xffff)
1834
1835#define RADEON_RING_HIGH_MARK 128
1836
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1837#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1838
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1839#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1840#define RADEON_WRITE(reg, val) \
1841do { \
1842 if (reg < 0x10000) { \
1843 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1844 } else { \
1845 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1846 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1847 } \
1848} while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1849#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1850#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1851
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1852#define RADEON_WRITE_PLL(addr, val) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1853do { \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1854 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1855 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1856 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1857} while (0)
1858
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1859#define RADEON_WRITE_PCIE(addr, val) \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1860do { \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1861 RADEON_WRITE8(RADEON_PCIE_INDEX, \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1862 ((addr) & 0xff)); \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1863 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1864} while (0)
1865
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1866#define R500_WRITE_MCIND(addr, val) \
1867do { \
1868 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1869 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1870 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1871} while (0)
1872
1873#define RS480_WRITE_MCIND(addr, val) \
1874do { \
1875 RADEON_WRITE(RS480_NB_MC_INDEX, \
1876 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1877 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1878 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1879} while (0)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]1880
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1881#define RS690_WRITE_MCIND(addr, val) \
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]1882do { \
1883 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1884 RADEON_WRITE(RS690_MC_DATA, val); \
1885 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1886} while (0)
1887
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]1888#define RS600_WRITE_MCIND(addr, val) \
1889do { \
1890 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1891 RADEON_WRITE(RS600_MC_DATA, val); \
1892} while (0)
1893
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1894#define IGP_WRITE_MCIND(addr, val) \
1895do { \
Alex Deucherf0738e92008-10-16 17:12:02 +1000[diff] [blame]1896 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1897 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1898 RS690_WRITE_MCIND(addr, val); \
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]1899 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1900 RS600_WRITE_MCIND(addr, val); \
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1901 else \
1902 RS480_WRITE_MCIND(addr, val); \
1903} while (0)
1904
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1905#define CP_PACKET0( reg, n ) \
1906 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1907#define CP_PACKET0_TABLE( reg, n ) \
1908 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1909#define CP_PACKET1( reg0, reg1 ) \
1910 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1911#define CP_PACKET2() \
1912 (RADEON_CP_PACKET2)
1913#define CP_PACKET3( pkt, n ) \
1914 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1915
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1916/* ================================================================
1917 * Engine control helper macros
1918 */
1919
1920#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1921 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1922 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1923 RADEON_WAIT_HOST_IDLECLEAN) ); \
1924} while (0)
1925
1926#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1927 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1928 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1929 RADEON_WAIT_HOST_IDLECLEAN) ); \
1930} while (0)
1931
1932#define RADEON_WAIT_UNTIL_IDLE() do { \
1933 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1934 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1935 RADEON_WAIT_3D_IDLECLEAN | \
1936 RADEON_WAIT_HOST_IDLECLEAN) ); \
1937} while (0)
1938
1939#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1940 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1941 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1942} while (0)
1943
1944#define RADEON_FLUSH_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1945 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1946 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1947 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1948 } else { \
1949 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1950 OUT_RING(R300_RB3D_DC_FLUSH); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1951 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1952} while (0)
1953
1954#define RADEON_PURGE_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1955 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1956 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1957 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1958 } else { \
1959 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1960 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1961 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1962} while (0)
1963
1964#define RADEON_FLUSH_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1965 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1966 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1967 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1968 } else { \
1969 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1970 OUT_RING(R300_ZC_FLUSH); \
1971 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1972} while (0)
1973
1974#define RADEON_PURGE_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1975 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1976 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1977 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1978 } else { \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1979 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1980 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1981 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1982} while (0)
1983
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1984/* ================================================================
1985 * Misc helper macros
1986 */
1987
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1988/* Perfbox functionality only.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1989 */
1990#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1991do { \
1992 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1993 u32 head = GET_RING_HEAD( dev_priv ); \
1994 if (head == dev_priv->ring.tail) \
1995 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1996 } \
1997} while (0)
1998
1999#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]2000do { \
2001 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
2002 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2003 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]2004 int __ret; \
2005 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2006 __ret = r600_do_cp_idle(dev_priv); \
2007 else \
2008 __ret = radeon_do_cp_idle(dev_priv); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2009 if ( __ret ) return __ret; \
2010 sarea_priv->last_dispatch = 0; \
2011 radeon_freelist_reset( dev ); \
2012 } \
2013} while (0)
2014
2015#define RADEON_DISPATCH_AGE( age ) do { \
2016 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2017 OUT_RING( age ); \
2018} while (0)
2019
2020#define RADEON_FRAME_AGE( age ) do { \
2021 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2022 OUT_RING( age ); \
2023} while (0)
2024
2025#define RADEON_CLEAR_AGE( age ) do { \
2026 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2027 OUT_RING( age ); \
2028} while (0)
2029
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]2030#define R600_DISPATCH_AGE(age) do { \
2031 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2032 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2033 OUT_RING(age); \
2034} while (0)
2035
2036#define R600_FRAME_AGE(age) do { \
2037 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2038 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2039 OUT_RING(age); \
2040} while (0)
2041
2042#define R600_CLEAR_AGE(age) do { \
2043 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2044 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2045 OUT_RING(age); \
2046} while (0)
2047
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2048/* ================================================================
2049 * Ring control
2050 */
2051
2052#define RADEON_VERBOSE 0
2053
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2054#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2055
Dave Airlie98638712009-06-04 07:08:13 +1000[diff] [blame]2056#define RADEON_RING_ALIGN 16
2057
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2058#define BEGIN_RING( n ) do { \
2059 if ( RADEON_VERBOSE ) { \
Márton Németh3e684ea2008-01-24 15:58:57 +1000[diff] [blame]2060 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2061 } \
Dave Airlie98638712009-06-04 07:08:13 +1000[diff] [blame]2062 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2063 _align_nr += n; \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2064 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2065 COMMIT_RING(); \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2066 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2067 } \
2068 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2069 ring = dev_priv->ring.start; \
2070 write = dev_priv->ring.tail; \
2071 mask = dev_priv->ring.tail_mask; \
2072} while (0)
2073
2074#define ADVANCE_RING() do { \
2075 if ( RADEON_VERBOSE ) { \
2076 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2077 write, dev_priv->ring.tail ); \
2078 } \
2079 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]2080 DRM_ERROR( \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2081 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2082 ((dev_priv->ring.tail + _nr) & mask), \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2083 write, __LINE__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2084 } else \
2085 dev_priv->ring.tail = write; \
2086} while (0)
2087
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2088extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2089
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2090#define COMMIT_RING() do { \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2091 radeon_commit_ring(dev_priv); \
2092 } while(0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2093
2094#define OUT_RING( x ) do { \
2095 if ( RADEON_VERBOSE ) { \
2096 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2097 (unsigned int)(x), write ); \
2098 } \
2099 ring[write++] = (x); \
2100 write &= mask; \
2101} while (0)
2102
2103#define OUT_RING_REG( reg, val ) do { \
2104 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2105 OUT_RING( val ); \
2106} while (0)
2107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2108#define OUT_RING_TABLE( tab, sz ) do { \
2109 int _size = (sz); \
2110 int *_tab = (int *)(tab); \
2111 \
2112 if (write + _size > mask) { \
2113 int _i = (mask+1) - write; \
2114 _size -= _i; \
2115 while (_i > 0 ) { \
2116 *(int *)(ring + write) = *_tab++; \
2117 write++; \
2118 _i--; \
2119 } \
2120 write = 0; \
2121 _tab += _i; \
2122 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2123 while (_size > 0) { \
2124 *(ring + write) = *_tab++; \
2125 write++; \
2126 _size--; \
2127 } \
2128 write &= mask; \
2129} while (0)
2130
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200[diff] [blame]2131/**
2132 * Copy given number of dwords from drm buffer to the ring buffer.
2133 */
2134#define OUT_RING_DRM_BUFFER(buf, sz) do { \
2135 int _size = (sz) * 4; \
2136 struct drm_buffer *_buf = (buf); \
2137 int _part_size; \
2138 while (_size > 0) { \
2139 _part_size = _size; \
2140 \
2141 if (write + _part_size/4 > mask) \
2142 _part_size = ((mask + 1) - write)*4; \
2143 \
2144 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \
2145 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
2146 \
2147 \
2148 \
2149 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
2150 [drm_buffer_index(_buf)], _part_size); \
2151 \
2152 _size -= _part_size; \
2153 write = (write + _part_size/4) & mask; \
2154 drm_buffer_advance(_buf, _part_size); \
2155 } \
2156} while (0)
2157
2158
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]2159#endif /* __RADEON_DRV_H__ */