Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/clock24xx.h |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * |
| 7 | * Contacts: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 18 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 19 | #include "clock.h" |
| 20 | |
| 21 | #include "prm.h" |
| 22 | #include "cm.h" |
| 23 | #include "prm-regbits-24xx.h" |
| 24 | #include "cm-regbits-24xx.h" |
| 25 | #include "sdrc.h" |
| 26 | |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 27 | static void omap2_table_mpu_recalc(struct clk *clk); |
| 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); |
| 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); |
| 30 | static void omap2_sys_clk_recalc(struct clk *clk); |
| 31 | static void omap2_osc_clk_recalc(struct clk *clk); |
| 32 | static void omap2_sys_clk_recalc(struct clk *clk); |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 33 | static void omap2_dpllcore_recalc(struct clk *clk); |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 34 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 35 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 36 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| 37 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP |
| 38 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM |
| 39 | */ |
| 40 | struct prcm_config { |
| 41 | unsigned long xtal_speed; /* crystal rate */ |
| 42 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ |
| 43 | unsigned long mpu_speed; /* speed of MPU */ |
| 44 | unsigned long cm_clksel_mpu; /* mpu divider */ |
| 45 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ |
| 46 | unsigned long cm_clksel_gfx; /* gfx dividers */ |
| 47 | unsigned long cm_clksel1_core; /* major subsystem dividers */ |
| 48 | unsigned long cm_clksel1_pll; /* m,n */ |
| 49 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ |
| 50 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ |
| 51 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ |
| 52 | unsigned char flags; |
| 53 | }; |
| 54 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 55 | /* |
| 56 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. |
| 57 | * These configurations are characterized by voltage and speed for clocks. |
| 58 | * The device is only validated for certain combinations. One way to express |
| 59 | * these combinations is via the 'ratio's' which the clocks operate with |
| 60 | * respect to each other. These ratio sets are for a given voltage/DPLL |
| 61 | * setting. All configurations can be described by a DPLL setting and a ratio |
| 62 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. |
| 63 | * |
| 64 | * 2430 differs from 2420 in that there are no more phase synchronizers used. |
| 65 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs |
| 66 | * 2430 (iva2.1, NOdsp, mdm) |
| 67 | */ |
| 68 | |
| 69 | /* Core fields for cm_clksel, not ratio governed */ |
| 70 | #define RX_CLKSEL_DSS1 (0x10 << 8) |
| 71 | #define RX_CLKSEL_DSS2 (0x0 << 13) |
| 72 | #define RX_CLKSEL_SSI (0x5 << 20) |
| 73 | |
| 74 | /*------------------------------------------------------------------------- |
| 75 | * Voltage/DPLL ratios |
| 76 | *-------------------------------------------------------------------------*/ |
| 77 | |
| 78 | /* 2430 Ratio's, 2430-Ratio Config 1 */ |
| 79 | #define R1_CLKSEL_L3 (4 << 0) |
| 80 | #define R1_CLKSEL_L4 (2 << 5) |
| 81 | #define R1_CLKSEL_USB (4 << 25) |
| 82 | #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 83 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 84 | R1_CLKSEL_L4 | R1_CLKSEL_L3 |
| 85 | #define R1_CLKSEL_MPU (2 << 0) |
| 86 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU |
| 87 | #define R1_CLKSEL_DSP (2 << 0) |
| 88 | #define R1_CLKSEL_DSP_IF (2 << 5) |
| 89 | #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF |
| 90 | #define R1_CLKSEL_GFX (2 << 0) |
| 91 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX |
| 92 | #define R1_CLKSEL_MDM (4 << 0) |
| 93 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM |
| 94 | |
| 95 | /* 2430-Ratio Config 2 */ |
| 96 | #define R2_CLKSEL_L3 (6 << 0) |
| 97 | #define R2_CLKSEL_L4 (2 << 5) |
| 98 | #define R2_CLKSEL_USB (2 << 25) |
| 99 | #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 100 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 101 | R2_CLKSEL_L4 | R2_CLKSEL_L3 |
| 102 | #define R2_CLKSEL_MPU (2 << 0) |
| 103 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU |
| 104 | #define R2_CLKSEL_DSP (2 << 0) |
| 105 | #define R2_CLKSEL_DSP_IF (3 << 5) |
| 106 | #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF |
| 107 | #define R2_CLKSEL_GFX (2 << 0) |
| 108 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX |
| 109 | #define R2_CLKSEL_MDM (6 << 0) |
| 110 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM |
| 111 | |
| 112 | /* 2430-Ratio Bootm (BYPASS) */ |
| 113 | #define RB_CLKSEL_L3 (1 << 0) |
| 114 | #define RB_CLKSEL_L4 (1 << 5) |
| 115 | #define RB_CLKSEL_USB (1 << 25) |
| 116 | #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 117 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 118 | RB_CLKSEL_L4 | RB_CLKSEL_L3 |
| 119 | #define RB_CLKSEL_MPU (1 << 0) |
| 120 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU |
| 121 | #define RB_CLKSEL_DSP (1 << 0) |
| 122 | #define RB_CLKSEL_DSP_IF (1 << 5) |
| 123 | #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF |
| 124 | #define RB_CLKSEL_GFX (1 << 0) |
| 125 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX |
| 126 | #define RB_CLKSEL_MDM (1 << 0) |
| 127 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM |
| 128 | |
| 129 | /* 2420 Ratio Equivalents */ |
| 130 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) |
| 131 | #define RXX_CLKSEL_SSI (0x8 << 20) |
| 132 | |
| 133 | /* 2420-PRCM III 532MHz core */ |
| 134 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ |
| 135 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ |
| 136 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ |
| 137 | #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ |
| 138 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ |
| 139 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ |
| 140 | RIII_CLKSEL_L3 |
| 141 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ |
| 142 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU |
| 143 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ |
| 144 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ |
| 145 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ |
| 146 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ |
| 147 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ |
| 148 | #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ |
| 149 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ |
| 150 | RIII_CLKSEL_DSP |
| 151 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ |
| 152 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX |
| 153 | |
| 154 | /* 2420-PRCM II 600MHz core */ |
| 155 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ |
| 156 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ |
| 157 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ |
| 158 | #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ |
| 159 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ |
| 160 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 161 | RII_CLKSEL_L4 | RII_CLKSEL_L3 |
| 162 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ |
| 163 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU |
| 164 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ |
| 165 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ |
| 166 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 167 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 168 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ |
| 169 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ |
| 170 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ |
| 171 | RII_CLKSEL_DSP |
| 172 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ |
| 173 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
| 174 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 175 | /* 2420-PRCM I 660MHz core */ |
| 176 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ |
| 177 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ |
| 178 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ |
| 179 | #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ |
| 180 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ |
| 181 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 182 | RI_CLKSEL_L4 | RI_CLKSEL_L3 |
| 183 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ |
| 184 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU |
| 185 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ |
| 186 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ |
| 187 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ |
| 188 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ |
| 189 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ |
| 190 | #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ |
| 191 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ |
| 192 | RI_CLKSEL_DSP |
| 193 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ |
| 194 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX |
| 195 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 196 | /* 2420-PRCM VII (boot) */ |
| 197 | #define RVII_CLKSEL_L3 (1 << 0) |
| 198 | #define RVII_CLKSEL_L4 (1 << 5) |
| 199 | #define RVII_CLKSEL_DSS1 (1 << 8) |
| 200 | #define RVII_CLKSEL_DSS2 (0 << 13) |
| 201 | #define RVII_CLKSEL_VLYNQ (1 << 15) |
| 202 | #define RVII_CLKSEL_SSI (1 << 20) |
| 203 | #define RVII_CLKSEL_USB (1 << 25) |
| 204 | |
| 205 | #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ |
| 206 | RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ |
| 207 | RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 |
| 208 | |
| 209 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ |
| 210 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU |
| 211 | |
| 212 | #define RVII_CLKSEL_DSP (1 << 0) |
| 213 | #define RVII_CLKSEL_DSP_IF (1 << 5) |
| 214 | #define RVII_SYNC_DSP (0 << 7) |
| 215 | #define RVII_CLKSEL_IVA (1 << 8) |
| 216 | #define RVII_SYNC_IVA (0 << 13) |
| 217 | #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ |
| 218 | RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP |
| 219 | |
| 220 | #define RVII_CLKSEL_GFX (1 << 0) |
| 221 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX |
| 222 | |
| 223 | /*------------------------------------------------------------------------- |
| 224 | * 2430 Target modes: Along with each configuration the CPU has several |
| 225 | * modes which goes along with them. Modes mainly are the addition of |
| 226 | * describe DPLL combinations to go along with a ratio. |
| 227 | *-------------------------------------------------------------------------*/ |
| 228 | |
| 229 | /* Hardware governed */ |
| 230 | #define MX_48M_SRC (0 << 3) |
| 231 | #define MX_54M_SRC (0 << 5) |
| 232 | #define MX_APLLS_CLIKIN_12 (3 << 23) |
| 233 | #define MX_APLLS_CLIKIN_13 (2 << 23) |
| 234 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) |
| 235 | |
| 236 | /* |
| 237 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 238 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz |
| 239 | */ |
| 240 | #define M5A_DPLL_MULT_12 (133 << 12) |
| 241 | #define M5A_DPLL_DIV_12 (5 << 8) |
| 242 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 243 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ |
| 244 | MX_APLLS_CLIKIN_12 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 245 | #define M5A_DPLL_MULT_13 (61 << 12) |
| 246 | #define M5A_DPLL_DIV_13 (2 << 8) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 247 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 248 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ |
| 249 | MX_APLLS_CLIKIN_13 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 250 | #define M5A_DPLL_MULT_19 (55 << 12) |
| 251 | #define M5A_DPLL_DIV_19 (3 << 8) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 252 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 253 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ |
| 254 | MX_APLLS_CLIKIN_19_2 |
| 255 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ |
| 256 | #define M5B_DPLL_MULT_12 (50 << 12) |
| 257 | #define M5B_DPLL_DIV_12 (2 << 8) |
| 258 | #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 259 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ |
| 260 | MX_APLLS_CLIKIN_12 |
| 261 | #define M5B_DPLL_MULT_13 (200 << 12) |
| 262 | #define M5B_DPLL_DIV_13 (12 << 8) |
| 263 | |
| 264 | #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 265 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ |
| 266 | MX_APLLS_CLIKIN_13 |
| 267 | #define M5B_DPLL_MULT_19 (125 << 12) |
| 268 | #define M5B_DPLL_DIV_19 (31 << 8) |
| 269 | #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 270 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ |
| 271 | MX_APLLS_CLIKIN_19_2 |
| 272 | /* |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 273 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz |
| 274 | */ |
| 275 | #define M4_DPLL_MULT_12 (133 << 12) |
| 276 | #define M4_DPLL_DIV_12 (3 << 8) |
| 277 | #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 278 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ |
| 279 | MX_APLLS_CLIKIN_12 |
| 280 | |
| 281 | #define M4_DPLL_MULT_13 (399 << 12) |
| 282 | #define M4_DPLL_DIV_13 (12 << 8) |
| 283 | #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 284 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ |
| 285 | MX_APLLS_CLIKIN_13 |
| 286 | |
| 287 | #define M4_DPLL_MULT_19 (145 << 12) |
| 288 | #define M4_DPLL_DIV_19 (6 << 8) |
| 289 | #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 290 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ |
| 291 | MX_APLLS_CLIKIN_19_2 |
| 292 | |
| 293 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 294 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz |
| 295 | */ |
| 296 | #define M3_DPLL_MULT_12 (55 << 12) |
| 297 | #define M3_DPLL_DIV_12 (1 << 8) |
| 298 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 299 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ |
| 300 | MX_APLLS_CLIKIN_12 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 301 | #define M3_DPLL_MULT_13 (76 << 12) |
| 302 | #define M3_DPLL_DIV_13 (2 << 8) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 303 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 304 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ |
| 305 | MX_APLLS_CLIKIN_13 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 306 | #define M3_DPLL_MULT_19 (17 << 12) |
| 307 | #define M3_DPLL_DIV_19 (0 << 8) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 308 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 309 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ |
| 310 | MX_APLLS_CLIKIN_19_2 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 311 | |
| 312 | /* |
| 313 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz |
| 314 | */ |
| 315 | #define M2_DPLL_MULT_12 (55 << 12) |
| 316 | #define M2_DPLL_DIV_12 (1 << 8) |
| 317 | #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 318 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ |
| 319 | MX_APLLS_CLIKIN_12 |
| 320 | |
| 321 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, |
| 322 | * relock time issue */ |
| 323 | /* Core frequency changed from 330/165 to 329/164 MHz*/ |
| 324 | #define M2_DPLL_MULT_13 (76 << 12) |
| 325 | #define M2_DPLL_DIV_13 (2 << 8) |
| 326 | #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 327 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ |
| 328 | MX_APLLS_CLIKIN_13 |
| 329 | |
| 330 | #define M2_DPLL_MULT_19 (17 << 12) |
| 331 | #define M2_DPLL_DIV_19 (0 << 8) |
| 332 | #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 333 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ |
| 334 | MX_APLLS_CLIKIN_19_2 |
| 335 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 336 | /* boot (boot) */ |
| 337 | #define MB_DPLL_MULT (1 << 12) |
| 338 | #define MB_DPLL_DIV (0 << 8) |
| 339 | #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 340 | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 |
| 341 | |
| 342 | #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 343 | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 |
| 344 | |
| 345 | #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 346 | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 |
| 347 | |
| 348 | /* |
| 349 | * 2430 - chassis (sedna) |
| 350 | * 165 (ratio1) same as above #2 |
| 351 | * 150 (ratio1) |
| 352 | * 133 (ratio2) same as above #4 |
| 353 | * 110 (ratio2) same as above #3 |
| 354 | * 104 (ratio2) |
| 355 | * boot (boot) |
| 356 | */ |
| 357 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 358 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ |
| 359 | #define MI_DPLL_MULT_12 (55 << 12) |
| 360 | #define MI_DPLL_DIV_12 (1 << 8) |
| 361 | #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 362 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ |
| 363 | MX_APLLS_CLIKIN_12 |
| 364 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 365 | /* |
| 366 | * 2420 Equivalent - mode registers |
| 367 | * PRCM II , target DPLL = 2*300MHz = 600MHz |
| 368 | */ |
| 369 | #define MII_DPLL_MULT_12 (50 << 12) |
| 370 | #define MII_DPLL_DIV_12 (1 << 8) |
| 371 | #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 372 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ |
| 373 | MX_APLLS_CLIKIN_12 |
| 374 | #define MII_DPLL_MULT_13 (300 << 12) |
| 375 | #define MII_DPLL_DIV_13 (12 << 8) |
| 376 | #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 377 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ |
| 378 | MX_APLLS_CLIKIN_13 |
| 379 | |
| 380 | /* PRCM III target DPLL = 2*266 = 532MHz*/ |
| 381 | #define MIII_DPLL_MULT_12 (133 << 12) |
| 382 | #define MIII_DPLL_DIV_12 (5 << 8) |
| 383 | #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 384 | MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ |
| 385 | MX_APLLS_CLIKIN_12 |
| 386 | #define MIII_DPLL_MULT_13 (266 << 12) |
| 387 | #define MIII_DPLL_DIV_13 (12 << 8) |
| 388 | #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 389 | MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ |
| 390 | MX_APLLS_CLIKIN_13 |
| 391 | |
| 392 | /* PRCM VII (boot bypass) */ |
| 393 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL |
| 394 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL |
| 395 | |
| 396 | /* High and low operation value */ |
| 397 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) |
| 398 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) |
| 399 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 400 | /* MPU speed defines */ |
| 401 | #define S12M 12000000 |
| 402 | #define S13M 13000000 |
| 403 | #define S19M 19200000 |
| 404 | #define S26M 26000000 |
| 405 | #define S100M 100000000 |
| 406 | #define S133M 133000000 |
| 407 | #define S150M 150000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 408 | #define S164M 164000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 409 | #define S165M 165000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 410 | #define S199M 199000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 411 | #define S200M 200000000 |
| 412 | #define S266M 266000000 |
| 413 | #define S300M 300000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 414 | #define S329M 329000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 415 | #define S330M 330000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 416 | #define S399M 399000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 417 | #define S400M 400000000 |
| 418 | #define S532M 532000000 |
| 419 | #define S600M 600000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 420 | #define S658M 658000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 421 | #define S660M 660000000 |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 422 | #define S798M 798000000 |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 423 | |
| 424 | /*------------------------------------------------------------------------- |
| 425 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| 426 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, |
| 427 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, |
| 428 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM |
| 429 | * |
| 430 | * Filling in table based on H4 boards and 2430-SDPs variants available. |
| 431 | * There are quite a few more rates combinations which could be defined. |
| 432 | * |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 433 | * When multiple values are defined the start up will try and choose the |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 434 | * fastest one. If a 'fast' value is defined, then automatically, the /2 |
| 435 | * one should be included as it can be used. Generally having more that |
| 436 | * one fast set does not make sense, as static timings need to be changed |
| 437 | * to change the set. The exception is the bypass setting which is |
| 438 | * availble for low power bypass. |
| 439 | * |
| 440 | * Note: This table needs to be sorted, fastest to slowest. |
| 441 | *-------------------------------------------------------------------------*/ |
| 442 | static struct prcm_config rate_table[] = { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 443 | /* PRCM I - FAST */ |
| 444 | {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ |
| 445 | RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, |
| 446 | RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, |
| 447 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, |
| 448 | RATE_IN_242X}, |
| 449 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 450 | /* PRCM II - FAST */ |
| 451 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
| 452 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 453 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 454 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 455 | RATE_IN_242X}, |
| 456 | |
| 457 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
| 458 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 459 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 460 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 461 | RATE_IN_242X}, |
| 462 | |
| 463 | /* PRCM III - FAST */ |
| 464 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 465 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 466 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 467 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 468 | RATE_IN_242X}, |
| 469 | |
| 470 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 471 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 472 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 473 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 474 | RATE_IN_242X}, |
| 475 | |
| 476 | /* PRCM II - SLOW */ |
| 477 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
| 478 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 479 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 480 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 481 | RATE_IN_242X}, |
| 482 | |
| 483 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
| 484 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 485 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 486 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 487 | RATE_IN_242X}, |
| 488 | |
| 489 | /* PRCM III - SLOW */ |
| 490 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 491 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 492 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 493 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 494 | RATE_IN_242X}, |
| 495 | |
| 496 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 497 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 498 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 499 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 500 | RATE_IN_242X}, |
| 501 | |
| 502 | /* PRCM-VII (boot-bypass) */ |
| 503 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ |
| 504 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
| 505 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 506 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 507 | RATE_IN_242X}, |
| 508 | |
| 509 | /* PRCM-VII (boot-bypass) */ |
| 510 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ |
| 511 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
| 512 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 513 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 514 | RATE_IN_242X}, |
| 515 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 516 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ |
| 517 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 518 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 519 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 520 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 521 | SDRC_RFR_CTRL_133MHz, |
| 522 | RATE_IN_243X}, |
| 523 | |
| 524 | /* PRCM #2 - ratio1 (ES2) - FAST */ |
| 525 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ |
| 526 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 527 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, |
| 528 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 529 | SDRC_RFR_CTRL_165MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 530 | RATE_IN_243X}, |
| 531 | |
| 532 | /* PRCM #5a - ratio1 - FAST */ |
| 533 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 534 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 535 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
| 536 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 537 | SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 538 | RATE_IN_243X}, |
| 539 | |
| 540 | /* PRCM #5b - ratio1 - FAST */ |
| 541 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ |
| 542 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 543 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
| 544 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 545 | SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 546 | RATE_IN_243X}, |
| 547 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 548 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ |
| 549 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 550 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 551 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 552 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 553 | SDRC_RFR_CTRL_133MHz, |
| 554 | RATE_IN_243X}, |
| 555 | |
| 556 | /* PRCM #2 - ratio1 (ES2) - SLOW */ |
| 557 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ |
| 558 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 559 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, |
| 560 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 561 | SDRC_RFR_CTRL_165MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 562 | RATE_IN_243X}, |
| 563 | |
| 564 | /* PRCM #5a - ratio1 - SLOW */ |
| 565 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 566 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 567 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
| 568 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 569 | SDRC_RFR_CTRL_133MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 570 | RATE_IN_243X}, |
| 571 | |
| 572 | /* PRCM #5b - ratio1 - SLOW*/ |
| 573 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ |
| 574 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 575 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
| 576 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 577 | SDRC_RFR_CTRL_100MHz, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 578 | RATE_IN_243X}, |
| 579 | |
| 580 | /* PRCM-boot/bypass */ |
| 581 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ |
| 582 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
| 583 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, |
| 584 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 585 | SDRC_RFR_CTRL_BYPASS, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 586 | RATE_IN_243X}, |
| 587 | |
| 588 | /* PRCM-boot/bypass */ |
| 589 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ |
| 590 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
| 591 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, |
| 592 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 593 | SDRC_RFR_CTRL_BYPASS, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 594 | RATE_IN_243X}, |
| 595 | |
| 596 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
| 597 | }; |
| 598 | |
| 599 | /*------------------------------------------------------------------------- |
| 600 | * 24xx clock tree. |
| 601 | * |
| 602 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
| 603 | * cases the parent is selectable. The get/set parent calls will also |
| 604 | * switch sources. |
| 605 | * |
| 606 | * Many some clocks say always_enabled, but they can be auto idled for |
| 607 | * power savings. They will always be available upon clock request. |
| 608 | * |
| 609 | * Several sources are given initial rates which may be wrong, this will |
| 610 | * be fixed up in the init func. |
| 611 | * |
| 612 | * Things are broadly separated below by clock domains. It is |
| 613 | * noteworthy that most periferals have dependencies on multiple clock |
| 614 | * domains. Many get their interface clocks from the L4 domain, but get |
| 615 | * functional clocks from fixed sources or other core domain derived |
| 616 | * clocks. |
| 617 | *-------------------------------------------------------------------------*/ |
| 618 | |
| 619 | /* Base external input clocks */ |
| 620 | static struct clk func_32k_ck = { |
| 621 | .name = "func_32k_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 622 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 623 | .rate = 32000, |
| 624 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 625 | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 626 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 627 | .recalc = &propagate_rate, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 628 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 629 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 630 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 631 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 632 | .name = "osc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 633 | .ops = &clkops_oscck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 634 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 635 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 636 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 637 | .recalc = &omap2_osc_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 638 | }; |
| 639 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 640 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 641 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 642 | .name = "sys_ck", /* ~ ref_clk also */ |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 643 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 644 | .parent = &osc_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 645 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 646 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 647 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 648 | .recalc = &omap2_sys_clk_recalc, |
| 649 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 650 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 651 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 652 | .name = "alt_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 653 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 654 | .rate = 54000000, |
| 655 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 656 | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 657 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 658 | .recalc = &propagate_rate, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 659 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 660 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 661 | /* |
| 662 | * Analog domain root source clocks |
| 663 | */ |
| 664 | |
| 665 | /* dpll_ck, is broken out in to special cases through clksel */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 666 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
| 667 | * deal with this |
| 668 | */ |
| 669 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 670 | static struct dpll_data dpll_dd = { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 671 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 672 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 673 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 674 | .max_multiplier = 1024, |
| 675 | .max_divider = 16, |
| 676 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 677 | }; |
| 678 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 679 | /* |
| 680 | * XXX Cannot add round_rate here yet, as this is still a composite clock, |
| 681 | * not just a DPLL |
| 682 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 683 | static struct clk dpll_ck = { |
| 684 | .name = "dpll_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 685 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 686 | .parent = &sys_ck, /* Can be func_32k also */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 687 | .dpll_data = &dpll_dd, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 688 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 689 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 690 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 691 | .recalc = &omap2_dpllcore_recalc, |
| 692 | .set_rate = &omap2_reprogram_dpllcore, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 693 | }; |
| 694 | |
| 695 | static struct clk apll96_ck = { |
| 696 | .name = "apll96_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 697 | .ops = &clkops_fixed, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 698 | .parent = &sys_ck, |
| 699 | .rate = 96000000, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 700 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 701 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 702 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 704 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 705 | .recalc = &propagate_rate, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 706 | }; |
| 707 | |
| 708 | static struct clk apll54_ck = { |
| 709 | .name = "apll54_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 710 | .ops = &clkops_fixed, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 711 | .parent = &sys_ck, |
| 712 | .rate = 54000000, |
| 713 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 714 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 715 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 716 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 717 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 718 | .recalc = &propagate_rate, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 719 | }; |
| 720 | |
| 721 | /* |
| 722 | * PRCM digital base sources |
| 723 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 724 | |
| 725 | /* func_54m_ck */ |
| 726 | |
| 727 | static const struct clksel_rate func_54m_apll54_rates[] = { |
| 728 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 729 | { .div = 0 }, |
| 730 | }; |
| 731 | |
| 732 | static const struct clksel_rate func_54m_alt_rates[] = { |
| 733 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 734 | { .div = 0 }, |
| 735 | }; |
| 736 | |
| 737 | static const struct clksel func_54m_clksel[] = { |
| 738 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, |
| 739 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, |
| 740 | { .parent = NULL }, |
| 741 | }; |
| 742 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 743 | static struct clk func_54m_ck = { |
| 744 | .name = "func_54m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 745 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 746 | .parent = &apll54_ck, /* can also be alt_clk */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 747 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 748 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 749 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 750 | .init = &omap2_init_clksel_parent, |
| 751 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 752 | .clksel_mask = OMAP24XX_54M_SOURCE, |
| 753 | .clksel = func_54m_clksel, |
| 754 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 755 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 756 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 757 | static struct clk core_ck = { |
| 758 | .name = "core_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 759 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 760 | .parent = &dpll_ck, /* can also be 32k */ |
| 761 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 762 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 763 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 764 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 765 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 766 | |
| 767 | /* func_96m_ck */ |
| 768 | static const struct clksel_rate func_96m_apll96_rates[] = { |
| 769 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 770 | { .div = 0 }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 771 | }; |
| 772 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 773 | static const struct clksel_rate func_96m_alt_rates[] = { |
| 774 | { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, |
| 775 | { .div = 0 }, |
| 776 | }; |
| 777 | |
| 778 | static const struct clksel func_96m_clksel[] = { |
| 779 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, |
| 780 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, |
| 781 | { .parent = NULL } |
| 782 | }; |
| 783 | |
| 784 | /* The parent of this clock is not selectable on 2420. */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 785 | static struct clk func_96m_ck = { |
| 786 | .name = "func_96m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 787 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 788 | .parent = &apll96_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 789 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 790 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 791 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 792 | .init = &omap2_init_clksel_parent, |
| 793 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 794 | .clksel_mask = OMAP2430_96M_SOURCE, |
| 795 | .clksel = func_96m_clksel, |
| 796 | .recalc = &omap2_clksel_recalc, |
| 797 | .round_rate = &omap2_clksel_round_rate, |
| 798 | .set_rate = &omap2_clksel_set_rate |
| 799 | }; |
| 800 | |
| 801 | /* func_48m_ck */ |
| 802 | |
| 803 | static const struct clksel_rate func_48m_apll96_rates[] = { |
| 804 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 805 | { .div = 0 }, |
| 806 | }; |
| 807 | |
| 808 | static const struct clksel_rate func_48m_alt_rates[] = { |
| 809 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 810 | { .div = 0 }, |
| 811 | }; |
| 812 | |
| 813 | static const struct clksel func_48m_clksel[] = { |
| 814 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, |
| 815 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, |
| 816 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 817 | }; |
| 818 | |
| 819 | static struct clk func_48m_ck = { |
| 820 | .name = "func_48m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 821 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 822 | .parent = &apll96_ck, /* 96M or Alt */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 823 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 824 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 825 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 826 | .init = &omap2_init_clksel_parent, |
| 827 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 828 | .clksel_mask = OMAP24XX_48M_SOURCE, |
| 829 | .clksel = func_48m_clksel, |
| 830 | .recalc = &omap2_clksel_recalc, |
| 831 | .round_rate = &omap2_clksel_round_rate, |
| 832 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 833 | }; |
| 834 | |
| 835 | static struct clk func_12m_ck = { |
| 836 | .name = "func_12m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 837 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 838 | .parent = &func_48m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 839 | .fixed_div = 4, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 840 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 841 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 842 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 843 | .recalc = &omap2_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 844 | }; |
| 845 | |
| 846 | /* Secure timer, only available in secure mode */ |
| 847 | static struct clk wdt1_osc_ck = { |
| 848 | .name = "ck_wdt1_osc", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 849 | .ops = &clkops_null, /* RMK: missing? */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 850 | .parent = &osc_ck, |
| 851 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 852 | .recalc = &followparent_recalc, |
| 853 | }; |
| 854 | |
| 855 | /* |
| 856 | * The common_clkout* clksel_rate structs are common to |
| 857 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. |
| 858 | * sys_clkout2_* are 2420-only, so the |
| 859 | * clksel_rate flags fields are inaccurate for those clocks. This is |
| 860 | * harmless since access to those clocks are gated by the struct clk |
| 861 | * flags fields, which mark them as 2420-only. |
| 862 | */ |
| 863 | static const struct clksel_rate common_clkout_src_core_rates[] = { |
| 864 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 865 | { .div = 0 } |
| 866 | }; |
| 867 | |
| 868 | static const struct clksel_rate common_clkout_src_sys_rates[] = { |
| 869 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 870 | { .div = 0 } |
| 871 | }; |
| 872 | |
| 873 | static const struct clksel_rate common_clkout_src_96m_rates[] = { |
| 874 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 875 | { .div = 0 } |
| 876 | }; |
| 877 | |
| 878 | static const struct clksel_rate common_clkout_src_54m_rates[] = { |
| 879 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 880 | { .div = 0 } |
| 881 | }; |
| 882 | |
| 883 | static const struct clksel common_clkout_src_clksel[] = { |
| 884 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, |
| 885 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, |
| 886 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, |
| 887 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, |
| 888 | { .parent = NULL } |
| 889 | }; |
| 890 | |
| 891 | static struct clk sys_clkout_src = { |
| 892 | .name = "sys_clkout_src", |
| 893 | .parent = &func_54m_ck, |
| 894 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 895 | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 896 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 897 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 898 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| 899 | .init = &omap2_init_clksel_parent, |
| 900 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 901 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
| 902 | .clksel = common_clkout_src_clksel, |
| 903 | .recalc = &omap2_clksel_recalc, |
| 904 | .round_rate = &omap2_clksel_round_rate, |
| 905 | .set_rate = &omap2_clksel_set_rate |
| 906 | }; |
| 907 | |
| 908 | static const struct clksel_rate common_clkout_rates[] = { |
| 909 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 910 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
| 911 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, |
| 912 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, |
| 913 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, |
| 914 | { .div = 0 }, |
| 915 | }; |
| 916 | |
| 917 | static const struct clksel sys_clkout_clksel[] = { |
| 918 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, |
| 919 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 920 | }; |
| 921 | |
| 922 | static struct clk sys_clkout = { |
| 923 | .name = "sys_clkout", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 924 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 925 | .parent = &sys_clkout_src, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 926 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 927 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 928 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 929 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| 930 | .clksel = sys_clkout_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 931 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 932 | .round_rate = &omap2_clksel_round_rate, |
| 933 | .set_rate = &omap2_clksel_set_rate |
| 934 | }; |
| 935 | |
| 936 | /* In 2430, new in 2420 ES2 */ |
| 937 | static struct clk sys_clkout2_src = { |
| 938 | .name = "sys_clkout2_src", |
| 939 | .parent = &func_54m_ck, |
| 940 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 941 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 942 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 943 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
| 944 | .init = &omap2_init_clksel_parent, |
| 945 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 946 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, |
| 947 | .clksel = common_clkout_src_clksel, |
| 948 | .recalc = &omap2_clksel_recalc, |
| 949 | .round_rate = &omap2_clksel_round_rate, |
| 950 | .set_rate = &omap2_clksel_set_rate |
| 951 | }; |
| 952 | |
| 953 | static const struct clksel sys_clkout2_clksel[] = { |
| 954 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, |
| 955 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 956 | }; |
| 957 | |
| 958 | /* In 2430, new in 2420 ES2 */ |
| 959 | static struct clk sys_clkout2 = { |
| 960 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 961 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 962 | .parent = &sys_clkout2_src, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 963 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 964 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 965 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 966 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
| 967 | .clksel = sys_clkout2_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 968 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 969 | .round_rate = &omap2_clksel_round_rate, |
| 970 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 971 | }; |
| 972 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 973 | static struct clk emul_ck = { |
| 974 | .name = "emul_ck", |
| 975 | .parent = &func_54m_ck, |
| 976 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 977 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 978 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, |
| 979 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| 980 | .recalc = &followparent_recalc, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 981 | |
| 982 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 983 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 984 | /* |
| 985 | * MPU clock domain |
| 986 | * Clocks: |
| 987 | * MPU_FCLK, MPU_ICLK |
| 988 | * INT_M_FCLK, INT_M_I_CLK |
| 989 | * |
| 990 | * - Individual clocks are hardware managed. |
| 991 | * - Base divider comes from: CM_CLKSEL_MPU |
| 992 | * |
| 993 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 994 | static const struct clksel_rate mpu_core_rates[] = { |
| 995 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 996 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 997 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 998 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 999 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1000 | { .div = 0 }, |
| 1001 | }; |
| 1002 | |
| 1003 | static const struct clksel mpu_clksel[] = { |
| 1004 | { .parent = &core_ck, .rates = mpu_core_rates }, |
| 1005 | { .parent = NULL } |
| 1006 | }; |
| 1007 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1008 | static struct clk mpu_ck = { /* Control cpu */ |
| 1009 | .name = "mpu_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1010 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1011 | .parent = &core_ck, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 1012 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1013 | DELAYED_APP | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1014 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1015 | .clkdm_name = "mpu_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 1016 | .init = &omap2_init_clksel_parent, |
| 1017 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| 1018 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1019 | .clksel = mpu_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1020 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1021 | .round_rate = &omap2_clksel_round_rate, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 1022 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1023 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1024 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1025 | /* |
| 1026 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain |
| 1027 | * Clocks: |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1028 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1029 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1030 | * |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1031 | * Won't be too specific here. The core clock comes into this block |
| 1032 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| 1033 | * controls. The other branch gets further divided by 2 then possibly |
| 1034 | * routed into a synchronizer and out of clocks abc. |
| 1035 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1036 | static const struct clksel_rate dsp_fck_core_rates[] = { |
| 1037 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1038 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 1039 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 1040 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 1041 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 1042 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1043 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 1044 | { .div = 0 }, |
| 1045 | }; |
| 1046 | |
| 1047 | static const struct clksel dsp_fck_clksel[] = { |
| 1048 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, |
| 1049 | { .parent = NULL } |
| 1050 | }; |
| 1051 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1052 | static struct clk dsp_fck = { |
| 1053 | .name = "dsp_fck", |
| 1054 | .parent = &core_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1055 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | |
| 1056 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1057 | .clkdm_name = "dsp_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1058 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1059 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 1060 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 1061 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
| 1062 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1063 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1064 | .round_rate = &omap2_clksel_round_rate, |
| 1065 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1066 | }; |
| 1067 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1068 | /* DSP interface clock */ |
| 1069 | static const struct clksel_rate dsp_irate_ick_rates[] = { |
| 1070 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1071 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 1072 | { .div = 3, .val = 3, .flags = RATE_IN_243X }, |
| 1073 | { .div = 0 }, |
| 1074 | }; |
| 1075 | |
| 1076 | static const struct clksel dsp_irate_ick_clksel[] = { |
| 1077 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, |
| 1078 | { .parent = NULL } |
| 1079 | }; |
| 1080 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1081 | /* This clock does not exist as such in the TRM. */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1082 | static struct clk dsp_irate_ick = { |
| 1083 | .name = "dsp_irate_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1084 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1085 | .parent = &dsp_fck, |
| 1086 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1087 | CONFIG_PARTICIPANT, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1088 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 1089 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 1090 | .clksel = dsp_irate_ick_clksel, |
| 1091 | .recalc = &omap2_clksel_recalc, |
| 1092 | .round_rate = &omap2_clksel_round_rate, |
| 1093 | .set_rate = &omap2_clksel_set_rate |
| 1094 | }; |
| 1095 | |
| 1096 | /* 2420 only */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1097 | static struct clk dsp_ick = { |
| 1098 | .name = "dsp_ick", /* apparently ipi and isp */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1099 | .parent = &dsp_irate_ick, |
| 1100 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, |
| 1101 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
| 1102 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ |
| 1103 | }; |
| 1104 | |
| 1105 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
| 1106 | static struct clk iva2_1_ick = { |
| 1107 | .name = "iva2_1_ick", |
| 1108 | .parent = &dsp_irate_ick, |
| 1109 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, |
| 1110 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1111 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1112 | }; |
| 1113 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1114 | /* |
| 1115 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with |
| 1116 | * the C54x, but which is contained in the DSP powerdomain. Does not |
| 1117 | * exist on later OMAPs. |
| 1118 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1119 | static struct clk iva1_ifck = { |
| 1120 | .name = "iva1_ifck", |
| 1121 | .parent = &core_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1122 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | |
| 1123 | RATE_PROPAGATES | DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1124 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1125 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1126 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
| 1127 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 1128 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, |
| 1129 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1130 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1131 | .round_rate = &omap2_clksel_round_rate, |
| 1132 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1133 | }; |
| 1134 | |
| 1135 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 1136 | static struct clk iva1_mpu_int_ifck = { |
| 1137 | .name = "iva1_mpu_int_ifck", |
| 1138 | .parent = &iva1_ifck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1139 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1140 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1141 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1142 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
| 1143 | .fixed_div = 2, |
| 1144 | .recalc = &omap2_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1145 | }; |
| 1146 | |
| 1147 | /* |
| 1148 | * L3 clock domain |
| 1149 | * L3 clocks are used for both interface and functional clocks to |
| 1150 | * multiple entities. Some of these clocks are completely managed |
| 1151 | * by hardware, and some others allow software control. Hardware |
| 1152 | * managed ones general are based on directly CLK_REQ signals and |
| 1153 | * various auto idle settings. The functional spec sets many of these |
| 1154 | * as 'tie-high' for their enables. |
| 1155 | * |
| 1156 | * I-CLOCKS: |
| 1157 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA |
| 1158 | * CAM, HS-USB. |
| 1159 | * F-CLOCK |
| 1160 | * SSI. |
| 1161 | * |
| 1162 | * GPMC memories and SDRC have timing and clock sensitive registers which |
| 1163 | * may very well need notification when the clock changes. Currently for low |
| 1164 | * operating points, these are taken care of in sleep.S. |
| 1165 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1166 | static const struct clksel_rate core_l3_core_rates[] = { |
| 1167 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 1168 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 1169 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1170 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 1171 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1172 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 1173 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, |
| 1174 | { .div = 0 } |
| 1175 | }; |
| 1176 | |
| 1177 | static const struct clksel core_l3_clksel[] = { |
| 1178 | { .parent = &core_ck, .rates = core_l3_core_rates }, |
| 1179 | { .parent = NULL } |
| 1180 | }; |
| 1181 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1182 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 1183 | .name = "core_l3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1184 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1185 | .parent = &core_ck, |
| 1186 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1187 | DELAYED_APP | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1188 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1189 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1190 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1191 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| 1192 | .clksel = core_l3_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1193 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1194 | .round_rate = &omap2_clksel_round_rate, |
| 1195 | .set_rate = &omap2_clksel_set_rate |
| 1196 | }; |
| 1197 | |
| 1198 | /* usb_l4_ick */ |
| 1199 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { |
| 1200 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 1201 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1202 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 1203 | { .div = 0 } |
| 1204 | }; |
| 1205 | |
| 1206 | static const struct clksel usb_l4_ick_clksel[] = { |
| 1207 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, |
| 1208 | { .parent = NULL }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1209 | }; |
| 1210 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1211 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1212 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 1213 | .name = "usb_l4_ick", |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1214 | .parent = &core_l3_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1215 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1216 | DELAYED_APP | CONFIG_PARTICIPANT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1217 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1218 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1219 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 1220 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1221 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
| 1222 | .clksel = usb_l4_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1223 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1224 | .round_rate = &omap2_clksel_round_rate, |
| 1225 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1226 | }; |
| 1227 | |
| 1228 | /* |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1229 | * L4 clock management domain |
| 1230 | * |
| 1231 | * This domain contains lots of interface clocks from the L4 interface, some |
| 1232 | * functional clocks. Fixed APLL functional source clocks are managed in |
| 1233 | * this domain. |
| 1234 | */ |
| 1235 | static const struct clksel_rate l4_core_l3_rates[] = { |
| 1236 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1237 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 1238 | { .div = 0 } |
| 1239 | }; |
| 1240 | |
| 1241 | static const struct clksel l4_clksel[] = { |
| 1242 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, |
| 1243 | { .parent = NULL } |
| 1244 | }; |
| 1245 | |
| 1246 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 1247 | .name = "l4_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1248 | .ops = &clkops_null, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1249 | .parent = &core_l3_ck, |
| 1250 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1251 | DELAYED_APP | RATE_PROPAGATES, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1252 | .clkdm_name = "core_l4_clkdm", |
| 1253 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1254 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| 1255 | .clksel = l4_clksel, |
| 1256 | .recalc = &omap2_clksel_recalc, |
| 1257 | .round_rate = &omap2_clksel_round_rate, |
| 1258 | .set_rate = &omap2_clksel_set_rate |
| 1259 | }; |
| 1260 | |
| 1261 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1262 | * SSI is in L3 management domain, its direct parent is core not l3, |
| 1263 | * many core power domain entities are grouped into the L3 clock |
| 1264 | * domain. |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1265 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1266 | * |
| 1267 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
| 1268 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1269 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
| 1270 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 1271 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1272 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 1273 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 1274 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, |
| 1275 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 1276 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1277 | { .div = 0 } |
| 1278 | }; |
| 1279 | |
| 1280 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { |
| 1281 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, |
| 1282 | { .parent = NULL } |
| 1283 | }; |
| 1284 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1285 | static struct clk ssi_ssr_sst_fck = { |
| 1286 | .name = "ssi_fck", |
| 1287 | .parent = &core_ck, |
| 1288 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1289 | DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1290 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1291 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1292 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 1293 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1294 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
| 1295 | .clksel = ssi_ssr_sst_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1296 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1297 | .round_rate = &omap2_clksel_round_rate, |
| 1298 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1299 | }; |
| 1300 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1301 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1302 | /* |
| 1303 | * GFX clock domain |
| 1304 | * Clocks: |
| 1305 | * GFX_FCLK, GFX_ICLK |
| 1306 | * GFX_CG1(2d), GFX_CG2(3d) |
| 1307 | * |
| 1308 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) |
| 1309 | * The 2d and 3d clocks run at a hardware determined |
| 1310 | * divided value of fclk. |
| 1311 | * |
| 1312 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1313 | /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ |
| 1314 | |
| 1315 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
| 1316 | static const struct clksel gfx_fck_clksel[] = { |
| 1317 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, |
| 1318 | { .parent = NULL }, |
| 1319 | }; |
| 1320 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1321 | static struct clk gfx_3d_fck = { |
| 1322 | .name = "gfx_3d_fck", |
| 1323 | .parent = &core_l3_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1324 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1325 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1326 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1327 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| 1328 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1329 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1330 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1331 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1332 | .round_rate = &omap2_clksel_round_rate, |
| 1333 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1334 | }; |
| 1335 | |
| 1336 | static struct clk gfx_2d_fck = { |
| 1337 | .name = "gfx_2d_fck", |
| 1338 | .parent = &core_l3_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1339 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1340 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1341 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1342 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| 1343 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1344 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1345 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1346 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1347 | .round_rate = &omap2_clksel_round_rate, |
| 1348 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1349 | }; |
| 1350 | |
| 1351 | static struct clk gfx_ick = { |
| 1352 | .name = "gfx_ick", /* From l3 */ |
| 1353 | .parent = &core_l3_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1354 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1355 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1356 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1357 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 1358 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1359 | }; |
| 1360 | |
| 1361 | /* |
| 1362 | * Modem clock domain (2430) |
| 1363 | * CLOCKS: |
| 1364 | * MDM_OSC_CLK |
| 1365 | * MDM_ICLK |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1366 | * These clocks are usable in chassis mode only. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1367 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1368 | static const struct clksel_rate mdm_ick_core_rates[] = { |
| 1369 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, |
| 1370 | { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, |
| 1371 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, |
| 1372 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, |
| 1373 | { .div = 0 } |
| 1374 | }; |
| 1375 | |
| 1376 | static const struct clksel mdm_ick_clksel[] = { |
| 1377 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, |
| 1378 | { .parent = NULL } |
| 1379 | }; |
| 1380 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1381 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
| 1382 | .name = "mdm_ick", |
| 1383 | .parent = &core_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1384 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1385 | .clkdm_name = "mdm_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1386 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
| 1387 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
| 1388 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), |
| 1389 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, |
| 1390 | .clksel = mdm_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1391 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1392 | .round_rate = &omap2_clksel_round_rate, |
| 1393 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1394 | }; |
| 1395 | |
| 1396 | static struct clk mdm_osc_ck = { |
| 1397 | .name = "mdm_osc_ck", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1398 | .parent = &osc_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1399 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1400 | .clkdm_name = "mdm_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1401 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
| 1402 | .enable_bit = OMAP2430_EN_OSC_SHIFT, |
| 1403 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1404 | }; |
| 1405 | |
| 1406 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1407 | * DSS clock domain |
| 1408 | * CLOCKs: |
| 1409 | * DSS_L4_ICLK, DSS_L3_ICLK, |
| 1410 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK |
| 1411 | * |
| 1412 | * DSS is both initiator and target. |
| 1413 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1414 | /* XXX Add RATE_NOT_VALIDATED */ |
| 1415 | |
| 1416 | static const struct clksel_rate dss1_fck_sys_rates[] = { |
| 1417 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1418 | { .div = 0 } |
| 1419 | }; |
| 1420 | |
| 1421 | static const struct clksel_rate dss1_fck_core_rates[] = { |
| 1422 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 1423 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 1424 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 1425 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 1426 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, |
| 1427 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 1428 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, |
| 1429 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, |
| 1430 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, |
| 1431 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1432 | { .div = 0 } |
| 1433 | }; |
| 1434 | |
| 1435 | static const struct clksel dss1_fck_clksel[] = { |
| 1436 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, |
| 1437 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, |
| 1438 | { .parent = NULL }, |
| 1439 | }; |
| 1440 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1441 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 1442 | .name = "dss_ick", |
| 1443 | .parent = &l4_ck, /* really both l3 and l4 */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1444 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1445 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1447 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1448 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1449 | }; |
| 1450 | |
| 1451 | static struct clk dss1_fck = { |
| 1452 | .name = "dss1_fck", |
| 1453 | .parent = &core_ck, /* Core or sys */ |
| 1454 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1455 | DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1456 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1457 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1458 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1459 | .init = &omap2_init_clksel_parent, |
| 1460 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1461 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
| 1462 | .clksel = dss1_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1463 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1464 | .round_rate = &omap2_clksel_round_rate, |
| 1465 | .set_rate = &omap2_clksel_set_rate |
| 1466 | }; |
| 1467 | |
| 1468 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
| 1469 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1470 | { .div = 0 } |
| 1471 | }; |
| 1472 | |
| 1473 | static const struct clksel_rate dss2_fck_48m_rates[] = { |
| 1474 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1475 | { .div = 0 } |
| 1476 | }; |
| 1477 | |
| 1478 | static const struct clksel dss2_fck_clksel[] = { |
| 1479 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, |
| 1480 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, |
| 1481 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1482 | }; |
| 1483 | |
| 1484 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 1485 | .name = "dss2_fck", |
| 1486 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
| 1487 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Richard Woodruff | 474844f | 2007-01-26 12:08:51 -0800 | [diff] [blame] | 1488 | DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1489 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1491 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| 1492 | .init = &omap2_init_clksel_parent, |
| 1493 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1494 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 1495 | .clksel = dss2_fck_clksel, |
| 1496 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1497 | }; |
| 1498 | |
| 1499 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 1500 | .name = "dss_54m_fck", /* 54m tv clk */ |
| 1501 | .parent = &func_54m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1502 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1503 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1504 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1505 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| 1506 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1507 | }; |
| 1508 | |
| 1509 | /* |
| 1510 | * CORE power domain ICLK & FCLK defines. |
| 1511 | * Many of the these can have more than one possible parent. Entries |
| 1512 | * here will likely have an L4 interface parent, and may have multiple |
| 1513 | * functional clock parents. |
| 1514 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1515 | static const struct clksel_rate gpt_alt_rates[] = { |
| 1516 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 1517 | { .div = 0 } |
| 1518 | }; |
| 1519 | |
| 1520 | static const struct clksel omap24xx_gpt_clksel[] = { |
| 1521 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, |
| 1522 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 1523 | { .parent = &alt_ck, .rates = gpt_alt_rates }, |
| 1524 | { .parent = NULL }, |
| 1525 | }; |
| 1526 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1527 | static struct clk gpt1_ick = { |
| 1528 | .name = "gpt1_ick", |
| 1529 | .parent = &l4_ck, |
| 1530 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1531 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1532 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1533 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 1534 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1535 | }; |
| 1536 | |
| 1537 | static struct clk gpt1_fck = { |
| 1538 | .name = "gpt1_fck", |
| 1539 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1540 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1541 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1542 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1543 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 1544 | .init = &omap2_init_clksel_parent, |
| 1545 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), |
| 1546 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, |
| 1547 | .clksel = omap24xx_gpt_clksel, |
| 1548 | .recalc = &omap2_clksel_recalc, |
| 1549 | .round_rate = &omap2_clksel_round_rate, |
| 1550 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1551 | }; |
| 1552 | |
| 1553 | static struct clk gpt2_ick = { |
| 1554 | .name = "gpt2_ick", |
| 1555 | .parent = &l4_ck, |
| 1556 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1557 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1558 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1559 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 1560 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1561 | }; |
| 1562 | |
| 1563 | static struct clk gpt2_fck = { |
| 1564 | .name = "gpt2_fck", |
| 1565 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1566 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1567 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1568 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1569 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 1570 | .init = &omap2_init_clksel_parent, |
| 1571 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1572 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, |
| 1573 | .clksel = omap24xx_gpt_clksel, |
| 1574 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1575 | }; |
| 1576 | |
| 1577 | static struct clk gpt3_ick = { |
| 1578 | .name = "gpt3_ick", |
| 1579 | .parent = &l4_ck, |
| 1580 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1581 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1582 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1583 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 1584 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1585 | }; |
| 1586 | |
| 1587 | static struct clk gpt3_fck = { |
| 1588 | .name = "gpt3_fck", |
| 1589 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1590 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1591 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1592 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1593 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 1594 | .init = &omap2_init_clksel_parent, |
| 1595 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1596 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, |
| 1597 | .clksel = omap24xx_gpt_clksel, |
| 1598 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1599 | }; |
| 1600 | |
| 1601 | static struct clk gpt4_ick = { |
| 1602 | .name = "gpt4_ick", |
| 1603 | .parent = &l4_ck, |
| 1604 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1605 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1606 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1607 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 1608 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1609 | }; |
| 1610 | |
| 1611 | static struct clk gpt4_fck = { |
| 1612 | .name = "gpt4_fck", |
| 1613 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1614 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1615 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1616 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1617 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 1618 | .init = &omap2_init_clksel_parent, |
| 1619 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1620 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, |
| 1621 | .clksel = omap24xx_gpt_clksel, |
| 1622 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1623 | }; |
| 1624 | |
| 1625 | static struct clk gpt5_ick = { |
| 1626 | .name = "gpt5_ick", |
| 1627 | .parent = &l4_ck, |
| 1628 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1629 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1630 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1631 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 1632 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1633 | }; |
| 1634 | |
| 1635 | static struct clk gpt5_fck = { |
| 1636 | .name = "gpt5_fck", |
| 1637 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1638 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1639 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1640 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1641 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 1642 | .init = &omap2_init_clksel_parent, |
| 1643 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1644 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, |
| 1645 | .clksel = omap24xx_gpt_clksel, |
| 1646 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1647 | }; |
| 1648 | |
| 1649 | static struct clk gpt6_ick = { |
| 1650 | .name = "gpt6_ick", |
| 1651 | .parent = &l4_ck, |
| 1652 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1653 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1655 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 1656 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1657 | }; |
| 1658 | |
| 1659 | static struct clk gpt6_fck = { |
| 1660 | .name = "gpt6_fck", |
| 1661 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1662 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1663 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1665 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 1666 | .init = &omap2_init_clksel_parent, |
| 1667 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1668 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, |
| 1669 | .clksel = omap24xx_gpt_clksel, |
| 1670 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1671 | }; |
| 1672 | |
| 1673 | static struct clk gpt7_ick = { |
| 1674 | .name = "gpt7_ick", |
| 1675 | .parent = &l4_ck, |
| 1676 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1677 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1678 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1679 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1680 | }; |
| 1681 | |
| 1682 | static struct clk gpt7_fck = { |
| 1683 | .name = "gpt7_fck", |
| 1684 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1685 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1686 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1687 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1688 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1689 | .init = &omap2_init_clksel_parent, |
| 1690 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1691 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, |
| 1692 | .clksel = omap24xx_gpt_clksel, |
| 1693 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1694 | }; |
| 1695 | |
| 1696 | static struct clk gpt8_ick = { |
| 1697 | .name = "gpt8_ick", |
| 1698 | .parent = &l4_ck, |
| 1699 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1700 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1701 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1702 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1703 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1704 | }; |
| 1705 | |
| 1706 | static struct clk gpt8_fck = { |
| 1707 | .name = "gpt8_fck", |
| 1708 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1709 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1710 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1711 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1712 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1713 | .init = &omap2_init_clksel_parent, |
| 1714 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1715 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, |
| 1716 | .clksel = omap24xx_gpt_clksel, |
| 1717 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1718 | }; |
| 1719 | |
| 1720 | static struct clk gpt9_ick = { |
| 1721 | .name = "gpt9_ick", |
| 1722 | .parent = &l4_ck, |
| 1723 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1724 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1725 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1726 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1727 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1728 | }; |
| 1729 | |
| 1730 | static struct clk gpt9_fck = { |
| 1731 | .name = "gpt9_fck", |
| 1732 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1733 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1734 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1735 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1736 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1737 | .init = &omap2_init_clksel_parent, |
| 1738 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1739 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, |
| 1740 | .clksel = omap24xx_gpt_clksel, |
| 1741 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1742 | }; |
| 1743 | |
| 1744 | static struct clk gpt10_ick = { |
| 1745 | .name = "gpt10_ick", |
| 1746 | .parent = &l4_ck, |
| 1747 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1748 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1749 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1750 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1751 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1752 | }; |
| 1753 | |
| 1754 | static struct clk gpt10_fck = { |
| 1755 | .name = "gpt10_fck", |
| 1756 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1757 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1758 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1759 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1760 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1761 | .init = &omap2_init_clksel_parent, |
| 1762 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1763 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, |
| 1764 | .clksel = omap24xx_gpt_clksel, |
| 1765 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1766 | }; |
| 1767 | |
| 1768 | static struct clk gpt11_ick = { |
| 1769 | .name = "gpt11_ick", |
| 1770 | .parent = &l4_ck, |
| 1771 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1772 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1773 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1774 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1775 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1776 | }; |
| 1777 | |
| 1778 | static struct clk gpt11_fck = { |
| 1779 | .name = "gpt11_fck", |
| 1780 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1781 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1782 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1784 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1785 | .init = &omap2_init_clksel_parent, |
| 1786 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1787 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, |
| 1788 | .clksel = omap24xx_gpt_clksel, |
| 1789 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1790 | }; |
| 1791 | |
| 1792 | static struct clk gpt12_ick = { |
| 1793 | .name = "gpt12_ick", |
| 1794 | .parent = &l4_ck, |
| 1795 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1796 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1797 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1798 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1799 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1800 | }; |
| 1801 | |
| 1802 | static struct clk gpt12_fck = { |
| 1803 | .name = "gpt12_fck", |
| 1804 | .parent = &func_32k_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1805 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1806 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1807 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1808 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1809 | .init = &omap2_init_clksel_parent, |
| 1810 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1811 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, |
| 1812 | .clksel = omap24xx_gpt_clksel, |
| 1813 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1814 | }; |
| 1815 | |
| 1816 | static struct clk mcbsp1_ick = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1817 | .name = "mcbsp_ick", |
| 1818 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1819 | .parent = &l4_ck, |
| 1820 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1821 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1822 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1823 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1824 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1825 | }; |
| 1826 | |
| 1827 | static struct clk mcbsp1_fck = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1828 | .name = "mcbsp_fck", |
| 1829 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1830 | .parent = &func_96m_ck, |
| 1831 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1832 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1833 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1834 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1835 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1836 | }; |
| 1837 | |
| 1838 | static struct clk mcbsp2_ick = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1839 | .name = "mcbsp_ick", |
| 1840 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1841 | .parent = &l4_ck, |
| 1842 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1843 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1844 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1845 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1846 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1847 | }; |
| 1848 | |
| 1849 | static struct clk mcbsp2_fck = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1850 | .name = "mcbsp_fck", |
| 1851 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1852 | .parent = &func_96m_ck, |
| 1853 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1854 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1855 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1856 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1857 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1858 | }; |
| 1859 | |
| 1860 | static struct clk mcbsp3_ick = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1861 | .name = "mcbsp_ick", |
| 1862 | .id = 3, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1863 | .parent = &l4_ck, |
| 1864 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1865 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1866 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1867 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| 1868 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1869 | }; |
| 1870 | |
| 1871 | static struct clk mcbsp3_fck = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1872 | .name = "mcbsp_fck", |
| 1873 | .id = 3, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1874 | .parent = &func_96m_ck, |
| 1875 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1876 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1877 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1878 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| 1879 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1880 | }; |
| 1881 | |
| 1882 | static struct clk mcbsp4_ick = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1883 | .name = "mcbsp_ick", |
| 1884 | .id = 4, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1885 | .parent = &l4_ck, |
| 1886 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1887 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1888 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1889 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| 1890 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1891 | }; |
| 1892 | |
| 1893 | static struct clk mcbsp4_fck = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1894 | .name = "mcbsp_fck", |
| 1895 | .id = 4, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1896 | .parent = &func_96m_ck, |
| 1897 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1898 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1899 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1900 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| 1901 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1902 | }; |
| 1903 | |
| 1904 | static struct clk mcbsp5_ick = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1905 | .name = "mcbsp_ick", |
| 1906 | .id = 5, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1907 | .parent = &l4_ck, |
| 1908 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1909 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1910 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1911 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| 1912 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1913 | }; |
| 1914 | |
| 1915 | static struct clk mcbsp5_fck = { |
Eduardo Valentin | 44ec9a3 | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1916 | .name = "mcbsp_fck", |
| 1917 | .id = 5, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1918 | .parent = &func_96m_ck, |
| 1919 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1920 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1921 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1922 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| 1923 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1924 | }; |
| 1925 | |
| 1926 | static struct clk mcspi1_ick = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1927 | .name = "mcspi_ick", |
| 1928 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1929 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1930 | .clkdm_name = "core_l4_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1931 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1933 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1934 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1935 | }; |
| 1936 | |
| 1937 | static struct clk mcspi1_fck = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1938 | .name = "mcspi_fck", |
| 1939 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1940 | .parent = &func_48m_ck, |
| 1941 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1942 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1943 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1944 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1945 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1946 | }; |
| 1947 | |
| 1948 | static struct clk mcspi2_ick = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1949 | .name = "mcspi_ick", |
| 1950 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1951 | .parent = &l4_ck, |
| 1952 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1953 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1954 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1955 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1956 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1957 | }; |
| 1958 | |
| 1959 | static struct clk mcspi2_fck = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1960 | .name = "mcspi_fck", |
| 1961 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1962 | .parent = &func_48m_ck, |
| 1963 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1964 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1965 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1966 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1967 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1968 | }; |
| 1969 | |
| 1970 | static struct clk mcspi3_ick = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1971 | .name = "mcspi_ick", |
| 1972 | .id = 3, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1973 | .parent = &l4_ck, |
| 1974 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1975 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1977 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| 1978 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1979 | }; |
| 1980 | |
| 1981 | static struct clk mcspi3_fck = { |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 1982 | .name = "mcspi_fck", |
| 1983 | .id = 3, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1984 | .parent = &func_48m_ck, |
| 1985 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1986 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1988 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| 1989 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1990 | }; |
| 1991 | |
| 1992 | static struct clk uart1_ick = { |
| 1993 | .name = "uart1_ick", |
| 1994 | .parent = &l4_ck, |
| 1995 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1996 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1998 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1999 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2000 | }; |
| 2001 | |
| 2002 | static struct clk uart1_fck = { |
| 2003 | .name = "uart1_fck", |
| 2004 | .parent = &func_48m_ck, |
| 2005 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2006 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2007 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2008 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 2009 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2010 | }; |
| 2011 | |
| 2012 | static struct clk uart2_ick = { |
| 2013 | .name = "uart2_ick", |
| 2014 | .parent = &l4_ck, |
| 2015 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2016 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2017 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2018 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 2019 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2020 | }; |
| 2021 | |
| 2022 | static struct clk uart2_fck = { |
| 2023 | .name = "uart2_fck", |
| 2024 | .parent = &func_48m_ck, |
| 2025 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2026 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2027 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2028 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 2029 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2030 | }; |
| 2031 | |
| 2032 | static struct clk uart3_ick = { |
| 2033 | .name = "uart3_ick", |
| 2034 | .parent = &l4_ck, |
| 2035 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2036 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2038 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 2039 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2040 | }; |
| 2041 | |
| 2042 | static struct clk uart3_fck = { |
| 2043 | .name = "uart3_fck", |
| 2044 | .parent = &func_48m_ck, |
| 2045 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2046 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2048 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 2049 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2050 | }; |
| 2051 | |
| 2052 | static struct clk gpios_ick = { |
| 2053 | .name = "gpios_ick", |
| 2054 | .parent = &l4_ck, |
| 2055 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2056 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2057 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2058 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 2059 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2060 | }; |
| 2061 | |
| 2062 | static struct clk gpios_fck = { |
| 2063 | .name = "gpios_fck", |
| 2064 | .parent = &func_32k_ck, |
| 2065 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2066 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2067 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2068 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 2069 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2070 | }; |
| 2071 | |
| 2072 | static struct clk mpu_wdt_ick = { |
| 2073 | .name = "mpu_wdt_ick", |
| 2074 | .parent = &l4_ck, |
| 2075 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2076 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2077 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2078 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 2079 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2080 | }; |
| 2081 | |
| 2082 | static struct clk mpu_wdt_fck = { |
| 2083 | .name = "mpu_wdt_fck", |
| 2084 | .parent = &func_32k_ck, |
| 2085 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2086 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2087 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2088 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 2089 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2090 | }; |
| 2091 | |
| 2092 | static struct clk sync_32k_ick = { |
| 2093 | .name = "sync_32k_ick", |
| 2094 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2095 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 2096 | ENABLE_ON_INIT, |
| 2097 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2098 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2099 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| 2100 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2101 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2102 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2103 | static struct clk wdt1_ick = { |
| 2104 | .name = "wdt1_ick", |
| 2105 | .parent = &l4_ck, |
| 2106 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2107 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2108 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2109 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| 2110 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2111 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2112 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2113 | static struct clk omapctrl_ick = { |
| 2114 | .name = "omapctrl_ick", |
| 2115 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2116 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 2117 | ENABLE_ON_INIT, |
| 2118 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2119 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2120 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| 2121 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2122 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2123 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2124 | static struct clk icr_ick = { |
| 2125 | .name = "icr_ick", |
| 2126 | .parent = &l4_ck, |
| 2127 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2128 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2129 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2130 | .enable_bit = OMAP2430_EN_ICR_SHIFT, |
| 2131 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2132 | }; |
| 2133 | |
| 2134 | static struct clk cam_ick = { |
| 2135 | .name = "cam_ick", |
| 2136 | .parent = &l4_ck, |
| 2137 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2138 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2139 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2140 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 2141 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2142 | }; |
| 2143 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2144 | /* |
| 2145 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be |
| 2146 | * split into two separate clocks, since the parent clocks are different |
| 2147 | * and the clockdomains are also different. |
| 2148 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2149 | static struct clk cam_fck = { |
| 2150 | .name = "cam_fck", |
| 2151 | .parent = &func_96m_ck, |
| 2152 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2153 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2154 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2155 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 2156 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2157 | }; |
| 2158 | |
| 2159 | static struct clk mailboxes_ick = { |
| 2160 | .name = "mailboxes_ick", |
| 2161 | .parent = &l4_ck, |
| 2162 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2163 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2164 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2165 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 2166 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2167 | }; |
| 2168 | |
| 2169 | static struct clk wdt4_ick = { |
| 2170 | .name = "wdt4_ick", |
| 2171 | .parent = &l4_ck, |
| 2172 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2173 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2174 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2175 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 2176 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2177 | }; |
| 2178 | |
| 2179 | static struct clk wdt4_fck = { |
| 2180 | .name = "wdt4_fck", |
| 2181 | .parent = &func_32k_ck, |
| 2182 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2183 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2184 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2185 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 2186 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2187 | }; |
| 2188 | |
| 2189 | static struct clk wdt3_ick = { |
| 2190 | .name = "wdt3_ick", |
| 2191 | .parent = &l4_ck, |
| 2192 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2193 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2194 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2195 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 2196 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2197 | }; |
| 2198 | |
| 2199 | static struct clk wdt3_fck = { |
| 2200 | .name = "wdt3_fck", |
| 2201 | .parent = &func_32k_ck, |
| 2202 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2203 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2204 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2205 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 2206 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2207 | }; |
| 2208 | |
| 2209 | static struct clk mspro_ick = { |
| 2210 | .name = "mspro_ick", |
| 2211 | .parent = &l4_ck, |
| 2212 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2213 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2214 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2215 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 2216 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2217 | }; |
| 2218 | |
| 2219 | static struct clk mspro_fck = { |
| 2220 | .name = "mspro_fck", |
| 2221 | .parent = &func_96m_ck, |
| 2222 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2223 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2224 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2225 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 2226 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2227 | }; |
| 2228 | |
| 2229 | static struct clk mmc_ick = { |
| 2230 | .name = "mmc_ick", |
| 2231 | .parent = &l4_ck, |
| 2232 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2233 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2234 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2235 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 2236 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2237 | }; |
| 2238 | |
| 2239 | static struct clk mmc_fck = { |
| 2240 | .name = "mmc_fck", |
| 2241 | .parent = &func_96m_ck, |
| 2242 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2243 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2244 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2245 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 2246 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2247 | }; |
| 2248 | |
| 2249 | static struct clk fac_ick = { |
| 2250 | .name = "fac_ick", |
| 2251 | .parent = &l4_ck, |
| 2252 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2253 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2254 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2255 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 2256 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2257 | }; |
| 2258 | |
| 2259 | static struct clk fac_fck = { |
| 2260 | .name = "fac_fck", |
| 2261 | .parent = &func_12m_ck, |
| 2262 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2263 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2265 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 2266 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2267 | }; |
| 2268 | |
| 2269 | static struct clk eac_ick = { |
| 2270 | .name = "eac_ick", |
| 2271 | .parent = &l4_ck, |
| 2272 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2273 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2274 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2275 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 2276 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2277 | }; |
| 2278 | |
| 2279 | static struct clk eac_fck = { |
| 2280 | .name = "eac_fck", |
| 2281 | .parent = &func_96m_ck, |
| 2282 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2283 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2284 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2285 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 2286 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2287 | }; |
| 2288 | |
| 2289 | static struct clk hdq_ick = { |
| 2290 | .name = "hdq_ick", |
| 2291 | .parent = &l4_ck, |
| 2292 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2293 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2295 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 2296 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2297 | }; |
| 2298 | |
| 2299 | static struct clk hdq_fck = { |
| 2300 | .name = "hdq_fck", |
| 2301 | .parent = &func_12m_ck, |
| 2302 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2303 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2304 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2305 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 2306 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2307 | }; |
| 2308 | |
| 2309 | static struct clk i2c2_ick = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 2310 | .name = "i2c_ick", |
| 2311 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2312 | .parent = &l4_ck, |
| 2313 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2314 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2315 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2316 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 2317 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2318 | }; |
| 2319 | |
| 2320 | static struct clk i2c2_fck = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 2321 | .name = "i2c_fck", |
| 2322 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2323 | .parent = &func_12m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2324 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2325 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2326 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2327 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 2328 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2329 | }; |
| 2330 | |
| 2331 | static struct clk i2chs2_fck = { |
Syed Mohammed Khasim | 4574eb6 | 2008-11-21 13:39:45 -0800 | [diff] [blame] | 2332 | .name = "i2c_fck", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2333 | .id = 2, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2334 | .parent = &func_96m_ck, |
| 2335 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2336 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2337 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2338 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, |
| 2339 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2340 | }; |
| 2341 | |
| 2342 | static struct clk i2c1_ick = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 2343 | .name = "i2c_ick", |
| 2344 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2345 | .parent = &l4_ck, |
| 2346 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2347 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2348 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2349 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 2350 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2351 | }; |
| 2352 | |
| 2353 | static struct clk i2c1_fck = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 2354 | .name = "i2c_fck", |
| 2355 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2356 | .parent = &func_12m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2357 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2358 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2359 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2360 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 2361 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2362 | }; |
| 2363 | |
| 2364 | static struct clk i2chs1_fck = { |
Syed Mohammed Khasim | 4574eb6 | 2008-11-21 13:39:45 -0800 | [diff] [blame] | 2365 | .name = "i2c_fck", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2366 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2367 | .parent = &func_96m_ck, |
| 2368 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2369 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2371 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, |
| 2372 | .recalc = &followparent_recalc, |
| 2373 | }; |
| 2374 | |
| 2375 | static struct clk gpmc_fck = { |
| 2376 | .name = "gpmc_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2377 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2378 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2379 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 2380 | ENABLE_ON_INIT, |
| 2381 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2382 | .recalc = &followparent_recalc, |
| 2383 | }; |
| 2384 | |
| 2385 | static struct clk sdma_fck = { |
| 2386 | .name = "sdma_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2387 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2388 | .parent = &core_l3_ck, |
| 2389 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2390 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2391 | .recalc = &followparent_recalc, |
| 2392 | }; |
| 2393 | |
| 2394 | static struct clk sdma_ick = { |
| 2395 | .name = "sdma_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2396 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2397 | .parent = &l4_ck, |
| 2398 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2399 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2400 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2401 | }; |
| 2402 | |
| 2403 | static struct clk vlynq_ick = { |
| 2404 | .name = "vlynq_ick", |
| 2405 | .parent = &core_l3_ck, |
| 2406 | .flags = CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2407 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2408 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2409 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 2410 | .recalc = &followparent_recalc, |
| 2411 | }; |
| 2412 | |
| 2413 | static const struct clksel_rate vlynq_fck_96m_rates[] = { |
| 2414 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 2415 | { .div = 0 } |
| 2416 | }; |
| 2417 | |
| 2418 | static const struct clksel_rate vlynq_fck_core_rates[] = { |
| 2419 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, |
| 2420 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 2421 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, |
| 2422 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 2423 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 2424 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 2425 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, |
| 2426 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 2427 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 2428 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, |
| 2429 | { .div = 0 } |
| 2430 | }; |
| 2431 | |
| 2432 | static const struct clksel vlynq_fck_clksel[] = { |
| 2433 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, |
| 2434 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, |
| 2435 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2436 | }; |
| 2437 | |
| 2438 | static struct clk vlynq_fck = { |
| 2439 | .name = "vlynq_fck", |
| 2440 | .parent = &func_96m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2441 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2442 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2443 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2444 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 2445 | .init = &omap2_init_clksel_parent, |
| 2446 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 2447 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, |
| 2448 | .clksel = vlynq_fck_clksel, |
| 2449 | .recalc = &omap2_clksel_recalc, |
| 2450 | .round_rate = &omap2_clksel_round_rate, |
| 2451 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2452 | }; |
| 2453 | |
| 2454 | static struct clk sdrc_ick = { |
| 2455 | .name = "sdrc_ick", |
| 2456 | .parent = &l4_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2457 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2458 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2459 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 2460 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, |
| 2461 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2462 | }; |
| 2463 | |
| 2464 | static struct clk des_ick = { |
| 2465 | .name = "des_ick", |
| 2466 | .parent = &l4_ck, |
| 2467 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2468 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2469 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2470 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| 2471 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2472 | }; |
| 2473 | |
| 2474 | static struct clk sha_ick = { |
| 2475 | .name = "sha_ick", |
| 2476 | .parent = &l4_ck, |
| 2477 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2478 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2479 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2480 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| 2481 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2482 | }; |
| 2483 | |
| 2484 | static struct clk rng_ick = { |
| 2485 | .name = "rng_ick", |
| 2486 | .parent = &l4_ck, |
| 2487 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2488 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2489 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2490 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| 2491 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2492 | }; |
| 2493 | |
| 2494 | static struct clk aes_ick = { |
| 2495 | .name = "aes_ick", |
| 2496 | .parent = &l4_ck, |
| 2497 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2498 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2499 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2500 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| 2501 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2502 | }; |
| 2503 | |
| 2504 | static struct clk pka_ick = { |
| 2505 | .name = "pka_ick", |
| 2506 | .parent = &l4_ck, |
| 2507 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2508 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2509 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2510 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| 2511 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2512 | }; |
| 2513 | |
| 2514 | static struct clk usb_fck = { |
| 2515 | .name = "usb_fck", |
| 2516 | .parent = &func_48m_ck, |
| 2517 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2518 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2519 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2520 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 2521 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2522 | }; |
| 2523 | |
| 2524 | static struct clk usbhs_ick = { |
| 2525 | .name = "usbhs_ick", |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 2526 | .parent = &core_l3_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2527 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2528 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2529 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2530 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, |
| 2531 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2532 | }; |
| 2533 | |
| 2534 | static struct clk mmchs1_ick = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2535 | .name = "mmchs_ick", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2536 | .parent = &l4_ck, |
| 2537 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2538 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2539 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2540 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| 2541 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2542 | }; |
| 2543 | |
| 2544 | static struct clk mmchs1_fck = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2545 | .name = "mmchs_fck", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2546 | .parent = &func_96m_ck, |
| 2547 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2548 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2550 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| 2551 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2552 | }; |
| 2553 | |
| 2554 | static struct clk mmchs2_ick = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2555 | .name = "mmchs_ick", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 2556 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2557 | .parent = &l4_ck, |
| 2558 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2559 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2561 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 2562 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2563 | }; |
| 2564 | |
| 2565 | static struct clk mmchs2_fck = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2566 | .name = "mmchs_fck", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 2567 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2568 | .parent = &func_96m_ck, |
| 2569 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2571 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 2572 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2573 | }; |
| 2574 | |
| 2575 | static struct clk gpio5_ick = { |
| 2576 | .name = "gpio5_ick", |
| 2577 | .parent = &l4_ck, |
| 2578 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2579 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2581 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| 2582 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2583 | }; |
| 2584 | |
| 2585 | static struct clk gpio5_fck = { |
| 2586 | .name = "gpio5_fck", |
| 2587 | .parent = &func_32k_ck, |
| 2588 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2589 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2591 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| 2592 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2593 | }; |
| 2594 | |
| 2595 | static struct clk mdm_intc_ick = { |
| 2596 | .name = "mdm_intc_ick", |
| 2597 | .parent = &l4_ck, |
| 2598 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2599 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2600 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2601 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, |
| 2602 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2603 | }; |
| 2604 | |
| 2605 | static struct clk mmchsdb1_fck = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2606 | .name = "mmchsdb_fck", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2607 | .parent = &func_32k_ck, |
| 2608 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2609 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2611 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, |
| 2612 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2613 | }; |
| 2614 | |
| 2615 | static struct clk mmchsdb2_fck = { |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2616 | .name = "mmchsdb_fck", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 2617 | .id = 1, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2618 | .parent = &func_32k_ck, |
| 2619 | .flags = CLOCK_IN_OMAP243X, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 2620 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2621 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2622 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, |
| 2623 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2624 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2625 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2626 | /* |
| 2627 | * This clock is a composite clock which does entire set changes then |
| 2628 | * forces a rebalance. It keys on the MPU speed, but it really could |
| 2629 | * be any key speed part of a set in the rate table. |
| 2630 | * |
| 2631 | * to really change a set, you need memory table sets which get changed |
| 2632 | * in sram, pre-notifiers & post notifiers, changing the top set, without |
| 2633 | * having low level display recalc's won't work... this is why dpm notifiers |
| 2634 | * work, isr's off, walk a list of clocks already _off_ and not messing with |
| 2635 | * the bus. |
| 2636 | * |
| 2637 | * This clock should have no parent. It embodies the entire upper level |
| 2638 | * active set. A parent will mess up some of the init also. |
| 2639 | */ |
| 2640 | static struct clk virt_prcm_set = { |
| 2641 | .name = "virt_prcm_set", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2642 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2643 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2644 | DELAYED_APP, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2645 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2646 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2647 | .set_rate = &omap2_select_table_rate, |
| 2648 | .round_rate = &omap2_round_to_table_rate, |
| 2649 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2650 | |
| 2651 | static struct clk *onchip_24xx_clks[] __initdata = { |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2652 | /* external root sources */ |
| 2653 | &func_32k_ck, |
| 2654 | &osc_ck, |
| 2655 | &sys_ck, |
| 2656 | &alt_ck, |
| 2657 | /* internal analog sources */ |
| 2658 | &dpll_ck, |
| 2659 | &apll96_ck, |
| 2660 | &apll54_ck, |
| 2661 | /* internal prcm root sources */ |
| 2662 | &func_54m_ck, |
| 2663 | &core_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2664 | &func_96m_ck, |
| 2665 | &func_48m_ck, |
| 2666 | &func_12m_ck, |
| 2667 | &wdt1_osc_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2668 | &sys_clkout_src, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2669 | &sys_clkout, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2670 | &sys_clkout2_src, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2671 | &sys_clkout2, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 2672 | &emul_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2673 | /* mpu domain clocks */ |
| 2674 | &mpu_ck, |
| 2675 | /* dsp domain clocks */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2676 | &dsp_fck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2677 | &dsp_irate_ick, |
| 2678 | &dsp_ick, /* 242x */ |
| 2679 | &iva2_1_ick, /* 243x */ |
| 2680 | &iva1_ifck, /* 242x */ |
| 2681 | &iva1_mpu_int_ifck, /* 242x */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2682 | /* GFX domain clocks */ |
| 2683 | &gfx_3d_fck, |
| 2684 | &gfx_2d_fck, |
| 2685 | &gfx_ick, |
| 2686 | /* Modem domain clocks */ |
| 2687 | &mdm_ick, |
| 2688 | &mdm_osc_ck, |
| 2689 | /* DSS domain clocks */ |
| 2690 | &dss_ick, |
| 2691 | &dss1_fck, |
| 2692 | &dss2_fck, |
| 2693 | &dss_54m_fck, |
| 2694 | /* L3 domain clocks */ |
| 2695 | &core_l3_ck, |
| 2696 | &ssi_ssr_sst_fck, |
| 2697 | &usb_l4_ick, |
| 2698 | /* L4 domain clocks */ |
| 2699 | &l4_ck, /* used as both core_l4 and wu_l4 */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2700 | /* virtual meta-group clock */ |
| 2701 | &virt_prcm_set, |
| 2702 | /* general l4 interface ck, multi-parent functional clk */ |
| 2703 | &gpt1_ick, |
| 2704 | &gpt1_fck, |
| 2705 | &gpt2_ick, |
| 2706 | &gpt2_fck, |
| 2707 | &gpt3_ick, |
| 2708 | &gpt3_fck, |
| 2709 | &gpt4_ick, |
| 2710 | &gpt4_fck, |
| 2711 | &gpt5_ick, |
| 2712 | &gpt5_fck, |
| 2713 | &gpt6_ick, |
| 2714 | &gpt6_fck, |
| 2715 | &gpt7_ick, |
| 2716 | &gpt7_fck, |
| 2717 | &gpt8_ick, |
| 2718 | &gpt8_fck, |
| 2719 | &gpt9_ick, |
| 2720 | &gpt9_fck, |
| 2721 | &gpt10_ick, |
| 2722 | &gpt10_fck, |
| 2723 | &gpt11_ick, |
| 2724 | &gpt11_fck, |
| 2725 | &gpt12_ick, |
| 2726 | &gpt12_fck, |
| 2727 | &mcbsp1_ick, |
| 2728 | &mcbsp1_fck, |
| 2729 | &mcbsp2_ick, |
| 2730 | &mcbsp2_fck, |
| 2731 | &mcbsp3_ick, |
| 2732 | &mcbsp3_fck, |
| 2733 | &mcbsp4_ick, |
| 2734 | &mcbsp4_fck, |
| 2735 | &mcbsp5_ick, |
| 2736 | &mcbsp5_fck, |
| 2737 | &mcspi1_ick, |
| 2738 | &mcspi1_fck, |
| 2739 | &mcspi2_ick, |
| 2740 | &mcspi2_fck, |
| 2741 | &mcspi3_ick, |
| 2742 | &mcspi3_fck, |
| 2743 | &uart1_ick, |
| 2744 | &uart1_fck, |
| 2745 | &uart2_ick, |
| 2746 | &uart2_fck, |
| 2747 | &uart3_ick, |
| 2748 | &uart3_fck, |
| 2749 | &gpios_ick, |
| 2750 | &gpios_fck, |
| 2751 | &mpu_wdt_ick, |
| 2752 | &mpu_wdt_fck, |
| 2753 | &sync_32k_ick, |
| 2754 | &wdt1_ick, |
| 2755 | &omapctrl_ick, |
| 2756 | &icr_ick, |
| 2757 | &cam_fck, |
| 2758 | &cam_ick, |
| 2759 | &mailboxes_ick, |
| 2760 | &wdt4_ick, |
| 2761 | &wdt4_fck, |
| 2762 | &wdt3_ick, |
| 2763 | &wdt3_fck, |
| 2764 | &mspro_ick, |
| 2765 | &mspro_fck, |
| 2766 | &mmc_ick, |
| 2767 | &mmc_fck, |
| 2768 | &fac_ick, |
| 2769 | &fac_fck, |
| 2770 | &eac_ick, |
| 2771 | &eac_fck, |
| 2772 | &hdq_ick, |
| 2773 | &hdq_fck, |
| 2774 | &i2c1_ick, |
| 2775 | &i2c1_fck, |
| 2776 | &i2chs1_fck, |
| 2777 | &i2c2_ick, |
| 2778 | &i2c2_fck, |
| 2779 | &i2chs2_fck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 2780 | &gpmc_fck, |
| 2781 | &sdma_fck, |
| 2782 | &sdma_ick, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 2783 | &vlynq_ick, |
| 2784 | &vlynq_fck, |
| 2785 | &sdrc_ick, |
| 2786 | &des_ick, |
| 2787 | &sha_ick, |
| 2788 | &rng_ick, |
| 2789 | &aes_ick, |
| 2790 | &pka_ick, |
| 2791 | &usb_fck, |
| 2792 | &usbhs_ick, |
| 2793 | &mmchs1_ick, |
| 2794 | &mmchs1_fck, |
| 2795 | &mmchs2_ick, |
| 2796 | &mmchs2_fck, |
| 2797 | &gpio5_ick, |
| 2798 | &gpio5_fck, |
| 2799 | &mdm_intc_ick, |
| 2800 | &mmchsdb1_fck, |
| 2801 | &mmchsdb2_fck, |
| 2802 | }; |
| 2803 | |
| 2804 | #endif |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 2805 | |