blob: 01c012da4e26d01eef7c9cfeb87b71a26e1f1bd6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
33/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
Russell King975a1a72009-01-02 13:44:27 +000045 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
Russell King05caac52005-07-27 11:41:18 +010047 struct uart_port *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
Russell King70db3d92005-07-27 11:34:27 +010054 struct pci_dev *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
Joe Perchesad361c92009-07-06 13:05:40 -070063 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
Russell King70db3d92005-07-27 11:34:27 +010074setup_port(struct serial_private *priv, struct uart_port *port,
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 int bar, int offset, int regshift)
76{
Russell King70db3d92005-07-27 11:34:27 +010077 struct pci_dev *dev = priv->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
Russell King72ce9a82005-07-27 11:32:04 +010083 base = pci_resource_start(dev, bar);
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
Alan Cox6f441fe2008-05-01 04:34:59 -070089 priv->remapped_bar[bar] = ioremap_nocache(base, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
Russell King72ce9a82005-07-27 11:32:04 +010094 port->iobase = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 port->iotype = UPIO_PORT;
Russell King72ce9a82005-07-27 11:32:04 +0100100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 }
105 return 0;
106}
107
108/*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111static int addidata_apci7800_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000112 const struct pciserial_board *board,
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800113 struct uart_port *port, int idx)
114{
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132}
133
134/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138static int
Russell King975a1a72009-01-02 13:44:27 +0000139afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 struct uart_port *port, int idx)
141{
142 unsigned int bar, offset = board->first_offset;
Alan Cox5756ee92008-02-08 04:18:51 -0800143
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
Russell King70db3d92005-07-27 11:34:27 +0100152 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153}
154
155/*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
Russell King61a116e2006-07-03 15:22:35 +0100162static int pci_hp_diva_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163{
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
Justin Chen551f8f02005-10-24 22:16:38 +0100180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 rc = 1;
182 break;
183 }
184
185 return rc;
186}
187
188/*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192static int
Russell King975a1a72009-01-02 13:44:27 +0000193pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196{
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
Russell King70db3d92005-07-27 11:34:27 +0100200 switch (priv->dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
Russell King70db3d92005-07-27 11:34:27 +0100217 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218}
219
220/*
221 * Added for EKF Intel i960 serial boards
222 */
Russell King61a116e2006-07-03 15:22:35 +0100223static int pci_inteli960ni_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224{
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
Alan Cox5756ee92008-02-08 04:18:51 -0800231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237}
238
239/*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
Russell King61a116e2006-07-03 15:22:35 +0100245static int pci_plx9050_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246{
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
Alan Cox5756ee92008-02-08 04:18:51 -0800257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 irq_config = 0x43;
Alan Cox5756ee92008-02-08 04:18:51 -0800259
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
Alan Cox5756ee92008-02-08 04:18:51 -0800261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 /*
272 * enable/disable interrupts
273 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286}
287
288static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289{
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308}
309
Will Page04bf7e72009-04-06 17:32:15 +0100310#define NI8420_INT_ENABLE_REG 0x38
311#define NI8420_INT_ENABLE_BIT 0x2000
312
313static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314{
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334}
335
336
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100337/* MITE registers */
338#define MITE_IOWBSR1 0xc4
339#define MITE_IOWCR1 0xf4
340#define MITE_LCIMR1 0x08
341#define MITE_LCIMR2 0x10
342
343#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346{
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365}
366
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368static int
Russell King975a1a72009-01-02 13:44:27 +0000369sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 struct uart_port *port, int idx)
371{
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
Russell King70db3d92005-07-27 11:34:27 +0100385 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386}
387
388/*
389* This does initialization for PMC OCTALPRO cards:
390* maps the device memory, resets the UARTs (needed, bc
391* if the module is removed and inserted again, the card
392* is in the sleep mode) and enables global interrupt.
393*/
394
395/* global control register offset for SBS PMC-OctalPro */
396#define OCT_REG_CR_OFF 0x500
397
Russell King61a116e2006-07-03 15:22:35 +0100398static int sbs_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399{
400 u8 __iomem *p;
401
Arjan van de Ven24ed3ab2009-06-24 18:34:58 +0100402 p = pci_ioremap_bar(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
Alan Cox5756ee92008-02-08 04:18:51 -0800407 writeb(0x10, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 udelay(50);
Alan Cox5756ee92008-02-08 04:18:51 -0800409 writeb(0x0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416}
417
418/*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422static void __devexit sbs_exit(struct pci_dev *dev)
423{
424 u8 __iomem *p;
425
Arjan van de Ven24ed3ab2009-06-24 18:34:58 +0100426 p = pci_ioremap_bar(dev, 0);
Alan Cox5756ee92008-02-08 04:18:51 -0800427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 writeb(0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 iounmap(p);
431}
432
433/*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
Alan Cox5756ee92008-02-08 04:18:51 -0800445 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
Russell King67d74b82005-07-27 11:33:03 +0100451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
Andrey Paninfbc0dc02005-07-18 11:38:09 +0100454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
463static int pci_siig10x_init(struct pci_dev *dev)
464{
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
Alan Cox6f441fe2008-05-01 04:34:59 -0700480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488}
489
490#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
493static int pci_siig20x_init(struct pci_dev *dev)
494{
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508}
509
Russell King67d74b82005-07-27 11:33:03 +0100510static int pci_siig_init(struct pci_dev *dev)
511{
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521}
522
Andrey Panin3ec9c592006-02-02 20:15:09 +0000523static int pci_siig_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000524 const struct pciserial_board *board,
Andrey Panin3ec9c592006-02-02 20:15:09 +0000525 struct uart_port *port, int idx)
526{
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535}
536
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537/*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
Helge Dellere9422e02006-08-29 21:57:29 +0200542static const unsigned short timedia_single_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544};
545
Helge Dellere9422e02006-08-29 21:57:29 +0200546static const unsigned short timedia_dual_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
Alan Cox5756ee92008-02-08 04:18:51 -0800548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552};
553
Helge Dellere9422e02006-08-29 21:57:29 +0200554static const unsigned short timedia_quad_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559};
560
Helge Dellere9422e02006-08-29 21:57:29 +0200561static const unsigned short timedia_eight_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564};
565
Arjan van de Vencb3592b2005-11-28 21:04:11 +0000566static const struct timedia_struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 int num;
Helge Dellere9422e02006-08-29 21:57:29 +0200568 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569} timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
Helge Dellere9422e02006-08-29 21:57:29 +0200573 { 8, timedia_eight_port }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574};
575
Russell King61a116e2006-07-03 15:22:35 +0100576static int pci_timedia_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577{
Helge Dellere9422e02006-08-29 21:57:29 +0200578 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 int i, j;
580
Helge Dellere9422e02006-08-29 21:57:29 +0200581 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582 ids = timedia_data[i].ids;
583 for (j = 0; ids[j]; j++)
584 if (dev->subsystem_device == ids[j])
585 return timedia_data[i].num;
586 }
587 return 0;
588}
589
590/*
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
593 */
594static int
Russell King975a1a72009-01-02 13:44:27 +0000595pci_timedia_setup(struct serial_private *priv,
596 const struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 struct uart_port *port, int idx)
598{
599 unsigned int bar = 0, offset = board->first_offset;
600
601 switch (idx) {
602 case 0:
603 bar = 0;
604 break;
605 case 1:
606 offset = board->uart_offset;
607 bar = 0;
608 break;
609 case 2:
610 bar = 1;
611 break;
612 case 3:
613 offset = board->uart_offset;
Dave Jonesc2cd6d32005-12-07 18:11:26 +0000614 /* FALLTHROUGH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 case 4: /* BAR 2 */
616 case 5: /* BAR 3 */
617 case 6: /* BAR 4 */
618 case 7: /* BAR 5 */
619 bar = idx - 2;
620 }
621
Russell King70db3d92005-07-27 11:34:27 +0100622 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623}
624
625/*
626 * Some Titan cards are also a little weird
627 */
628static int
Russell King70db3d92005-07-27 11:34:27 +0100629titan_400l_800l_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000630 const struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 struct uart_port *port, int idx)
632{
633 unsigned int bar, offset = board->first_offset;
634
635 switch (idx) {
636 case 0:
637 bar = 1;
638 break;
639 case 1:
640 bar = 2;
641 break;
642 default:
643 bar = 4;
644 offset = (idx - 2) * board->uart_offset;
645 }
646
Russell King70db3d92005-07-27 11:34:27 +0100647 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648}
649
Russell King61a116e2006-07-03 15:22:35 +0100650static int pci_xircom_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651{
652 msleep(100);
653 return 0;
654}
655
Will Page04bf7e72009-04-06 17:32:15 +0100656static int pci_ni8420_init(struct pci_dev *dev)
657{
658 void __iomem *p;
659 unsigned long base, len;
660 unsigned int bar = 0;
661
662 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
663 moan_device("no memory in bar", dev);
664 return 0;
665 }
666
667 base = pci_resource_start(dev, bar);
668 len = pci_resource_len(dev, bar);
669 p = ioremap_nocache(base, len);
670 if (p == NULL)
671 return -ENOMEM;
672
673 /* Enable CPU Interrupt */
674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
675 p + NI8420_INT_ENABLE_REG);
676
677 iounmap(p);
678 return 0;
679}
680
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100681#define MITE_IOWBSR1_WSIZE 0xa
682#define MITE_IOWBSR1_WIN_OFFSET 0x800
683#define MITE_IOWBSR1_WENAB (1 << 7)
684#define MITE_LCIMR1_IO_IE_0 (1 << 24)
685#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
687
688static int pci_ni8430_init(struct pci_dev *dev)
689{
690 void __iomem *p;
691 unsigned long base, len;
692 u32 device_window;
693 unsigned int bar = 0;
694
695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
696 moan_device("no memory in bar", dev);
697 return 0;
698 }
699
700 base = pci_resource_start(dev, bar);
701 len = pci_resource_len(dev, bar);
702 p = ioremap_nocache(base, len);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /* Set device window address and size in BAR0 */
707 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
709 writel(device_window, p + MITE_IOWBSR1);
710
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
713 p + MITE_IOWCR1);
714
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
717
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
720
721 iounmap(p);
722 return 0;
723}
724
725/* UART Port Control Register */
726#define NI8430_PORTCON 0x0f
727#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
728
729static int
Alan Coxbf538fe2009-04-06 17:35:42 +0100730pci_ni8430_setup(struct serial_private *priv,
731 const struct pciserial_board *board,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100732 struct uart_port *port, int idx)
733{
734 void __iomem *p;
735 unsigned long base, len;
736 unsigned int bar, offset = board->first_offset;
737
738 if (idx >= board->num_ports)
739 return 1;
740
741 bar = FL_GET_BASE(board->flags);
742 offset += idx * board->uart_offset;
743
744 base = pci_resource_start(priv->dev, bar);
745 len = pci_resource_len(priv->dev, bar);
746 p = ioremap_nocache(base, len);
747
748 /* enable the transciever */
749 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
750 p + offset + NI8430_PORTCON);
751
752 iounmap(p);
753
754 return setup_port(priv, port, bar, offset, board->reg_shift);
755}
756
757
Russell King61a116e2006-07-03 15:22:35 +0100758static int pci_netmos_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759{
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial = dev->subsystem_device & 0xf;
762
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -0800763 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
764 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
Michael Bueschc4285b42009-06-30 11:41:21 -0700765 return 0;
Jiri Slaby25cf9bc2009-01-15 13:30:34 +0000766 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
767 dev->subsystem_device == 0x0299)
768 return 0;
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 if (num_serial == 0)
771 return -ENODEV;
772 return num_serial;
773}
774
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700775/*
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700776 * These chips are available with optionally one parallel port and up to
777 * two serial ports. Unfortunately they all have the same product id.
778 *
779 * Basic configuration is done over a region of 32 I/O ports. The base
780 * ioport is called INTA or INTC, depending on docs/other drivers.
781 *
782 * The region of the 32 I/O ports is configured in POSIO0R...
783 */
784
785/* registers */
786#define ITE_887x_MISCR 0x9c
787#define ITE_887x_INTCBAR 0x78
788#define ITE_887x_UARTBAR 0x7c
789#define ITE_887x_PS0BAR 0x10
790#define ITE_887x_POSIO0 0x60
791
792/* I/O space size */
793#define ITE_887x_IOSIZE 32
794/* I/O space size (bits 26-24; 8 bytes = 011b) */
795#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
796/* I/O space size (bits 26-24; 32 bytes = 101b) */
797#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
798/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
799#define ITE_887x_POSIO_SPEED (3 << 29)
800/* enable IO_Space bit */
801#define ITE_887x_POSIO_ENABLE (1 << 31)
802
Ralf Baechlef79abb82007-08-30 23:56:31 -0700803static int pci_ite887x_init(struct pci_dev *dev)
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700804{
805 /* inta_addr are the configuration addresses of the ITE */
806 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
807 0x200, 0x280, 0 };
808 int ret, i, type;
809 struct resource *iobase = NULL;
810 u32 miscr, uartbar, ioport;
811
812 /* search for the base-ioport */
813 i = 0;
814 while (inta_addr[i] && iobase == NULL) {
815 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
816 "ite887x");
817 if (iobase != NULL) {
818 /* write POSIO0R - speed | size | ioport */
819 pci_write_config_dword(dev, ITE_887x_POSIO0,
820 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
821 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
822 /* write INTCBAR - ioport */
Alan Cox5756ee92008-02-08 04:18:51 -0800823 pci_write_config_dword(dev, ITE_887x_INTCBAR,
824 inta_addr[i]);
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700825 ret = inb(inta_addr[i]);
826 if (ret != 0xff) {
827 /* ioport connected */
828 break;
829 }
830 release_region(iobase->start, ITE_887x_IOSIZE);
831 iobase = NULL;
832 }
833 i++;
834 }
835
836 if (!inta_addr[i]) {
837 printk(KERN_ERR "ite887x: could not find iobase\n");
838 return -ENODEV;
839 }
840
841 /* start of undocumented type checking (see parport_pc.c) */
842 type = inb(iobase->start + 0x18) & 0x0f;
843
844 switch (type) {
845 case 0x2: /* ITE8871 (1P) */
846 case 0xa: /* ITE8875 (1P) */
847 ret = 0;
848 break;
849 case 0xe: /* ITE8872 (2S1P) */
850 ret = 2;
851 break;
852 case 0x6: /* ITE8873 (1S) */
853 ret = 1;
854 break;
855 case 0x8: /* ITE8874 (2S) */
856 ret = 2;
857 break;
858 default:
859 moan_device("Unknown ITE887x", dev);
860 ret = -ENODEV;
861 }
862
863 /* configure all serial ports */
864 for (i = 0; i < ret; i++) {
865 /* read the I/O port from the device */
866 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
867 &ioport);
868 ioport &= 0x0000FF00; /* the actual base address */
869 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
870 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
871 ITE_887x_POSIO_IOSIZE_8 | ioport);
872
873 /* write the ioport to the UARTBAR */
874 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
875 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
876 uartbar |= (ioport << (16 * i)); /* set the ioport */
877 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
878
879 /* get current config */
880 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
881 /* disable interrupts (UARTx_Routing[3:0]) */
882 miscr &= ~(0xf << (12 - 4 * i));
883 /* activate the UART (UARTx_En) */
884 miscr |= 1 << (23 - i);
885 /* write new config with activated UART */
886 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
887 }
888
889 if (ret <= 0) {
890 /* the device has no UARTs if we get here */
891 release_region(iobase->start, ITE_887x_IOSIZE);
892 }
893
894 return ret;
895}
896
897static void __devexit pci_ite887x_exit(struct pci_dev *dev)
898{
899 u32 ioport;
900 /* the ioport is bit 0-15 in POSIO0R */
901 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
902 ioport &= 0xffff;
903 release_region(ioport, ITE_887x_IOSIZE);
904}
905
Russell King9f2a0362009-01-02 13:44:20 +0000906/*
907 * Oxford Semiconductor Inc.
908 * Check that device is part of the Tornado range of devices, then determine
909 * the number of ports available on the device.
910 */
911static int pci_oxsemi_tornado_init(struct pci_dev *dev)
912{
913 u8 __iomem *p;
914 unsigned long deviceID;
915 unsigned int number_uarts = 0;
916
917 /* OxSemi Tornado devices are all 0xCxxx */
918 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
919 (dev->device & 0xF000) != 0xC000)
920 return 0;
921
922 p = pci_iomap(dev, 0, 5);
923 if (p == NULL)
924 return -ENOMEM;
925
926 deviceID = ioread32(p);
927 /* Tornado device */
928 if (deviceID == 0x07000200) {
929 number_uarts = ioread8(p + 4);
930 printk(KERN_DEBUG
931 "%d ports detected on Oxford PCI Express device\n",
932 number_uarts);
933 }
934 pci_iounmap(dev, p);
935 return number_uarts;
936}
937
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938static int
Russell King975a1a72009-01-02 13:44:27 +0000939pci_default_setup(struct serial_private *priv,
940 const struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941 struct uart_port *port, int idx)
942{
943 unsigned int bar, offset = board->first_offset, maxnr;
944
945 bar = FL_GET_BASE(board->flags);
946 if (board->flags & FL_BASE_BARS)
947 bar += idx;
948 else
949 offset += idx * board->uart_offset;
950
Greg Kroah-Hartman2427ddd2006-06-12 17:07:52 -0700951 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
952 (board->reg_shift + 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953
954 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
955 return 1;
Alan Cox5756ee92008-02-08 04:18:51 -0800956
Russell King70db3d92005-07-27 11:34:27 +0100957 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958}
959
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -0800960static int skip_tx_en_setup(struct serial_private *priv,
961 const struct pciserial_board *board,
962 struct uart_port *port, int idx)
963{
964 port->flags |= UPF_NO_TXEN_TEST;
965 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
966 "[%04x:%04x] subsystem [%04x:%04x]\n",
967 priv->dev->vendor,
968 priv->dev->device,
969 priv->dev->subsystem_vendor,
970 priv->dev->subsystem_device);
971
972 return pci_default_setup(priv, board, port, idx);
973}
974
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975/* This should be in linux/pci_ids.h */
976#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
977#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
978#define PCI_DEVICE_ID_OCTPRO 0x0001
979#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
980#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
981#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
982#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
Michael Bramer78d70d42009-01-27 11:51:16 +0000983#define PCI_VENDOR_ID_ADVANTECH 0x13fe
984#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -0700986/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
987#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
988
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989/*
990 * Master list of serial port init/setup/exit quirks.
991 * This does not describe the general nature of the port.
992 * (ie, baud base, number and location of ports, etc)
993 *
994 * This list is ordered alphabetically by vendor then device.
995 * Specific entries must come before more generic entries.
996 */
Sam Ravnborg7a63ce52008-04-28 02:14:02 -0700997static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800999 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1000 */
1001 {
1002 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1003 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1004 .subvendor = PCI_ANY_ID,
1005 .subdevice = PCI_ANY_ID,
1006 .setup = addidata_apci7800_setup,
1007 },
1008 /*
Russell King61a116e2006-07-03 15:22:35 +01001009 * AFAVLAB cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 * It is not clear whether this applies to all products.
1011 */
1012 {
1013 .vendor = PCI_VENDOR_ID_AFAVLAB,
1014 .device = PCI_ANY_ID,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .setup = afavlab_setup,
1018 },
1019 /*
1020 * HP Diva
1021 */
1022 {
1023 .vendor = PCI_VENDOR_ID_HP,
1024 .device = PCI_DEVICE_ID_HP_DIVA,
1025 .subvendor = PCI_ANY_ID,
1026 .subdevice = PCI_ANY_ID,
1027 .init = pci_hp_diva_init,
1028 .setup = pci_hp_diva_setup,
1029 },
1030 /*
1031 * Intel
1032 */
1033 {
1034 .vendor = PCI_VENDOR_ID_INTEL,
1035 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1036 .subvendor = 0xe4bf,
1037 .subdevice = PCI_ANY_ID,
1038 .init = pci_inteli960ni_init,
1039 .setup = pci_default_setup,
1040 },
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -08001041 {
1042 .vendor = PCI_VENDOR_ID_INTEL,
1043 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1044 .subvendor = PCI_ANY_ID,
1045 .subdevice = PCI_ANY_ID,
1046 .setup = skip_tx_en_setup,
1047 },
1048 {
1049 .vendor = PCI_VENDOR_ID_INTEL,
1050 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1051 .subvendor = PCI_ANY_ID,
1052 .subdevice = PCI_ANY_ID,
1053 .setup = skip_tx_en_setup,
1054 },
1055 {
1056 .vendor = PCI_VENDOR_ID_INTEL,
1057 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .setup = skip_tx_en_setup,
1061 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062 /*
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001063 * ITE
1064 */
1065 {
1066 .vendor = PCI_VENDOR_ID_ITE,
1067 .device = PCI_DEVICE_ID_ITE_8872,
1068 .subvendor = PCI_ANY_ID,
1069 .subdevice = PCI_ANY_ID,
1070 .init = pci_ite887x_init,
1071 .setup = pci_default_setup,
1072 .exit = __devexit_p(pci_ite887x_exit),
1073 },
1074 /*
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01001075 * National Instruments
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_NI,
Will Page04bf7e72009-04-06 17:32:15 +01001079 .device = PCI_DEVICE_ID_NI_PCI23216,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ni8420_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ni8420_exit),
1085 },
1086 {
1087 .vendor = PCI_VENDOR_ID_NI,
1088 .device = PCI_DEVICE_ID_NI_PCI2328,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .init = pci_ni8420_init,
1092 .setup = pci_default_setup,
1093 .exit = __devexit_p(pci_ni8420_exit),
1094 },
1095 {
1096 .vendor = PCI_VENDOR_ID_NI,
1097 .device = PCI_DEVICE_ID_NI_PCI2324,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .init = pci_ni8420_init,
1101 .setup = pci_default_setup,
1102 .exit = __devexit_p(pci_ni8420_exit),
1103 },
1104 {
1105 .vendor = PCI_VENDOR_ID_NI,
1106 .device = PCI_DEVICE_ID_NI_PCI2322,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .init = pci_ni8420_init,
1110 .setup = pci_default_setup,
1111 .exit = __devexit_p(pci_ni8420_exit),
1112 },
1113 {
1114 .vendor = PCI_VENDOR_ID_NI,
1115 .device = PCI_DEVICE_ID_NI_PCI2324I,
1116 .subvendor = PCI_ANY_ID,
1117 .subdevice = PCI_ANY_ID,
1118 .init = pci_ni8420_init,
1119 .setup = pci_default_setup,
1120 .exit = __devexit_p(pci_ni8420_exit),
1121 },
1122 {
1123 .vendor = PCI_VENDOR_ID_NI,
1124 .device = PCI_DEVICE_ID_NI_PCI2322I,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .init = pci_ni8420_init,
1128 .setup = pci_default_setup,
1129 .exit = __devexit_p(pci_ni8420_exit),
1130 },
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01001187 .device = PCI_ANY_ID,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8430_init,
1191 .setup = pci_ni8430_setup,
1192 .exit = __devexit_p(pci_ni8430_exit),
1193 },
1194 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 * Panacom
1196 */
1197 {
1198 .vendor = PCI_VENDOR_ID_PANACOM,
1199 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_plx9050_init,
1203 .setup = pci_default_setup,
1204 .exit = __devexit_p(pci_plx9050_exit),
Alan Cox5756ee92008-02-08 04:18:51 -08001205 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206 {
1207 .vendor = PCI_VENDOR_ID_PANACOM,
1208 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .init = pci_plx9050_init,
1212 .setup = pci_default_setup,
1213 .exit = __devexit_p(pci_plx9050_exit),
1214 },
1215 /*
1216 * PLX
1217 */
1218 {
1219 .vendor = PCI_VENDOR_ID_PLX,
Thomas Hoehn48212002007-02-10 01:46:05 -08001220 .device = PCI_DEVICE_ID_PLX_9030,
1221 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1222 .subdevice = PCI_ANY_ID,
1223 .setup = pci_default_setup,
1224 },
1225 {
1226 .vendor = PCI_VENDOR_ID_PLX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 .device = PCI_DEVICE_ID_PLX_9050,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001228 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1229 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1230 .init = pci_plx9050_init,
1231 .setup = pci_default_setup,
1232 .exit = __devexit_p(pci_plx9050_exit),
1233 },
1234 {
1235 .vendor = PCI_VENDOR_ID_PLX,
1236 .device = PCI_DEVICE_ID_PLX_9050,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1238 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1239 .init = pci_plx9050_init,
1240 .setup = pci_default_setup,
1241 .exit = __devexit_p(pci_plx9050_exit),
1242 },
1243 {
1244 .vendor = PCI_VENDOR_ID_PLX,
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -07001245 .device = PCI_DEVICE_ID_PLX_9050,
1246 .subvendor = PCI_VENDOR_ID_PLX,
1247 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1248 .init = pci_plx9050_init,
1249 .setup = pci_default_setup,
1250 .exit = __devexit_p(pci_plx9050_exit),
1251 },
1252 {
1253 .vendor = PCI_VENDOR_ID_PLX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1255 .subvendor = PCI_VENDOR_ID_PLX,
1256 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1257 .init = pci_plx9050_init,
1258 .setup = pci_default_setup,
1259 .exit = __devexit_p(pci_plx9050_exit),
1260 },
1261 /*
1262 * SBS Technologies, Inc., PMC-OCTALPRO 232
1263 */
1264 {
1265 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1266 .device = PCI_DEVICE_ID_OCTPRO,
1267 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1268 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1269 .init = sbs_init,
1270 .setup = sbs_setup,
1271 .exit = __devexit_p(sbs_exit),
1272 },
1273 /*
1274 * SBS Technologies, Inc., PMC-OCTALPRO 422
1275 */
1276 {
1277 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1278 .device = PCI_DEVICE_ID_OCTPRO,
1279 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1280 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1281 .init = sbs_init,
1282 .setup = sbs_setup,
1283 .exit = __devexit_p(sbs_exit),
1284 },
1285 /*
1286 * SBS Technologies, Inc., P-Octal 232
1287 */
1288 {
1289 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1290 .device = PCI_DEVICE_ID_OCTPRO,
1291 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1292 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1293 .init = sbs_init,
1294 .setup = sbs_setup,
1295 .exit = __devexit_p(sbs_exit),
1296 },
1297 /*
1298 * SBS Technologies, Inc., P-Octal 422
1299 */
1300 {
1301 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1302 .device = PCI_DEVICE_ID_OCTPRO,
1303 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1304 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1305 .init = sbs_init,
1306 .setup = sbs_setup,
1307 .exit = __devexit_p(sbs_exit),
1308 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309 /*
Russell King61a116e2006-07-03 15:22:35 +01001310 * SIIG cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311 */
1312 {
1313 .vendor = PCI_VENDOR_ID_SIIG,
Russell King67d74b82005-07-27 11:33:03 +01001314 .device = PCI_ANY_ID,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 .subvendor = PCI_ANY_ID,
1316 .subdevice = PCI_ANY_ID,
Russell King67d74b82005-07-27 11:33:03 +01001317 .init = pci_siig_init,
Andrey Panin3ec9c592006-02-02 20:15:09 +00001318 .setup = pci_siig_setup,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 },
1320 /*
1321 * Titan cards
1322 */
1323 {
1324 .vendor = PCI_VENDOR_ID_TITAN,
1325 .device = PCI_DEVICE_ID_TITAN_400L,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .setup = titan_400l_800l_setup,
1329 },
1330 {
1331 .vendor = PCI_VENDOR_ID_TITAN,
1332 .device = PCI_DEVICE_ID_TITAN_800L,
1333 .subvendor = PCI_ANY_ID,
1334 .subdevice = PCI_ANY_ID,
1335 .setup = titan_400l_800l_setup,
1336 },
1337 /*
1338 * Timedia cards
1339 */
1340 {
1341 .vendor = PCI_VENDOR_ID_TIMEDIA,
1342 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1343 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1344 .subdevice = PCI_ANY_ID,
1345 .init = pci_timedia_init,
1346 .setup = pci_timedia_setup,
1347 },
1348 {
1349 .vendor = PCI_VENDOR_ID_TIMEDIA,
1350 .device = PCI_ANY_ID,
1351 .subvendor = PCI_ANY_ID,
1352 .subdevice = PCI_ANY_ID,
1353 .setup = pci_timedia_setup,
1354 },
1355 /*
1356 * Xircom cards
1357 */
1358 {
1359 .vendor = PCI_VENDOR_ID_XIRCOM,
1360 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
1363 .init = pci_xircom_init,
1364 .setup = pci_default_setup,
1365 },
1366 /*
Russell King61a116e2006-07-03 15:22:35 +01001367 * Netmos cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 */
1369 {
1370 .vendor = PCI_VENDOR_ID_NETMOS,
1371 .device = PCI_ANY_ID,
1372 .subvendor = PCI_ANY_ID,
1373 .subdevice = PCI_ANY_ID,
1374 .init = pci_netmos_init,
1375 .setup = pci_default_setup,
1376 },
1377 /*
Russell King9f2a0362009-01-02 13:44:20 +00001378 * For Oxford Semiconductor and Mainpine
1379 */
1380 {
1381 .vendor = PCI_VENDOR_ID_OXSEMI,
1382 .device = PCI_ANY_ID,
1383 .subvendor = PCI_ANY_ID,
1384 .subdevice = PCI_ANY_ID,
1385 .init = pci_oxsemi_tornado_init,
1386 .setup = pci_default_setup,
1387 },
1388 {
1389 .vendor = PCI_VENDOR_ID_MAINPINE,
1390 .device = PCI_ANY_ID,
1391 .subvendor = PCI_ANY_ID,
1392 .subdevice = PCI_ANY_ID,
1393 .init = pci_oxsemi_tornado_init,
1394 .setup = pci_default_setup,
1395 },
1396 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397 * Default "match everything" terminator entry
1398 */
1399 {
1400 .vendor = PCI_ANY_ID,
1401 .device = PCI_ANY_ID,
1402 .subvendor = PCI_ANY_ID,
1403 .subdevice = PCI_ANY_ID,
1404 .setup = pci_default_setup,
1405 }
1406};
1407
1408static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1409{
1410 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1411}
1412
1413static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1414{
1415 struct pci_serial_quirk *quirk;
1416
1417 for (quirk = pci_serial_quirks; ; quirk++)
1418 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1419 quirk_id_matches(quirk->device, dev->device) &&
1420 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1421 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
Alan Cox5756ee92008-02-08 04:18:51 -08001422 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423 return quirk;
1424}
1425
Andrew Mortondd68e882006-01-05 10:55:26 +00001426static inline int get_pci_irq(struct pci_dev *dev,
Russell King975a1a72009-01-02 13:44:27 +00001427 const struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428{
1429 if (board->flags & FL_NOIRQ)
1430 return 0;
1431 else
1432 return dev->irq;
1433}
1434
1435/*
1436 * This is the configuration table for all of the PCI serial boards
1437 * which we support. It is directly indexed by the pci_board_num_t enum
1438 * value, which is encoded in the pci_device_id PCI probe table's
1439 * driver_data member.
1440 *
1441 * The makeup of these names are:
Gareth Howlett26e92862006-01-04 17:00:42 +00001442 * pbn_bn{_bt}_n_baud{_offsetinhex}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001444 * bn = PCI BAR number
1445 * bt = Index using PCI BARs
1446 * n = number of serial ports
1447 * baud = baud rate
1448 * offsetinhex = offset for each sequential port (in hex)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001450 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
Russell Kingf1690f32005-05-06 10:19:09 +01001451 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 * Please note: in theory if n = 1, _bt infix should make no difference.
1453 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1454 */
1455enum pci_board_num_t {
1456 pbn_default = 0,
1457
1458 pbn_b0_1_115200,
1459 pbn_b0_2_115200,
1460 pbn_b0_4_115200,
1461 pbn_b0_5_115200,
Alan Coxbf0df632007-10-16 01:24:00 -07001462 pbn_b0_8_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463
1464 pbn_b0_1_921600,
1465 pbn_b0_2_921600,
1466 pbn_b0_4_921600,
1467
David Ransondb1de152005-07-27 11:43:55 -07001468 pbn_b0_2_1130000,
1469
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001470 pbn_b0_4_1152000,
1471
Gareth Howlett26e92862006-01-04 17:00:42 +00001472 pbn_b0_2_1843200,
1473 pbn_b0_4_1843200,
1474
1475 pbn_b0_2_1843200_200,
1476 pbn_b0_4_1843200_200,
1477 pbn_b0_8_1843200_200,
1478
Lee Howard7106b4e2008-10-21 13:48:58 +01001479 pbn_b0_1_4000000,
1480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 pbn_b0_bt_1_115200,
1482 pbn_b0_bt_2_115200,
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08001483 pbn_b0_bt_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484 pbn_b0_bt_8_115200,
1485
1486 pbn_b0_bt_1_460800,
1487 pbn_b0_bt_2_460800,
1488 pbn_b0_bt_4_460800,
1489
1490 pbn_b0_bt_1_921600,
1491 pbn_b0_bt_2_921600,
1492 pbn_b0_bt_4_921600,
1493 pbn_b0_bt_8_921600,
1494
1495 pbn_b1_1_115200,
1496 pbn_b1_2_115200,
1497 pbn_b1_4_115200,
1498 pbn_b1_8_115200,
Will Page04bf7e72009-04-06 17:32:15 +01001499 pbn_b1_16_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500
1501 pbn_b1_1_921600,
1502 pbn_b1_2_921600,
1503 pbn_b1_4_921600,
1504 pbn_b1_8_921600,
1505
Gareth Howlett26e92862006-01-04 17:00:42 +00001506 pbn_b1_2_1250000,
1507
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001508 pbn_b1_bt_1_115200,
Will Page04bf7e72009-04-06 17:32:15 +01001509 pbn_b1_bt_2_115200,
1510 pbn_b1_bt_4_115200,
1511
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512 pbn_b1_bt_2_921600,
1513
1514 pbn_b1_1_1382400,
1515 pbn_b1_2_1382400,
1516 pbn_b1_4_1382400,
1517 pbn_b1_8_1382400,
1518
1519 pbn_b2_1_115200,
Peter Horton737c1752006-08-26 09:07:36 +01001520 pbn_b2_2_115200,
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001521 pbn_b2_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 pbn_b2_8_115200,
1523
1524 pbn_b2_1_460800,
1525 pbn_b2_4_460800,
1526 pbn_b2_8_460800,
1527 pbn_b2_16_460800,
1528
1529 pbn_b2_1_921600,
1530 pbn_b2_4_921600,
1531 pbn_b2_8_921600,
1532
1533 pbn_b2_bt_1_115200,
1534 pbn_b2_bt_2_115200,
1535 pbn_b2_bt_4_115200,
1536
1537 pbn_b2_bt_2_921600,
1538 pbn_b2_bt_4_921600,
1539
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001540 pbn_b3_2_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 pbn_b3_4_115200,
1542 pbn_b3_8_115200,
1543
1544 /*
1545 * Board-specific versions.
1546 */
1547 pbn_panacom,
1548 pbn_panacom2,
1549 pbn_panacom4,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001550 pbn_exsys_4055,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 pbn_plx_romulus,
1552 pbn_oxsemi,
Lee Howard7106b4e2008-10-21 13:48:58 +01001553 pbn_oxsemi_1_4000000,
1554 pbn_oxsemi_2_4000000,
1555 pbn_oxsemi_4_4000000,
1556 pbn_oxsemi_8_4000000,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 pbn_intel_i960,
1558 pbn_sgi_ioc3,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559 pbn_computone_4,
1560 pbn_computone_6,
1561 pbn_computone_8,
1562 pbn_sbsxrsio,
1563 pbn_exar_XR17C152,
1564 pbn_exar_XR17C154,
1565 pbn_exar_XR17C158,
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07001566 pbn_exar_ibm_saturn,
Olof Johanssonaa798502007-08-22 14:01:55 -07001567 pbn_pasemi_1682M,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01001568 pbn_ni8430_2,
1569 pbn_ni8430_4,
1570 pbn_ni8430_8,
1571 pbn_ni8430_16,
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07001572 pbn_ADDIDATA_PCIe_1_3906250,
1573 pbn_ADDIDATA_PCIe_2_3906250,
1574 pbn_ADDIDATA_PCIe_4_3906250,
1575 pbn_ADDIDATA_PCIe_8_3906250,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576};
1577
1578/*
1579 * uart_offset - the space between channels
1580 * reg_shift - describes how the UART registers are mapped
1581 * to PCI memory by the card.
1582 * For example IER register on SBS, Inc. PMC-OctPro is located at
1583 * offset 0x10 from the UART base, while UART_IER is defined as 1
1584 * in include/linux/serial_reg.h,
1585 * see first lines of serial_in() and serial_out() in 8250.c
1586*/
1587
Russell King1c7c1fe2005-07-27 11:31:19 +01001588static struct pciserial_board pci_boards[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 [pbn_default] = {
1590 .flags = FL_BASE0,
1591 .num_ports = 1,
1592 .base_baud = 115200,
1593 .uart_offset = 8,
1594 },
1595 [pbn_b0_1_115200] = {
1596 .flags = FL_BASE0,
1597 .num_ports = 1,
1598 .base_baud = 115200,
1599 .uart_offset = 8,
1600 },
1601 [pbn_b0_2_115200] = {
1602 .flags = FL_BASE0,
1603 .num_ports = 2,
1604 .base_baud = 115200,
1605 .uart_offset = 8,
1606 },
1607 [pbn_b0_4_115200] = {
1608 .flags = FL_BASE0,
1609 .num_ports = 4,
1610 .base_baud = 115200,
1611 .uart_offset = 8,
1612 },
1613 [pbn_b0_5_115200] = {
1614 .flags = FL_BASE0,
1615 .num_ports = 5,
1616 .base_baud = 115200,
1617 .uart_offset = 8,
1618 },
Alan Coxbf0df632007-10-16 01:24:00 -07001619 [pbn_b0_8_115200] = {
1620 .flags = FL_BASE0,
1621 .num_ports = 8,
1622 .base_baud = 115200,
1623 .uart_offset = 8,
1624 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625 [pbn_b0_1_921600] = {
1626 .flags = FL_BASE0,
1627 .num_ports = 1,
1628 .base_baud = 921600,
1629 .uart_offset = 8,
1630 },
1631 [pbn_b0_2_921600] = {
1632 .flags = FL_BASE0,
1633 .num_ports = 2,
1634 .base_baud = 921600,
1635 .uart_offset = 8,
1636 },
1637 [pbn_b0_4_921600] = {
1638 .flags = FL_BASE0,
1639 .num_ports = 4,
1640 .base_baud = 921600,
1641 .uart_offset = 8,
1642 },
David Ransondb1de152005-07-27 11:43:55 -07001643
1644 [pbn_b0_2_1130000] = {
1645 .flags = FL_BASE0,
1646 .num_ports = 2,
1647 .base_baud = 1130000,
1648 .uart_offset = 8,
1649 },
1650
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001651 [pbn_b0_4_1152000] = {
1652 .flags = FL_BASE0,
1653 .num_ports = 4,
1654 .base_baud = 1152000,
1655 .uart_offset = 8,
1656 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657
Gareth Howlett26e92862006-01-04 17:00:42 +00001658 [pbn_b0_2_1843200] = {
1659 .flags = FL_BASE0,
1660 .num_ports = 2,
1661 .base_baud = 1843200,
1662 .uart_offset = 8,
1663 },
1664 [pbn_b0_4_1843200] = {
1665 .flags = FL_BASE0,
1666 .num_ports = 4,
1667 .base_baud = 1843200,
1668 .uart_offset = 8,
1669 },
1670
1671 [pbn_b0_2_1843200_200] = {
1672 .flags = FL_BASE0,
1673 .num_ports = 2,
1674 .base_baud = 1843200,
1675 .uart_offset = 0x200,
1676 },
1677 [pbn_b0_4_1843200_200] = {
1678 .flags = FL_BASE0,
1679 .num_ports = 4,
1680 .base_baud = 1843200,
1681 .uart_offset = 0x200,
1682 },
1683 [pbn_b0_8_1843200_200] = {
1684 .flags = FL_BASE0,
1685 .num_ports = 8,
1686 .base_baud = 1843200,
1687 .uart_offset = 0x200,
1688 },
Lee Howard7106b4e2008-10-21 13:48:58 +01001689 [pbn_b0_1_4000000] = {
1690 .flags = FL_BASE0,
1691 .num_ports = 1,
1692 .base_baud = 4000000,
1693 .uart_offset = 8,
1694 },
Gareth Howlett26e92862006-01-04 17:00:42 +00001695
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696 [pbn_b0_bt_1_115200] = {
1697 .flags = FL_BASE0|FL_BASE_BARS,
1698 .num_ports = 1,
1699 .base_baud = 115200,
1700 .uart_offset = 8,
1701 },
1702 [pbn_b0_bt_2_115200] = {
1703 .flags = FL_BASE0|FL_BASE_BARS,
1704 .num_ports = 2,
1705 .base_baud = 115200,
1706 .uart_offset = 8,
1707 },
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08001708 [pbn_b0_bt_4_115200] = {
1709 .flags = FL_BASE0|FL_BASE_BARS,
1710 .num_ports = 4,
1711 .base_baud = 115200,
1712 .uart_offset = 8,
1713 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714 [pbn_b0_bt_8_115200] = {
1715 .flags = FL_BASE0|FL_BASE_BARS,
1716 .num_ports = 8,
1717 .base_baud = 115200,
1718 .uart_offset = 8,
1719 },
1720
1721 [pbn_b0_bt_1_460800] = {
1722 .flags = FL_BASE0|FL_BASE_BARS,
1723 .num_ports = 1,
1724 .base_baud = 460800,
1725 .uart_offset = 8,
1726 },
1727 [pbn_b0_bt_2_460800] = {
1728 .flags = FL_BASE0|FL_BASE_BARS,
1729 .num_ports = 2,
1730 .base_baud = 460800,
1731 .uart_offset = 8,
1732 },
1733 [pbn_b0_bt_4_460800] = {
1734 .flags = FL_BASE0|FL_BASE_BARS,
1735 .num_ports = 4,
1736 .base_baud = 460800,
1737 .uart_offset = 8,
1738 },
1739
1740 [pbn_b0_bt_1_921600] = {
1741 .flags = FL_BASE0|FL_BASE_BARS,
1742 .num_ports = 1,
1743 .base_baud = 921600,
1744 .uart_offset = 8,
1745 },
1746 [pbn_b0_bt_2_921600] = {
1747 .flags = FL_BASE0|FL_BASE_BARS,
1748 .num_ports = 2,
1749 .base_baud = 921600,
1750 .uart_offset = 8,
1751 },
1752 [pbn_b0_bt_4_921600] = {
1753 .flags = FL_BASE0|FL_BASE_BARS,
1754 .num_ports = 4,
1755 .base_baud = 921600,
1756 .uart_offset = 8,
1757 },
1758 [pbn_b0_bt_8_921600] = {
1759 .flags = FL_BASE0|FL_BASE_BARS,
1760 .num_ports = 8,
1761 .base_baud = 921600,
1762 .uart_offset = 8,
1763 },
1764
1765 [pbn_b1_1_115200] = {
1766 .flags = FL_BASE1,
1767 .num_ports = 1,
1768 .base_baud = 115200,
1769 .uart_offset = 8,
1770 },
1771 [pbn_b1_2_115200] = {
1772 .flags = FL_BASE1,
1773 .num_ports = 2,
1774 .base_baud = 115200,
1775 .uart_offset = 8,
1776 },
1777 [pbn_b1_4_115200] = {
1778 .flags = FL_BASE1,
1779 .num_ports = 4,
1780 .base_baud = 115200,
1781 .uart_offset = 8,
1782 },
1783 [pbn_b1_8_115200] = {
1784 .flags = FL_BASE1,
1785 .num_ports = 8,
1786 .base_baud = 115200,
1787 .uart_offset = 8,
1788 },
Will Page04bf7e72009-04-06 17:32:15 +01001789 [pbn_b1_16_115200] = {
1790 .flags = FL_BASE1,
1791 .num_ports = 16,
1792 .base_baud = 115200,
1793 .uart_offset = 8,
1794 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795
1796 [pbn_b1_1_921600] = {
1797 .flags = FL_BASE1,
1798 .num_ports = 1,
1799 .base_baud = 921600,
1800 .uart_offset = 8,
1801 },
1802 [pbn_b1_2_921600] = {
1803 .flags = FL_BASE1,
1804 .num_ports = 2,
1805 .base_baud = 921600,
1806 .uart_offset = 8,
1807 },
1808 [pbn_b1_4_921600] = {
1809 .flags = FL_BASE1,
1810 .num_ports = 4,
1811 .base_baud = 921600,
1812 .uart_offset = 8,
1813 },
1814 [pbn_b1_8_921600] = {
1815 .flags = FL_BASE1,
1816 .num_ports = 8,
1817 .base_baud = 921600,
1818 .uart_offset = 8,
1819 },
Gareth Howlett26e92862006-01-04 17:00:42 +00001820 [pbn_b1_2_1250000] = {
1821 .flags = FL_BASE1,
1822 .num_ports = 2,
1823 .base_baud = 1250000,
1824 .uart_offset = 8,
1825 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001827 [pbn_b1_bt_1_115200] = {
1828 .flags = FL_BASE1|FL_BASE_BARS,
1829 .num_ports = 1,
1830 .base_baud = 115200,
1831 .uart_offset = 8,
1832 },
Will Page04bf7e72009-04-06 17:32:15 +01001833 [pbn_b1_bt_2_115200] = {
1834 .flags = FL_BASE1|FL_BASE_BARS,
1835 .num_ports = 2,
1836 .base_baud = 115200,
1837 .uart_offset = 8,
1838 },
1839 [pbn_b1_bt_4_115200] = {
1840 .flags = FL_BASE1|FL_BASE_BARS,
1841 .num_ports = 4,
1842 .base_baud = 115200,
1843 .uart_offset = 8,
1844 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001845
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846 [pbn_b1_bt_2_921600] = {
1847 .flags = FL_BASE1|FL_BASE_BARS,
1848 .num_ports = 2,
1849 .base_baud = 921600,
1850 .uart_offset = 8,
1851 },
1852
1853 [pbn_b1_1_1382400] = {
1854 .flags = FL_BASE1,
1855 .num_ports = 1,
1856 .base_baud = 1382400,
1857 .uart_offset = 8,
1858 },
1859 [pbn_b1_2_1382400] = {
1860 .flags = FL_BASE1,
1861 .num_ports = 2,
1862 .base_baud = 1382400,
1863 .uart_offset = 8,
1864 },
1865 [pbn_b1_4_1382400] = {
1866 .flags = FL_BASE1,
1867 .num_ports = 4,
1868 .base_baud = 1382400,
1869 .uart_offset = 8,
1870 },
1871 [pbn_b1_8_1382400] = {
1872 .flags = FL_BASE1,
1873 .num_ports = 8,
1874 .base_baud = 1382400,
1875 .uart_offset = 8,
1876 },
1877
1878 [pbn_b2_1_115200] = {
1879 .flags = FL_BASE2,
1880 .num_ports = 1,
1881 .base_baud = 115200,
1882 .uart_offset = 8,
1883 },
Peter Horton737c1752006-08-26 09:07:36 +01001884 [pbn_b2_2_115200] = {
1885 .flags = FL_BASE2,
1886 .num_ports = 2,
1887 .base_baud = 115200,
1888 .uart_offset = 8,
1889 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001890 [pbn_b2_4_115200] = {
1891 .flags = FL_BASE2,
1892 .num_ports = 4,
1893 .base_baud = 115200,
1894 .uart_offset = 8,
1895 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896 [pbn_b2_8_115200] = {
1897 .flags = FL_BASE2,
1898 .num_ports = 8,
1899 .base_baud = 115200,
1900 .uart_offset = 8,
1901 },
1902
1903 [pbn_b2_1_460800] = {
1904 .flags = FL_BASE2,
1905 .num_ports = 1,
1906 .base_baud = 460800,
1907 .uart_offset = 8,
1908 },
1909 [pbn_b2_4_460800] = {
1910 .flags = FL_BASE2,
1911 .num_ports = 4,
1912 .base_baud = 460800,
1913 .uart_offset = 8,
1914 },
1915 [pbn_b2_8_460800] = {
1916 .flags = FL_BASE2,
1917 .num_ports = 8,
1918 .base_baud = 460800,
1919 .uart_offset = 8,
1920 },
1921 [pbn_b2_16_460800] = {
1922 .flags = FL_BASE2,
1923 .num_ports = 16,
1924 .base_baud = 460800,
1925 .uart_offset = 8,
1926 },
1927
1928 [pbn_b2_1_921600] = {
1929 .flags = FL_BASE2,
1930 .num_ports = 1,
1931 .base_baud = 921600,
1932 .uart_offset = 8,
1933 },
1934 [pbn_b2_4_921600] = {
1935 .flags = FL_BASE2,
1936 .num_ports = 4,
1937 .base_baud = 921600,
1938 .uart_offset = 8,
1939 },
1940 [pbn_b2_8_921600] = {
1941 .flags = FL_BASE2,
1942 .num_ports = 8,
1943 .base_baud = 921600,
1944 .uart_offset = 8,
1945 },
1946
1947 [pbn_b2_bt_1_115200] = {
1948 .flags = FL_BASE2|FL_BASE_BARS,
1949 .num_ports = 1,
1950 .base_baud = 115200,
1951 .uart_offset = 8,
1952 },
1953 [pbn_b2_bt_2_115200] = {
1954 .flags = FL_BASE2|FL_BASE_BARS,
1955 .num_ports = 2,
1956 .base_baud = 115200,
1957 .uart_offset = 8,
1958 },
1959 [pbn_b2_bt_4_115200] = {
1960 .flags = FL_BASE2|FL_BASE_BARS,
1961 .num_ports = 4,
1962 .base_baud = 115200,
1963 .uart_offset = 8,
1964 },
1965
1966 [pbn_b2_bt_2_921600] = {
1967 .flags = FL_BASE2|FL_BASE_BARS,
1968 .num_ports = 2,
1969 .base_baud = 921600,
1970 .uart_offset = 8,
1971 },
1972 [pbn_b2_bt_4_921600] = {
1973 .flags = FL_BASE2|FL_BASE_BARS,
1974 .num_ports = 4,
1975 .base_baud = 921600,
1976 .uart_offset = 8,
1977 },
1978
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001979 [pbn_b3_2_115200] = {
1980 .flags = FL_BASE3,
1981 .num_ports = 2,
1982 .base_baud = 115200,
1983 .uart_offset = 8,
1984 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985 [pbn_b3_4_115200] = {
1986 .flags = FL_BASE3,
1987 .num_ports = 4,
1988 .base_baud = 115200,
1989 .uart_offset = 8,
1990 },
1991 [pbn_b3_8_115200] = {
1992 .flags = FL_BASE3,
1993 .num_ports = 8,
1994 .base_baud = 115200,
1995 .uart_offset = 8,
1996 },
1997
1998 /*
1999 * Entries following this are board-specific.
2000 */
2001
2002 /*
2003 * Panacom - IOMEM
2004 */
2005 [pbn_panacom] = {
2006 .flags = FL_BASE2,
2007 .num_ports = 2,
2008 .base_baud = 921600,
2009 .uart_offset = 0x400,
2010 .reg_shift = 7,
2011 },
2012 [pbn_panacom2] = {
2013 .flags = FL_BASE2|FL_BASE_BARS,
2014 .num_ports = 2,
2015 .base_baud = 921600,
2016 .uart_offset = 0x400,
2017 .reg_shift = 7,
2018 },
2019 [pbn_panacom4] = {
2020 .flags = FL_BASE2|FL_BASE_BARS,
2021 .num_ports = 4,
2022 .base_baud = 921600,
2023 .uart_offset = 0x400,
2024 .reg_shift = 7,
2025 },
2026
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002027 [pbn_exsys_4055] = {
2028 .flags = FL_BASE2,
2029 .num_ports = 4,
2030 .base_baud = 115200,
2031 .uart_offset = 8,
2032 },
2033
Linus Torvalds1da177e2005-04-16 15:20:36 -07002034 /* I think this entry is broken - the first_offset looks wrong --rmk */
2035 [pbn_plx_romulus] = {
2036 .flags = FL_BASE2,
2037 .num_ports = 4,
2038 .base_baud = 921600,
2039 .uart_offset = 8 << 2,
2040 .reg_shift = 2,
2041 .first_offset = 0x03,
2042 },
2043
2044 /*
2045 * This board uses the size of PCI Base region 0 to
2046 * signal now many ports are available
2047 */
2048 [pbn_oxsemi] = {
2049 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2050 .num_ports = 32,
2051 .base_baud = 115200,
2052 .uart_offset = 8,
2053 },
Lee Howard7106b4e2008-10-21 13:48:58 +01002054 [pbn_oxsemi_1_4000000] = {
2055 .flags = FL_BASE0,
2056 .num_ports = 1,
2057 .base_baud = 4000000,
2058 .uart_offset = 0x200,
2059 .first_offset = 0x1000,
2060 },
2061 [pbn_oxsemi_2_4000000] = {
2062 .flags = FL_BASE0,
2063 .num_ports = 2,
2064 .base_baud = 4000000,
2065 .uart_offset = 0x200,
2066 .first_offset = 0x1000,
2067 },
2068 [pbn_oxsemi_4_4000000] = {
2069 .flags = FL_BASE0,
2070 .num_ports = 4,
2071 .base_baud = 4000000,
2072 .uart_offset = 0x200,
2073 .first_offset = 0x1000,
2074 },
2075 [pbn_oxsemi_8_4000000] = {
2076 .flags = FL_BASE0,
2077 .num_ports = 8,
2078 .base_baud = 4000000,
2079 .uart_offset = 0x200,
2080 .first_offset = 0x1000,
2081 },
2082
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083
2084 /*
2085 * EKF addition for i960 Boards form EKF with serial port.
2086 * Max 256 ports.
2087 */
2088 [pbn_intel_i960] = {
2089 .flags = FL_BASE0,
2090 .num_ports = 32,
2091 .base_baud = 921600,
2092 .uart_offset = 8 << 2,
2093 .reg_shift = 2,
2094 .first_offset = 0x10000,
2095 },
2096 [pbn_sgi_ioc3] = {
2097 .flags = FL_BASE0|FL_NOIRQ,
2098 .num_ports = 1,
2099 .base_baud = 458333,
2100 .uart_offset = 8,
2101 .reg_shift = 0,
2102 .first_offset = 0x20178,
2103 },
2104
2105 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002106 * Computone - uses IOMEM.
2107 */
2108 [pbn_computone_4] = {
2109 .flags = FL_BASE0,
2110 .num_ports = 4,
2111 .base_baud = 921600,
2112 .uart_offset = 0x40,
2113 .reg_shift = 2,
2114 .first_offset = 0x200,
2115 },
2116 [pbn_computone_6] = {
2117 .flags = FL_BASE0,
2118 .num_ports = 6,
2119 .base_baud = 921600,
2120 .uart_offset = 0x40,
2121 .reg_shift = 2,
2122 .first_offset = 0x200,
2123 },
2124 [pbn_computone_8] = {
2125 .flags = FL_BASE0,
2126 .num_ports = 8,
2127 .base_baud = 921600,
2128 .uart_offset = 0x40,
2129 .reg_shift = 2,
2130 .first_offset = 0x200,
2131 },
2132 [pbn_sbsxrsio] = {
2133 .flags = FL_BASE0,
2134 .num_ports = 8,
2135 .base_baud = 460800,
2136 .uart_offset = 256,
2137 .reg_shift = 4,
2138 },
2139 /*
2140 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2141 * Only basic 16550A support.
2142 * XR17C15[24] are not tested, but they should work.
2143 */
2144 [pbn_exar_XR17C152] = {
2145 .flags = FL_BASE0,
2146 .num_ports = 2,
2147 .base_baud = 921600,
2148 .uart_offset = 0x200,
2149 },
2150 [pbn_exar_XR17C154] = {
2151 .flags = FL_BASE0,
2152 .num_ports = 4,
2153 .base_baud = 921600,
2154 .uart_offset = 0x200,
2155 },
2156 [pbn_exar_XR17C158] = {
2157 .flags = FL_BASE0,
2158 .num_ports = 8,
2159 .base_baud = 921600,
2160 .uart_offset = 0x200,
2161 },
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07002162 [pbn_exar_ibm_saturn] = {
2163 .flags = FL_BASE0,
2164 .num_ports = 1,
2165 .base_baud = 921600,
2166 .uart_offset = 0x200,
2167 },
2168
Olof Johanssonaa798502007-08-22 14:01:55 -07002169 /*
2170 * PA Semi PWRficient PA6T-1682M on-chip UART
2171 */
2172 [pbn_pasemi_1682M] = {
2173 .flags = FL_BASE0,
2174 .num_ports = 1,
2175 .base_baud = 8333333,
2176 },
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002177 /*
2178 * National Instruments 843x
2179 */
2180 [pbn_ni8430_16] = {
2181 .flags = FL_BASE0,
2182 .num_ports = 16,
2183 .base_baud = 3686400,
2184 .uart_offset = 0x10,
2185 .first_offset = 0x800,
2186 },
2187 [pbn_ni8430_8] = {
2188 .flags = FL_BASE0,
2189 .num_ports = 8,
2190 .base_baud = 3686400,
2191 .uart_offset = 0x10,
2192 .first_offset = 0x800,
2193 },
2194 [pbn_ni8430_4] = {
2195 .flags = FL_BASE0,
2196 .num_ports = 4,
2197 .base_baud = 3686400,
2198 .uart_offset = 0x10,
2199 .first_offset = 0x800,
2200 },
2201 [pbn_ni8430_2] = {
2202 .flags = FL_BASE0,
2203 .num_ports = 2,
2204 .base_baud = 3686400,
2205 .uart_offset = 0x10,
2206 .first_offset = 0x800,
2207 },
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07002208 /*
2209 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2210 */
2211 [pbn_ADDIDATA_PCIe_1_3906250] = {
2212 .flags = FL_BASE0,
2213 .num_ports = 1,
2214 .base_baud = 3906250,
2215 .uart_offset = 0x200,
2216 .first_offset = 0x1000,
2217 },
2218 [pbn_ADDIDATA_PCIe_2_3906250] = {
2219 .flags = FL_BASE0,
2220 .num_ports = 2,
2221 .base_baud = 3906250,
2222 .uart_offset = 0x200,
2223 .first_offset = 0x1000,
2224 },
2225 [pbn_ADDIDATA_PCIe_4_3906250] = {
2226 .flags = FL_BASE0,
2227 .num_ports = 4,
2228 .base_baud = 3906250,
2229 .uart_offset = 0x200,
2230 .first_offset = 0x1000,
2231 },
2232 [pbn_ADDIDATA_PCIe_8_3906250] = {
2233 .flags = FL_BASE0,
2234 .num_ports = 8,
2235 .base_baud = 3906250,
2236 .uart_offset = 0x200,
2237 .first_offset = 0x1000,
2238 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002239};
2240
Christian Schmidt436bbd42007-08-22 14:01:19 -07002241static const struct pci_device_id softmodem_blacklist[] = {
Alan Cox5756ee92008-02-08 04:18:51 -08002242 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
Christian Schmidt436bbd42007-08-22 14:01:19 -07002243};
2244
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245/*
2246 * Given a complete unknown PCI device, try to use some heuristics to
2247 * guess what the configuration might be, based on the pitiful PCI
2248 * serial specs. Returns 0 on success, 1 on failure.
2249 */
2250static int __devinit
Russell King1c7c1fe2005-07-27 11:31:19 +01002251serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002252{
Christian Schmidt436bbd42007-08-22 14:01:19 -07002253 const struct pci_device_id *blacklist;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002254 int num_iomem, num_port, first_port = -1, i;
Alan Cox5756ee92008-02-08 04:18:51 -08002255
Linus Torvalds1da177e2005-04-16 15:20:36 -07002256 /*
2257 * If it is not a communications device or the programming
2258 * interface is greater than 6, give up.
2259 *
2260 * (Should we try to make guesses for multiport serial devices
Alan Cox5756ee92008-02-08 04:18:51 -08002261 * later?)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002262 */
2263 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2264 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2265 (dev->class & 0xff) > 6)
2266 return -ENODEV;
2267
Christian Schmidt436bbd42007-08-22 14:01:19 -07002268 /*
2269 * Do not access blacklisted devices that are known not to
2270 * feature serial ports.
2271 */
2272 for (blacklist = softmodem_blacklist;
2273 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2274 blacklist++) {
2275 if (dev->vendor == blacklist->vendor &&
2276 dev->device == blacklist->device)
2277 return -ENODEV;
2278 }
2279
Linus Torvalds1da177e2005-04-16 15:20:36 -07002280 num_iomem = num_port = 0;
2281 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2282 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2283 num_port++;
2284 if (first_port == -1)
2285 first_port = i;
2286 }
2287 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2288 num_iomem++;
2289 }
2290
2291 /*
2292 * If there is 1 or 0 iomem regions, and exactly one port,
2293 * use it. We guess the number of ports based on the IO
2294 * region size.
2295 */
2296 if (num_iomem <= 1 && num_port == 1) {
2297 board->flags = first_port;
2298 board->num_ports = pci_resource_len(dev, first_port) / 8;
2299 return 0;
2300 }
2301
2302 /*
2303 * Now guess if we've got a board which indexes by BARs.
2304 * Each IO BAR should be 8 bytes, and they should follow
2305 * consecutively.
2306 */
2307 first_port = -1;
2308 num_port = 0;
2309 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2310 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2311 pci_resource_len(dev, i) == 8 &&
2312 (first_port == -1 || (first_port + num_port) == i)) {
2313 num_port++;
2314 if (first_port == -1)
2315 first_port = i;
2316 }
2317 }
2318
2319 if (num_port > 1) {
2320 board->flags = first_port | FL_BASE_BARS;
2321 board->num_ports = num_port;
2322 return 0;
2323 }
2324
2325 return -ENODEV;
2326}
2327
2328static inline int
Russell King975a1a72009-01-02 13:44:27 +00002329serial_pci_matches(const struct pciserial_board *board,
2330 const struct pciserial_board *guessed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002331{
2332 return
2333 board->num_ports == guessed->num_ports &&
2334 board->base_baud == guessed->base_baud &&
2335 board->uart_offset == guessed->uart_offset &&
2336 board->reg_shift == guessed->reg_shift &&
2337 board->first_offset == guessed->first_offset;
2338}
2339
Russell King241fc432005-07-27 11:35:54 +01002340struct serial_private *
Russell King975a1a72009-01-02 13:44:27 +00002341pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
Russell King241fc432005-07-27 11:35:54 +01002342{
2343 struct uart_port serial_port;
2344 struct serial_private *priv;
2345 struct pci_serial_quirk *quirk;
2346 int rc, nr_ports, i;
2347
2348 nr_ports = board->num_ports;
2349
2350 /*
2351 * Find an init and setup quirks.
2352 */
2353 quirk = find_quirk(dev);
2354
2355 /*
2356 * Run the new-style initialization function.
2357 * The initialization function returns:
2358 * <0 - error
2359 * 0 - use board->num_ports
2360 * >0 - number of ports
2361 */
2362 if (quirk->init) {
2363 rc = quirk->init(dev);
2364 if (rc < 0) {
2365 priv = ERR_PTR(rc);
2366 goto err_out;
2367 }
2368 if (rc)
2369 nr_ports = rc;
2370 }
2371
Burman Yan8f31bb32007-02-14 00:33:07 -08002372 priv = kzalloc(sizeof(struct serial_private) +
Russell King241fc432005-07-27 11:35:54 +01002373 sizeof(unsigned int) * nr_ports,
2374 GFP_KERNEL);
2375 if (!priv) {
2376 priv = ERR_PTR(-ENOMEM);
2377 goto err_deinit;
2378 }
2379
Russell King241fc432005-07-27 11:35:54 +01002380 priv->dev = dev;
2381 priv->quirk = quirk;
2382
2383 memset(&serial_port, 0, sizeof(struct uart_port));
2384 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2385 serial_port.uartclk = board->base_baud * 16;
2386 serial_port.irq = get_pci_irq(dev, board);
2387 serial_port.dev = &dev->dev;
2388
2389 for (i = 0; i < nr_ports; i++) {
2390 if (quirk->setup(priv, board, &serial_port, i))
2391 break;
2392
2393#ifdef SERIAL_DEBUG_PCI
Lennert Buytenhek80647b92009-11-11 14:26:41 -08002394 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
Russell King241fc432005-07-27 11:35:54 +01002395 serial_port.iobase, serial_port.irq, serial_port.iotype);
2396#endif
Alan Cox5756ee92008-02-08 04:18:51 -08002397
Russell King241fc432005-07-27 11:35:54 +01002398 priv->line[i] = serial8250_register_port(&serial_port);
2399 if (priv->line[i] < 0) {
2400 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2401 break;
2402 }
2403 }
Russell King241fc432005-07-27 11:35:54 +01002404 priv->nr = i;
Russell King241fc432005-07-27 11:35:54 +01002405 return priv;
2406
Alan Cox5756ee92008-02-08 04:18:51 -08002407err_deinit:
Russell King241fc432005-07-27 11:35:54 +01002408 if (quirk->exit)
2409 quirk->exit(dev);
Alan Cox5756ee92008-02-08 04:18:51 -08002410err_out:
Russell King241fc432005-07-27 11:35:54 +01002411 return priv;
2412}
2413EXPORT_SYMBOL_GPL(pciserial_init_ports);
2414
2415void pciserial_remove_ports(struct serial_private *priv)
2416{
2417 struct pci_serial_quirk *quirk;
2418 int i;
2419
2420 for (i = 0; i < priv->nr; i++)
2421 serial8250_unregister_port(priv->line[i]);
2422
2423 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2424 if (priv->remapped_bar[i])
2425 iounmap(priv->remapped_bar[i]);
2426 priv->remapped_bar[i] = NULL;
2427 }
2428
2429 /*
2430 * Find the exit quirks.
2431 */
2432 quirk = find_quirk(priv->dev);
2433 if (quirk->exit)
2434 quirk->exit(priv->dev);
2435
2436 kfree(priv);
2437}
2438EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2439
2440void pciserial_suspend_ports(struct serial_private *priv)
2441{
2442 int i;
2443
2444 for (i = 0; i < priv->nr; i++)
2445 if (priv->line[i] >= 0)
2446 serial8250_suspend_port(priv->line[i]);
2447}
2448EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2449
2450void pciserial_resume_ports(struct serial_private *priv)
2451{
2452 int i;
2453
2454 /*
2455 * Ensure that the board is correctly configured.
2456 */
2457 if (priv->quirk->init)
2458 priv->quirk->init(priv->dev);
2459
2460 for (i = 0; i < priv->nr; i++)
2461 if (priv->line[i] >= 0)
2462 serial8250_resume_port(priv->line[i]);
2463}
2464EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2465
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466/*
2467 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2468 * to the arrangement of serial ports on a PCI card.
2469 */
2470static int __devinit
2471pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2472{
2473 struct serial_private *priv;
Russell King975a1a72009-01-02 13:44:27 +00002474 const struct pciserial_board *board;
2475 struct pciserial_board tmp;
Russell King241fc432005-07-27 11:35:54 +01002476 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002477
2478 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2479 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2480 ent->driver_data);
2481 return -EINVAL;
2482 }
2483
2484 board = &pci_boards[ent->driver_data];
2485
2486 rc = pci_enable_device(dev);
2487 if (rc)
2488 return rc;
2489
2490 if (ent->driver_data == pbn_default) {
2491 /*
2492 * Use a copy of the pci_board entry for this;
2493 * avoid changing entries in the table.
2494 */
Russell King1c7c1fe2005-07-27 11:31:19 +01002495 memcpy(&tmp, board, sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002496 board = &tmp;
2497
2498 /*
2499 * We matched one of our class entries. Try to
2500 * determine the parameters of this board.
2501 */
Russell King975a1a72009-01-02 13:44:27 +00002502 rc = serial_pci_guess_board(dev, &tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002503 if (rc)
2504 goto disable;
2505 } else {
2506 /*
2507 * We matched an explicit entry. If we are able to
2508 * detect this boards settings with our heuristic,
2509 * then we no longer need this entry.
2510 */
Russell King1c7c1fe2005-07-27 11:31:19 +01002511 memcpy(&tmp, &pci_boards[pbn_default],
2512 sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002513 rc = serial_pci_guess_board(dev, &tmp);
2514 if (rc == 0 && serial_pci_matches(board, &tmp))
2515 moan_device("Redundant entry in serial pci_table.",
2516 dev);
2517 }
2518
Russell King241fc432005-07-27 11:35:54 +01002519 priv = pciserial_init_ports(dev, board);
2520 if (!IS_ERR(priv)) {
2521 pci_set_drvdata(dev, priv);
2522 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002523 }
2524
Russell King241fc432005-07-27 11:35:54 +01002525 rc = PTR_ERR(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002526
Linus Torvalds1da177e2005-04-16 15:20:36 -07002527 disable:
2528 pci_disable_device(dev);
2529 return rc;
2530}
2531
2532static void __devexit pciserial_remove_one(struct pci_dev *dev)
2533{
2534 struct serial_private *priv = pci_get_drvdata(dev);
2535
2536 pci_set_drvdata(dev, NULL);
2537
Russell King241fc432005-07-27 11:35:54 +01002538 pciserial_remove_ports(priv);
Russell King056a8762005-07-22 10:15:04 +01002539
2540 pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002541}
2542
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002543#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2545{
2546 struct serial_private *priv = pci_get_drvdata(dev);
2547
Russell King241fc432005-07-27 11:35:54 +01002548 if (priv)
2549 pciserial_suspend_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002550
Linus Torvalds1da177e2005-04-16 15:20:36 -07002551 pci_save_state(dev);
2552 pci_set_power_state(dev, pci_choose_state(dev, state));
2553 return 0;
2554}
2555
2556static int pciserial_resume_one(struct pci_dev *dev)
2557{
Dirk Hohndelccb9d592007-10-29 06:28:17 -07002558 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002559 struct serial_private *priv = pci_get_drvdata(dev);
2560
2561 pci_set_power_state(dev, PCI_D0);
2562 pci_restore_state(dev);
2563
2564 if (priv) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002565 /*
2566 * The device may have been disabled. Re-enable it.
2567 */
Dirk Hohndelccb9d592007-10-29 06:28:17 -07002568 err = pci_enable_device(dev);
Alan Cox40836c42008-10-13 10:36:11 +01002569 /* FIXME: We cannot simply error out here */
Dirk Hohndelccb9d592007-10-29 06:28:17 -07002570 if (err)
Alan Cox40836c42008-10-13 10:36:11 +01002571 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
Russell King241fc432005-07-27 11:35:54 +01002572 pciserial_resume_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002573 }
2574 return 0;
2575}
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002576#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577
2578static struct pci_device_id serial_pci_tbl[] = {
Michael Bramer78d70d42009-01-27 11:51:16 +00002579 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2580 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2581 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2582 pbn_b2_8_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002583 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2584 PCI_SUBVENDOR_ID_CONNECT_TECH,
2585 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2586 pbn_b1_8_1382400 },
2587 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2588 PCI_SUBVENDOR_ID_CONNECT_TECH,
2589 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2590 pbn_b1_4_1382400 },
2591 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2592 PCI_SUBVENDOR_ID_CONNECT_TECH,
2593 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2594 pbn_b1_2_1382400 },
2595 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2596 PCI_SUBVENDOR_ID_CONNECT_TECH,
2597 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2598 pbn_b1_8_1382400 },
2599 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2600 PCI_SUBVENDOR_ID_CONNECT_TECH,
2601 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2602 pbn_b1_4_1382400 },
2603 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2604 PCI_SUBVENDOR_ID_CONNECT_TECH,
2605 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2606 pbn_b1_2_1382400 },
2607 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2608 PCI_SUBVENDOR_ID_CONNECT_TECH,
2609 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2610 pbn_b1_8_921600 },
2611 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2612 PCI_SUBVENDOR_ID_CONNECT_TECH,
2613 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2614 pbn_b1_8_921600 },
2615 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2616 PCI_SUBVENDOR_ID_CONNECT_TECH,
2617 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2618 pbn_b1_4_921600 },
2619 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2620 PCI_SUBVENDOR_ID_CONNECT_TECH,
2621 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2622 pbn_b1_4_921600 },
2623 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2624 PCI_SUBVENDOR_ID_CONNECT_TECH,
2625 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2626 pbn_b1_2_921600 },
2627 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2628 PCI_SUBVENDOR_ID_CONNECT_TECH,
2629 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2630 pbn_b1_8_921600 },
2631 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2632 PCI_SUBVENDOR_ID_CONNECT_TECH,
2633 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2634 pbn_b1_8_921600 },
2635 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2636 PCI_SUBVENDOR_ID_CONNECT_TECH,
2637 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2638 pbn_b1_4_921600 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002639 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2640 PCI_SUBVENDOR_ID_CONNECT_TECH,
2641 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2642 pbn_b1_2_1250000 },
2643 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2644 PCI_SUBVENDOR_ID_CONNECT_TECH,
2645 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2646 pbn_b0_2_1843200 },
2647 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2648 PCI_SUBVENDOR_ID_CONNECT_TECH,
2649 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2650 pbn_b0_4_1843200 },
Yoichi Yuasa85d14942006-02-08 21:46:24 +00002651 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2652 PCI_VENDOR_ID_AFAVLAB,
2653 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2654 pbn_b0_4_1152000 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002655 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2656 PCI_SUBVENDOR_ID_CONNECT_TECH,
2657 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2658 pbn_b0_2_1843200_200 },
2659 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2660 PCI_SUBVENDOR_ID_CONNECT_TECH,
2661 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2662 pbn_b0_4_1843200_200 },
2663 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2664 PCI_SUBVENDOR_ID_CONNECT_TECH,
2665 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2666 pbn_b0_8_1843200_200 },
2667 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2668 PCI_SUBVENDOR_ID_CONNECT_TECH,
2669 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2670 pbn_b0_2_1843200_200 },
2671 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2672 PCI_SUBVENDOR_ID_CONNECT_TECH,
2673 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2674 pbn_b0_4_1843200_200 },
2675 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2676 PCI_SUBVENDOR_ID_CONNECT_TECH,
2677 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2678 pbn_b0_8_1843200_200 },
2679 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2680 PCI_SUBVENDOR_ID_CONNECT_TECH,
2681 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2682 pbn_b0_2_1843200_200 },
2683 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2684 PCI_SUBVENDOR_ID_CONNECT_TECH,
2685 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2686 pbn_b0_4_1843200_200 },
2687 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2688 PCI_SUBVENDOR_ID_CONNECT_TECH,
2689 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2690 pbn_b0_8_1843200_200 },
2691 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2692 PCI_SUBVENDOR_ID_CONNECT_TECH,
2693 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2694 pbn_b0_2_1843200_200 },
2695 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2696 PCI_SUBVENDOR_ID_CONNECT_TECH,
2697 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2698 pbn_b0_4_1843200_200 },
2699 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2700 PCI_SUBVENDOR_ID_CONNECT_TECH,
2701 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2702 pbn_b0_8_1843200_200 },
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07002703 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2704 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2705 0, 0, pbn_exar_ibm_saturn },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002706
2707 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
Alan Cox5756ee92008-02-08 04:18:51 -08002708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002709 pbn_b2_bt_1_115200 },
2710 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
Alan Cox5756ee92008-02-08 04:18:51 -08002711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002712 pbn_b2_bt_2_115200 },
2713 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
Alan Cox5756ee92008-02-08 04:18:51 -08002714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002715 pbn_b2_bt_4_115200 },
2716 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
Alan Cox5756ee92008-02-08 04:18:51 -08002717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002718 pbn_b2_bt_2_115200 },
2719 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
Alan Cox5756ee92008-02-08 04:18:51 -08002720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002721 pbn_b2_bt_4_115200 },
2722 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
Alan Cox5756ee92008-02-08 04:18:51 -08002723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002724 pbn_b2_8_115200 },
Flavio Leitnere65f0f82009-01-02 13:50:43 +00002725 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2727 pbn_b2_8_460800 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002728 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2730 pbn_b2_8_115200 },
2731
2732 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2734 pbn_b2_bt_2_115200 },
2735 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2737 pbn_b2_bt_2_921600 },
2738 /*
2739 * VScom SPCOM800, from sl@s.pl
2740 */
Alan Cox5756ee92008-02-08 04:18:51 -08002741 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002743 pbn_b2_8_921600 },
2744 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
Alan Cox5756ee92008-02-08 04:18:51 -08002745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002746 pbn_b2_4_921600 },
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -07002747 /* Unknown card - subdevice 0x1584 */
2748 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2749 PCI_VENDOR_ID_PLX,
2750 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2751 pbn_b0_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002752 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2753 PCI_SUBVENDOR_ID_KEYSPAN,
2754 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2755 pbn_panacom },
2756 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2758 pbn_panacom4 },
2759 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2761 pbn_panacom2 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08002762 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2763 PCI_VENDOR_ID_ESDGMBH,
2764 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2765 pbn_b2_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002766 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2767 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002768 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002769 pbn_b2_4_460800 },
2770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2771 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002772 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002773 pbn_b2_8_460800 },
2774 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2775 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002776 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002777 pbn_b2_16_460800 },
2778 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2779 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002780 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781 pbn_b2_16_460800 },
2782 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2783 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08002784 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002785 pbn_b2_4_460800 },
2786 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2787 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08002788 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002789 pbn_b2_8_460800 },
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002790 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2791 PCI_SUBVENDOR_ID_EXSYS,
2792 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2793 pbn_exsys_4055 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002794 /*
2795 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2796 * (Exoray@isys.ca)
2797 */
2798 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2799 0x10b5, 0x106a, 0, 0,
2800 pbn_plx_romulus },
2801 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_b1_4_115200 },
2804 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_b1_2_115200 },
2807 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2809 pbn_b1_8_115200 },
2810 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2812 pbn_b1_8_115200 },
2813 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08002814 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2815 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002816 pbn_b0_4_921600 },
2817 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08002818 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2819 0, 0,
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002820 pbn_b0_4_1152000 },
David Ransondb1de152005-07-27 11:43:55 -07002821
2822 /*
2823 * The below card is a little controversial since it is the
2824 * subject of a PCI vendor/device ID clash. (See
2825 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2826 * For now just used the hex ID 0x950a.
2827 */
2828 { PCI_VENDOR_ID_OXSEMI, 0x950a,
Niels de Vos39aced62009-01-02 13:46:58 +00002829 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2830 pbn_b0_2_115200 },
2831 { PCI_VENDOR_ID_OXSEMI, 0x950a,
David Ransondb1de152005-07-27 11:43:55 -07002832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2833 pbn_b0_2_1130000 },
Andre Przywara70fd8fd2009-06-11 12:41:57 +01002834 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2835 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2836 pbn_b0_1_921600 },
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002837 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2839 pbn_b0_4_115200 },
2840 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2842 pbn_b0_bt_2_921600 },
2843
2844 /*
Lee Howard7106b4e2008-10-21 13:48:58 +01002845 * Oxford Semiconductor Inc. Tornado PCI express device range.
2846 */
2847 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849 pbn_b0_1_4000000 },
2850 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852 pbn_b0_1_4000000 },
2853 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855 pbn_oxsemi_1_4000000 },
2856 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858 pbn_oxsemi_1_4000000 },
2859 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2861 pbn_b0_1_4000000 },
2862 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2864 pbn_b0_1_4000000 },
2865 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2867 pbn_oxsemi_1_4000000 },
2868 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2870 pbn_oxsemi_1_4000000 },
2871 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2873 pbn_b0_1_4000000 },
2874 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2876 pbn_b0_1_4000000 },
2877 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2879 pbn_b0_1_4000000 },
2880 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882 pbn_b0_1_4000000 },
2883 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885 pbn_oxsemi_2_4000000 },
2886 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888 pbn_oxsemi_2_4000000 },
2889 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2891 pbn_oxsemi_4_4000000 },
2892 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2894 pbn_oxsemi_4_4000000 },
2895 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_oxsemi_8_4000000 },
2898 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900 pbn_oxsemi_8_4000000 },
2901 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2903 pbn_oxsemi_1_4000000 },
2904 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2906 pbn_oxsemi_1_4000000 },
2907 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2909 pbn_oxsemi_1_4000000 },
2910 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912 pbn_oxsemi_1_4000000 },
2913 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2915 pbn_oxsemi_1_4000000 },
2916 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918 pbn_oxsemi_1_4000000 },
2919 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921 pbn_oxsemi_1_4000000 },
2922 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2924 pbn_oxsemi_1_4000000 },
2925 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2927 pbn_oxsemi_1_4000000 },
2928 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2930 pbn_oxsemi_1_4000000 },
2931 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2933 pbn_oxsemi_1_4000000 },
2934 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2936 pbn_oxsemi_1_4000000 },
2937 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2939 pbn_oxsemi_1_4000000 },
2940 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2942 pbn_oxsemi_1_4000000 },
2943 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2945 pbn_oxsemi_1_4000000 },
2946 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2948 pbn_oxsemi_1_4000000 },
2949 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2951 pbn_oxsemi_1_4000000 },
2952 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2954 pbn_oxsemi_1_4000000 },
2955 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2957 pbn_oxsemi_1_4000000 },
2958 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2960 pbn_oxsemi_1_4000000 },
2961 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2963 pbn_oxsemi_1_4000000 },
2964 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2966 pbn_oxsemi_1_4000000 },
2967 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969 pbn_oxsemi_1_4000000 },
2970 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972 pbn_oxsemi_1_4000000 },
2973 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2975 pbn_oxsemi_1_4000000 },
2976 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2978 pbn_oxsemi_1_4000000 },
Lee Howardb80de362008-10-21 13:50:14 +01002979 /*
2980 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2981 */
2982 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2983 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2984 pbn_oxsemi_1_4000000 },
2985 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2986 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2987 pbn_oxsemi_2_4000000 },
2988 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2989 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2990 pbn_oxsemi_4_4000000 },
2991 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2992 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2993 pbn_oxsemi_8_4000000 },
Lee Howard7106b4e2008-10-21 13:48:58 +01002994 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002995 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2996 * from skokodyn@yahoo.com
2997 */
2998 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2999 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3000 pbn_sbsxrsio },
3001 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3002 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3003 pbn_sbsxrsio },
3004 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3005 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3006 pbn_sbsxrsio },
3007 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3008 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3009 pbn_sbsxrsio },
3010
3011 /*
3012 * Digitan DS560-558, from jimd@esoft.com
3013 */
3014 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
Alan Cox5756ee92008-02-08 04:18:51 -08003015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003016 pbn_b1_1_115200 },
3017
3018 /*
3019 * Titan Electronic cards
3020 * The 400L and 800L have a custom setup quirk.
3021 */
3022 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
Alan Cox5756ee92008-02-08 04:18:51 -08003023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003024 pbn_b0_1_921600 },
3025 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
Alan Cox5756ee92008-02-08 04:18:51 -08003026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003027 pbn_b0_2_921600 },
3028 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
Alan Cox5756ee92008-02-08 04:18:51 -08003029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003030 pbn_b0_4_921600 },
3031 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
Alan Cox5756ee92008-02-08 04:18:51 -08003032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003033 pbn_b0_4_921600 },
3034 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036 pbn_b1_1_921600 },
3037 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039 pbn_b1_bt_2_921600 },
3040 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042 pbn_b0_bt_4_921600 },
3043 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045 pbn_b0_bt_8_921600 },
3046
3047 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3049 pbn_b2_1_460800 },
3050 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052 pbn_b2_1_460800 },
3053 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055 pbn_b2_1_460800 },
3056 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3058 pbn_b2_bt_2_921600 },
3059 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3061 pbn_b2_bt_2_921600 },
3062 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064 pbn_b2_bt_2_921600 },
3065 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3067 pbn_b2_bt_4_921600 },
3068 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_b2_bt_4_921600 },
3071 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3073 pbn_b2_bt_4_921600 },
3074 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3076 pbn_b0_1_921600 },
3077 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079 pbn_b0_1_921600 },
3080 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082 pbn_b0_1_921600 },
3083 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085 pbn_b0_bt_2_921600 },
3086 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_b0_bt_2_921600 },
3089 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_b0_bt_2_921600 },
3092 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094 pbn_b0_bt_4_921600 },
3095 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_b0_bt_4_921600 },
3098 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_b0_bt_4_921600 },
Andrey Panin3ec9c592006-02-02 20:15:09 +00003101 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3103 pbn_b0_bt_8_921600 },
3104 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106 pbn_b0_bt_8_921600 },
3107 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3109 pbn_b0_bt_8_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110
3111 /*
3112 * Computone devices submitted by Doug McNash dmcnash@computone.com
3113 */
3114 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3115 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3116 0, 0, pbn_computone_4 },
3117 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3118 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3119 0, 0, pbn_computone_8 },
3120 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3121 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3122 0, 0, pbn_computone_6 },
3123
3124 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_oxsemi },
3127 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3128 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3129 pbn_b0_bt_1_921600 },
3130
3131 /*
3132 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3133 */
3134 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136 pbn_b0_bt_8_115200 },
3137 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_b0_bt_8_115200 },
3140
3141 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143 pbn_b0_bt_2_115200 },
3144 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146 pbn_b0_bt_2_115200 },
3147 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149 pbn_b0_bt_2_115200 },
Lennert Buytenhekb87e5e22009-11-11 14:26:42 -08003150 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_b0_bt_2_115200 },
3153 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155 pbn_b0_bt_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003156 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158 pbn_b0_bt_4_460800 },
3159 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161 pbn_b0_bt_4_460800 },
3162 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164 pbn_b0_bt_2_460800 },
3165 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167 pbn_b0_bt_2_460800 },
3168 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170 pbn_b0_bt_2_460800 },
3171 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_b0_bt_1_115200 },
3174 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176 pbn_b0_bt_1_460800 },
3177
3178 /*
Russell King1fb8cac2006-12-13 14:45:46 +00003179 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3180 * Cards are identified by their subsystem vendor IDs, which
3181 * (in hex) match the model number.
3182 *
3183 * Note that JC140x are RS422/485 cards which require ox950
3184 * ACR = 0x10, and as such are not currently fully supported.
3185 */
3186 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3187 0x1204, 0x0004, 0, 0,
3188 pbn_b0_4_921600 },
3189 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3190 0x1208, 0x0004, 0, 0,
3191 pbn_b0_4_921600 },
3192/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3193 0x1402, 0x0002, 0, 0,
3194 pbn_b0_2_921600 }, */
3195/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3196 0x1404, 0x0004, 0, 0,
3197 pbn_b0_4_921600 }, */
3198 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3199 0x1208, 0x0004, 0, 0,
3200 pbn_b0_4_921600 },
3201
Kiros Yeh2a52fcb2009-12-21 16:26:48 -08003202 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3203 0x1204, 0x0004, 0, 0,
3204 pbn_b0_4_921600 },
3205 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3206 0x1208, 0x0004, 0, 0,
3207 pbn_b0_4_921600 },
3208 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3209 0x1208, 0x0004, 0, 0,
3210 pbn_b0_4_921600 },
Russell King1fb8cac2006-12-13 14:45:46 +00003211 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003212 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3213 */
3214 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216 pbn_b1_1_1382400 },
3217
3218 /*
3219 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3220 */
3221 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b1_1_1382400 },
3224
3225 /*
3226 * RAStel 2 port modem, gerg@moreton.com.au
3227 */
3228 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_b2_bt_2_115200 },
3231
3232 /*
3233 * EKF addition for i960 Boards form EKF with serial port
3234 */
3235 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3236 0xE4BF, PCI_ANY_ID, 0, 0,
3237 pbn_intel_i960 },
3238
3239 /*
3240 * Xircom Cardbus/Ethernet combos
3241 */
3242 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_b0_1_115200 },
3245 /*
3246 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3247 */
3248 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_b0_1_115200 },
3251
3252 /*
3253 * Untested PCI modems, sent in from various folks...
3254 */
3255
3256 /*
3257 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3258 */
3259 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3260 0x1048, 0x1500, 0, 0,
3261 pbn_b1_1_115200 },
3262
3263 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3264 0xFF00, 0, 0, 0,
3265 pbn_sgi_ioc3 },
3266
3267 /*
3268 * HP Diva card
3269 */
3270 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3271 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3272 pbn_b1_1_115200 },
3273 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_b0_5_115200 },
3276 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b2_1_115200 },
3279
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00003280 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282 pbn_b3_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003283 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3285 pbn_b3_4_115200 },
3286 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3288 pbn_b3_8_115200 },
3289
3290 /*
3291 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3292 */
3293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3294 PCI_ANY_ID, PCI_ANY_ID,
3295 0,
3296 0, pbn_exar_XR17C152 },
3297 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3298 PCI_ANY_ID, PCI_ANY_ID,
3299 0,
3300 0, pbn_exar_XR17C154 },
3301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3302 PCI_ANY_ID, PCI_ANY_ID,
3303 0,
3304 0, pbn_exar_XR17C158 },
3305
3306 /*
3307 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3308 */
3309 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_b0_1_115200 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07003312 /*
3313 * ITE
3314 */
3315 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3316 PCI_ANY_ID, PCI_ANY_ID,
3317 0, 0,
3318 pbn_b1_bt_1_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003319
3320 /*
Peter Horton737c1752006-08-26 09:07:36 +01003321 * IntaShield IS-200
3322 */
3323 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3325 pbn_b2_2_115200 },
Ignacio García Pérez4b6f6ce2008-05-23 13:04:28 -07003326 /*
3327 * IntaShield IS-400
3328 */
3329 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3331 pbn_b2_4_115200 },
Peter Horton737c1752006-08-26 09:07:36 +01003332 /*
Thomas Hoehn48212002007-02-10 01:46:05 -08003333 * Perle PCI-RAS cards
3334 */
3335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3336 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3337 0, 0, pbn_b2_4_921600 },
3338 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3339 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3340 0, 0, pbn_b2_8_921600 },
Alan Coxbf0df632007-10-16 01:24:00 -07003341
3342 /*
3343 * Mainpine series cards: Fairly standard layout but fools
3344 * parts of the autodetect in some cases and uses otherwise
3345 * unmatched communications subclasses in the PCI Express case
3346 */
3347
3348 { /* RockForceDUO */
3349 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3350 PCI_VENDOR_ID_MAINPINE, 0x0200,
3351 0, 0, pbn_b0_2_115200 },
3352 { /* RockForceQUATRO */
3353 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3354 PCI_VENDOR_ID_MAINPINE, 0x0300,
3355 0, 0, pbn_b0_4_115200 },
3356 { /* RockForceDUO+ */
3357 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3358 PCI_VENDOR_ID_MAINPINE, 0x0400,
3359 0, 0, pbn_b0_2_115200 },
3360 { /* RockForceQUATRO+ */
3361 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3362 PCI_VENDOR_ID_MAINPINE, 0x0500,
3363 0, 0, pbn_b0_4_115200 },
3364 { /* RockForce+ */
3365 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3366 PCI_VENDOR_ID_MAINPINE, 0x0600,
3367 0, 0, pbn_b0_2_115200 },
3368 { /* RockForce+ */
3369 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3370 PCI_VENDOR_ID_MAINPINE, 0x0700,
3371 0, 0, pbn_b0_4_115200 },
3372 { /* RockForceOCTO+ */
3373 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3374 PCI_VENDOR_ID_MAINPINE, 0x0800,
3375 0, 0, pbn_b0_8_115200 },
3376 { /* RockForceDUO+ */
3377 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3378 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3379 0, 0, pbn_b0_2_115200 },
3380 { /* RockForceQUARTRO+ */
3381 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3382 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3383 0, 0, pbn_b0_4_115200 },
3384 { /* RockForceOCTO+ */
3385 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3386 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3387 0, 0, pbn_b0_8_115200 },
3388 { /* RockForceD1 */
3389 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3390 PCI_VENDOR_ID_MAINPINE, 0x2000,
3391 0, 0, pbn_b0_1_115200 },
3392 { /* RockForceF1 */
3393 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3394 PCI_VENDOR_ID_MAINPINE, 0x2100,
3395 0, 0, pbn_b0_1_115200 },
3396 { /* RockForceD2 */
3397 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3398 PCI_VENDOR_ID_MAINPINE, 0x2200,
3399 0, 0, pbn_b0_2_115200 },
3400 { /* RockForceF2 */
3401 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3402 PCI_VENDOR_ID_MAINPINE, 0x2300,
3403 0, 0, pbn_b0_2_115200 },
3404 { /* RockForceD4 */
3405 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3406 PCI_VENDOR_ID_MAINPINE, 0x2400,
3407 0, 0, pbn_b0_4_115200 },
3408 { /* RockForceF4 */
3409 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3410 PCI_VENDOR_ID_MAINPINE, 0x2500,
3411 0, 0, pbn_b0_4_115200 },
3412 { /* RockForceD8 */
3413 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3414 PCI_VENDOR_ID_MAINPINE, 0x2600,
3415 0, 0, pbn_b0_8_115200 },
3416 { /* RockForceF8 */
3417 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3418 PCI_VENDOR_ID_MAINPINE, 0x2700,
3419 0, 0, pbn_b0_8_115200 },
3420 { /* IQ Express D1 */
3421 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3422 PCI_VENDOR_ID_MAINPINE, 0x3000,
3423 0, 0, pbn_b0_1_115200 },
3424 { /* IQ Express F1 */
3425 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3426 PCI_VENDOR_ID_MAINPINE, 0x3100,
3427 0, 0, pbn_b0_1_115200 },
3428 { /* IQ Express D2 */
3429 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3430 PCI_VENDOR_ID_MAINPINE, 0x3200,
3431 0, 0, pbn_b0_2_115200 },
3432 { /* IQ Express F2 */
3433 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3434 PCI_VENDOR_ID_MAINPINE, 0x3300,
3435 0, 0, pbn_b0_2_115200 },
3436 { /* IQ Express D4 */
3437 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3438 PCI_VENDOR_ID_MAINPINE, 0x3400,
3439 0, 0, pbn_b0_4_115200 },
3440 { /* IQ Express F4 */
3441 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3442 PCI_VENDOR_ID_MAINPINE, 0x3500,
3443 0, 0, pbn_b0_4_115200 },
3444 { /* IQ Express D8 */
3445 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3446 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3447 0, 0, pbn_b0_8_115200 },
3448 { /* IQ Express F8 */
3449 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3450 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3451 0, 0, pbn_b0_8_115200 },
3452
3453
Thomas Hoehn48212002007-02-10 01:46:05 -08003454 /*
Olof Johanssonaa798502007-08-22 14:01:55 -07003455 * PA Semi PA6T-1682M on-chip UART
3456 */
3457 { PCI_VENDOR_ID_PASEMI, 0xa004,
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459 pbn_pasemi_1682M },
3460
3461 /*
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01003462 * National Instruments
3463 */
Will Page04bf7e72009-04-06 17:32:15 +01003464 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 pbn_b1_16_115200 },
3467 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469 pbn_b1_8_115200 },
3470 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_b1_bt_4_115200 },
3473 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_b1_bt_2_115200 },
3476 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_b1_bt_4_115200 },
3479 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_b1_bt_2_115200 },
3482 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_b1_16_115200 },
3485 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_b1_8_115200 },
3488 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_b1_bt_4_115200 },
3491 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b1_bt_2_115200 },
3494 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b1_bt_4_115200 },
3497 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499 pbn_b1_bt_2_115200 },
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01003500 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_ni8430_2 },
3503 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505 pbn_ni8430_2 },
3506 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3508 pbn_ni8430_4 },
3509 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3511 pbn_ni8430_4 },
3512 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3514 pbn_ni8430_8 },
3515 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3517 pbn_ni8430_8 },
3518 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3520 pbn_ni8430_16 },
3521 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3523 pbn_ni8430_16 },
3524 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526 pbn_ni8430_2 },
3527 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529 pbn_ni8430_2 },
3530 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3532 pbn_ni8430_4 },
3533 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535 pbn_ni8430_4 },
3536
3537 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08003538 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3539 */
3540 { PCI_VENDOR_ID_ADDIDATA,
3541 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3542 PCI_ANY_ID,
3543 PCI_ANY_ID,
3544 0,
3545 0,
3546 pbn_b0_4_115200 },
3547
3548 { PCI_VENDOR_ID_ADDIDATA,
3549 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3550 PCI_ANY_ID,
3551 PCI_ANY_ID,
3552 0,
3553 0,
3554 pbn_b0_2_115200 },
3555
3556 { PCI_VENDOR_ID_ADDIDATA,
3557 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3558 PCI_ANY_ID,
3559 PCI_ANY_ID,
3560 0,
3561 0,
3562 pbn_b0_1_115200 },
3563
3564 { PCI_VENDOR_ID_ADDIDATA_OLD,
3565 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3566 PCI_ANY_ID,
3567 PCI_ANY_ID,
3568 0,
3569 0,
3570 pbn_b1_8_115200 },
3571
3572 { PCI_VENDOR_ID_ADDIDATA,
3573 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3574 PCI_ANY_ID,
3575 PCI_ANY_ID,
3576 0,
3577 0,
3578 pbn_b0_4_115200 },
3579
3580 { PCI_VENDOR_ID_ADDIDATA,
3581 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3582 PCI_ANY_ID,
3583 PCI_ANY_ID,
3584 0,
3585 0,
3586 pbn_b0_2_115200 },
3587
3588 { PCI_VENDOR_ID_ADDIDATA,
3589 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3590 PCI_ANY_ID,
3591 PCI_ANY_ID,
3592 0,
3593 0,
3594 pbn_b0_1_115200 },
3595
3596 { PCI_VENDOR_ID_ADDIDATA,
3597 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3598 PCI_ANY_ID,
3599 PCI_ANY_ID,
3600 0,
3601 0,
3602 pbn_b0_4_115200 },
3603
3604 { PCI_VENDOR_ID_ADDIDATA,
3605 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3606 PCI_ANY_ID,
3607 PCI_ANY_ID,
3608 0,
3609 0,
3610 pbn_b0_2_115200 },
3611
3612 { PCI_VENDOR_ID_ADDIDATA,
3613 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3614 PCI_ANY_ID,
3615 PCI_ANY_ID,
3616 0,
3617 0,
3618 pbn_b0_1_115200 },
3619
3620 { PCI_VENDOR_ID_ADDIDATA,
3621 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3622 PCI_ANY_ID,
3623 PCI_ANY_ID,
3624 0,
3625 0,
3626 pbn_b0_8_115200 },
3627
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07003628 { PCI_VENDOR_ID_ADDIDATA,
3629 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3630 PCI_ANY_ID,
3631 PCI_ANY_ID,
3632 0,
3633 0,
3634 pbn_ADDIDATA_PCIe_4_3906250 },
3635
3636 { PCI_VENDOR_ID_ADDIDATA,
3637 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3638 PCI_ANY_ID,
3639 PCI_ANY_ID,
3640 0,
3641 0,
3642 pbn_ADDIDATA_PCIe_2_3906250 },
3643
3644 { PCI_VENDOR_ID_ADDIDATA,
3645 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3646 PCI_ANY_ID,
3647 PCI_ANY_ID,
3648 0,
3649 0,
3650 pbn_ADDIDATA_PCIe_1_3906250 },
3651
3652 { PCI_VENDOR_ID_ADDIDATA,
3653 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3654 PCI_ANY_ID,
3655 PCI_ANY_ID,
3656 0,
3657 0,
3658 pbn_ADDIDATA_PCIe_8_3906250 },
3659
Jiri Slaby25cf9bc2009-01-15 13:30:34 +00003660 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3661 PCI_VENDOR_ID_IBM, 0x0299,
3662 0, 0, pbn_b0_bt_2_115200 },
3663
Michael Bueschc4285b42009-06-30 11:41:21 -07003664 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3665 0xA000, 0x1000,
3666 0, 0, pbn_b0_1_115200 },
3667
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08003668 /*
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08003669 * Best Connectivity PCI Multi I/O cards
3670 */
3671
3672 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3673 0xA000, 0x1000,
3674 0, 0, pbn_b0_1_115200 },
3675
3676 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3677 0xA000, 0x3004,
3678 0, 0, pbn_b0_bt_4_115200 },
3679
3680 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003681 * These entries match devices with class COMMUNICATION_SERIAL,
3682 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3683 */
3684 { PCI_ANY_ID, PCI_ANY_ID,
3685 PCI_ANY_ID, PCI_ANY_ID,
3686 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3687 0xffff00, pbn_default },
3688 { PCI_ANY_ID, PCI_ANY_ID,
3689 PCI_ANY_ID, PCI_ANY_ID,
3690 PCI_CLASS_COMMUNICATION_MODEM << 8,
3691 0xffff00, pbn_default },
3692 { PCI_ANY_ID, PCI_ANY_ID,
3693 PCI_ANY_ID, PCI_ANY_ID,
3694 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3695 0xffff00, pbn_default },
3696 { 0, }
3697};
3698
3699static struct pci_driver serial_pci_driver = {
3700 .name = "serial",
3701 .probe = pciserial_init_one,
3702 .remove = __devexit_p(pciserial_remove_one),
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07003703#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07003704 .suspend = pciserial_suspend_one,
3705 .resume = pciserial_resume_one,
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07003706#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003707 .id_table = serial_pci_tbl,
3708};
3709
3710static int __init serial8250_pci_init(void)
3711{
3712 return pci_register_driver(&serial_pci_driver);
3713}
3714
3715static void __exit serial8250_pci_exit(void)
3716{
3717 pci_unregister_driver(&serial_pci_driver);
3718}
3719
3720module_init(serial8250_pci_init);
3721module_exit(serial8250_pci_exit);
3722
3723MODULE_LICENSE("GPL");
3724MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3725MODULE_DEVICE_TABLE(pci, serial_pci_tbl);